p6.c 6.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280
  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <linux/perf_event.h>
  3. #include <linux/types.h>
  4. #include "../perf_event.h"
  5. /*
  6. * Not sure about some of these
  7. */
  8. static const u64 p6_perfmon_event_map[] =
  9. {
  10. [PERF_COUNT_HW_CPU_CYCLES] = 0x0079, /* CPU_CLK_UNHALTED */
  11. [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, /* INST_RETIRED */
  12. [PERF_COUNT_HW_CACHE_REFERENCES] = 0x0f2e, /* L2_RQSTS:M:E:S:I */
  13. [PERF_COUNT_HW_CACHE_MISSES] = 0x012e, /* L2_RQSTS:I */
  14. [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4, /* BR_INST_RETIRED */
  15. [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5, /* BR_MISS_PRED_RETIRED */
  16. [PERF_COUNT_HW_BUS_CYCLES] = 0x0062, /* BUS_DRDY_CLOCKS */
  17. [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a2, /* RESOURCE_STALLS */
  18. };
  19. static const u64 __initconst p6_hw_cache_event_ids
  20. [PERF_COUNT_HW_CACHE_MAX]
  21. [PERF_COUNT_HW_CACHE_OP_MAX]
  22. [PERF_COUNT_HW_CACHE_RESULT_MAX] =
  23. {
  24. [ C(L1D) ] = {
  25. [ C(OP_READ) ] = {
  26. [ C(RESULT_ACCESS) ] = 0x0043, /* DATA_MEM_REFS */
  27. [ C(RESULT_MISS) ] = 0x0045, /* DCU_LINES_IN */
  28. },
  29. [ C(OP_WRITE) ] = {
  30. [ C(RESULT_ACCESS) ] = 0,
  31. [ C(RESULT_MISS) ] = 0x0f29, /* L2_LD:M:E:S:I */
  32. },
  33. [ C(OP_PREFETCH) ] = {
  34. [ C(RESULT_ACCESS) ] = 0,
  35. [ C(RESULT_MISS) ] = 0,
  36. },
  37. },
  38. [ C(L1I ) ] = {
  39. [ C(OP_READ) ] = {
  40. [ C(RESULT_ACCESS) ] = 0x0080, /* IFU_IFETCH */
  41. [ C(RESULT_MISS) ] = 0x0f28, /* L2_IFETCH:M:E:S:I */
  42. },
  43. [ C(OP_WRITE) ] = {
  44. [ C(RESULT_ACCESS) ] = -1,
  45. [ C(RESULT_MISS) ] = -1,
  46. },
  47. [ C(OP_PREFETCH) ] = {
  48. [ C(RESULT_ACCESS) ] = 0,
  49. [ C(RESULT_MISS) ] = 0,
  50. },
  51. },
  52. [ C(LL ) ] = {
  53. [ C(OP_READ) ] = {
  54. [ C(RESULT_ACCESS) ] = 0,
  55. [ C(RESULT_MISS) ] = 0,
  56. },
  57. [ C(OP_WRITE) ] = {
  58. [ C(RESULT_ACCESS) ] = 0,
  59. [ C(RESULT_MISS) ] = 0x0025, /* L2_M_LINES_INM */
  60. },
  61. [ C(OP_PREFETCH) ] = {
  62. [ C(RESULT_ACCESS) ] = 0,
  63. [ C(RESULT_MISS) ] = 0,
  64. },
  65. },
  66. [ C(DTLB) ] = {
  67. [ C(OP_READ) ] = {
  68. [ C(RESULT_ACCESS) ] = 0x0043, /* DATA_MEM_REFS */
  69. [ C(RESULT_MISS) ] = 0,
  70. },
  71. [ C(OP_WRITE) ] = {
  72. [ C(RESULT_ACCESS) ] = 0,
  73. [ C(RESULT_MISS) ] = 0,
  74. },
  75. [ C(OP_PREFETCH) ] = {
  76. [ C(RESULT_ACCESS) ] = 0,
  77. [ C(RESULT_MISS) ] = 0,
  78. },
  79. },
  80. [ C(ITLB) ] = {
  81. [ C(OP_READ) ] = {
  82. [ C(RESULT_ACCESS) ] = 0x0080, /* IFU_IFETCH */
  83. [ C(RESULT_MISS) ] = 0x0085, /* ITLB_MISS */
  84. },
  85. [ C(OP_WRITE) ] = {
  86. [ C(RESULT_ACCESS) ] = -1,
  87. [ C(RESULT_MISS) ] = -1,
  88. },
  89. [ C(OP_PREFETCH) ] = {
  90. [ C(RESULT_ACCESS) ] = -1,
  91. [ C(RESULT_MISS) ] = -1,
  92. },
  93. },
  94. [ C(BPU ) ] = {
  95. [ C(OP_READ) ] = {
  96. [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED */
  97. [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISS_PRED_RETIRED */
  98. },
  99. [ C(OP_WRITE) ] = {
  100. [ C(RESULT_ACCESS) ] = -1,
  101. [ C(RESULT_MISS) ] = -1,
  102. },
  103. [ C(OP_PREFETCH) ] = {
  104. [ C(RESULT_ACCESS) ] = -1,
  105. [ C(RESULT_MISS) ] = -1,
  106. },
  107. },
  108. };
  109. static u64 p6_pmu_event_map(int hw_event)
  110. {
  111. return p6_perfmon_event_map[hw_event];
  112. }
  113. /*
  114. * Event setting that is specified not to count anything.
  115. * We use this to effectively disable a counter.
  116. *
  117. * L2_RQSTS with 0 MESI unit mask.
  118. */
  119. #define P6_NOP_EVENT 0x0000002EULL
  120. static struct event_constraint p6_event_constraints[] =
  121. {
  122. INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FLOPS */
  123. INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
  124. INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
  125. INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
  126. INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
  127. INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
  128. EVENT_CONSTRAINT_END
  129. };
  130. static void p6_pmu_disable_all(void)
  131. {
  132. u64 val;
  133. /* p6 only has one enable register */
  134. rdmsrl(MSR_P6_EVNTSEL0, val);
  135. val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
  136. wrmsrl(MSR_P6_EVNTSEL0, val);
  137. }
  138. static void p6_pmu_enable_all(int added)
  139. {
  140. unsigned long val;
  141. /* p6 only has one enable register */
  142. rdmsrl(MSR_P6_EVNTSEL0, val);
  143. val |= ARCH_PERFMON_EVENTSEL_ENABLE;
  144. wrmsrl(MSR_P6_EVNTSEL0, val);
  145. }
  146. static inline void
  147. p6_pmu_disable_event(struct perf_event *event)
  148. {
  149. struct hw_perf_event *hwc = &event->hw;
  150. u64 val = P6_NOP_EVENT;
  151. (void)wrmsrl_safe(hwc->config_base, val);
  152. }
  153. static void p6_pmu_enable_event(struct perf_event *event)
  154. {
  155. struct hw_perf_event *hwc = &event->hw;
  156. u64 val;
  157. val = hwc->config;
  158. /*
  159. * p6 only has a global event enable, set on PerfEvtSel0
  160. * We "disable" events by programming P6_NOP_EVENT
  161. * and we rely on p6_pmu_enable_all() being called
  162. * to actually enable the events.
  163. */
  164. (void)wrmsrl_safe(hwc->config_base, val);
  165. }
  166. PMU_FORMAT_ATTR(event, "config:0-7" );
  167. PMU_FORMAT_ATTR(umask, "config:8-15" );
  168. PMU_FORMAT_ATTR(edge, "config:18" );
  169. PMU_FORMAT_ATTR(pc, "config:19" );
  170. PMU_FORMAT_ATTR(inv, "config:23" );
  171. PMU_FORMAT_ATTR(cmask, "config:24-31" );
  172. static struct attribute *intel_p6_formats_attr[] = {
  173. &format_attr_event.attr,
  174. &format_attr_umask.attr,
  175. &format_attr_edge.attr,
  176. &format_attr_pc.attr,
  177. &format_attr_inv.attr,
  178. &format_attr_cmask.attr,
  179. NULL,
  180. };
  181. static __initconst const struct x86_pmu p6_pmu = {
  182. .name = "p6",
  183. .handle_irq = x86_pmu_handle_irq,
  184. .disable_all = p6_pmu_disable_all,
  185. .enable_all = p6_pmu_enable_all,
  186. .enable = p6_pmu_enable_event,
  187. .disable = p6_pmu_disable_event,
  188. .hw_config = x86_pmu_hw_config,
  189. .schedule_events = x86_schedule_events,
  190. .eventsel = MSR_P6_EVNTSEL0,
  191. .perfctr = MSR_P6_PERFCTR0,
  192. .event_map = p6_pmu_event_map,
  193. .max_events = ARRAY_SIZE(p6_perfmon_event_map),
  194. .apic = 1,
  195. .max_period = (1ULL << 31) - 1,
  196. .version = 0,
  197. .num_counters = 2,
  198. /*
  199. * Events have 40 bits implemented. However they are designed such
  200. * that bits [32-39] are sign extensions of bit 31. As such the
  201. * effective width of a event for P6-like PMU is 32 bits only.
  202. *
  203. * See IA-32 Intel Architecture Software developer manual Vol 3B
  204. */
  205. .cntval_bits = 32,
  206. .cntval_mask = (1ULL << 32) - 1,
  207. .get_event_constraints = x86_get_event_constraints,
  208. .event_constraints = p6_event_constraints,
  209. .format_attrs = intel_p6_formats_attr,
  210. .events_sysfs_show = intel_event_sysfs_show,
  211. };
  212. static __init void p6_pmu_rdpmc_quirk(void)
  213. {
  214. if (boot_cpu_data.x86_stepping < 9) {
  215. /*
  216. * PPro erratum 26; fixed in stepping 9 and above.
  217. */
  218. pr_warn("Userspace RDPMC support disabled due to a CPU erratum\n");
  219. x86_pmu.attr_rdpmc_broken = 1;
  220. x86_pmu.attr_rdpmc = 0;
  221. }
  222. }
  223. __init int p6_pmu_init(void)
  224. {
  225. x86_pmu = p6_pmu;
  226. switch (boot_cpu_data.x86_model) {
  227. case 1: /* Pentium Pro */
  228. x86_add_quirk(p6_pmu_rdpmc_quirk);
  229. break;
  230. case 3: /* Pentium II - Klamath */
  231. case 5: /* Pentium II - Deschutes */
  232. case 6: /* Pentium II - Mendocino */
  233. break;
  234. case 7: /* Pentium III - Katmai */
  235. case 8: /* Pentium III - Coppermine */
  236. case 10: /* Pentium III Xeon */
  237. case 11: /* Pentium III - Tualatin */
  238. break;
  239. case 9: /* Pentium M - Banias */
  240. case 13: /* Pentium M - Dothan */
  241. break;
  242. default:
  243. pr_cont("unsupported p6 CPU model %d ", boot_cpu_data.x86_model);
  244. return -ENODEV;
  245. }
  246. memcpy(hw_cache_event_ids, p6_hw_cache_event_ids,
  247. sizeof(hw_cache_event_ids));
  248. return 0;
  249. }