ds.c 66 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <linux/bitops.h>
  3. #include <linux/types.h>
  4. #include <linux/slab.h>
  5. #include <linux/sched/clock.h>
  6. #include <asm/cpu_entry_area.h>
  7. #include <asm/perf_event.h>
  8. #include <asm/tlbflush.h>
  9. #include <asm/insn.h>
  10. #include <asm/io.h>
  11. #include <asm/timer.h>
  12. #include "../perf_event.h"
  13. /* Waste a full page so it can be mapped into the cpu_entry_area */
  14. DEFINE_PER_CPU_PAGE_ALIGNED(struct debug_store, cpu_debug_store);
  15. /* The size of a BTS record in bytes: */
  16. #define BTS_RECORD_SIZE 24
  17. #define PEBS_FIXUP_SIZE PAGE_SIZE
  18. /*
  19. * pebs_record_32 for p4 and core not supported
  20. struct pebs_record_32 {
  21. u32 flags, ip;
  22. u32 ax, bc, cx, dx;
  23. u32 si, di, bp, sp;
  24. };
  25. */
  26. union intel_x86_pebs_dse {
  27. u64 val;
  28. struct {
  29. unsigned int ld_dse:4;
  30. unsigned int ld_stlb_miss:1;
  31. unsigned int ld_locked:1;
  32. unsigned int ld_data_blk:1;
  33. unsigned int ld_addr_blk:1;
  34. unsigned int ld_reserved:24;
  35. };
  36. struct {
  37. unsigned int st_l1d_hit:1;
  38. unsigned int st_reserved1:3;
  39. unsigned int st_stlb_miss:1;
  40. unsigned int st_locked:1;
  41. unsigned int st_reserved2:26;
  42. };
  43. struct {
  44. unsigned int st_lat_dse:4;
  45. unsigned int st_lat_stlb_miss:1;
  46. unsigned int st_lat_locked:1;
  47. unsigned int ld_reserved3:26;
  48. };
  49. };
  50. /*
  51. * Map PEBS Load Latency Data Source encodings to generic
  52. * memory data source information
  53. */
  54. #define P(a, b) PERF_MEM_S(a, b)
  55. #define OP_LH (P(OP, LOAD) | P(LVL, HIT))
  56. #define LEVEL(x) P(LVLNUM, x)
  57. #define REM P(REMOTE, REMOTE)
  58. #define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
  59. /* Version for Sandy Bridge and later */
  60. static u64 pebs_data_source[] = {
  61. P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
  62. OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* 0x01: L1 local */
  63. OP_LH | P(LVL, LFB) | LEVEL(LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */
  64. OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x03: L2 hit */
  65. OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
  66. OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
  67. OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
  68. OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
  69. OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
  70. OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
  71. OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */
  72. OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
  73. OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | SNOOP_NONE_MISS, /* 0x0c: L3 miss, excl */
  74. OP_LH | P(LVL, REM_RAM1) | LEVEL(RAM) | REM | SNOOP_NONE_MISS, /* 0x0d: L3 miss, excl */
  75. OP_LH | P(LVL, IO) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0e: I/O */
  76. OP_LH | P(LVL, UNC) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0f: uncached */
  77. };
  78. /* Patch up minor differences in the bits */
  79. void __init intel_pmu_pebs_data_source_nhm(void)
  80. {
  81. pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT);
  82. pebs_data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
  83. pebs_data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
  84. }
  85. static void __init __intel_pmu_pebs_data_source_skl(bool pmem, u64 *data_source)
  86. {
  87. u64 pmem_or_l4 = pmem ? LEVEL(PMEM) : LEVEL(L4);
  88. data_source[0x08] = OP_LH | pmem_or_l4 | P(SNOOP, HIT);
  89. data_source[0x09] = OP_LH | pmem_or_l4 | REM | P(SNOOP, HIT);
  90. data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE);
  91. data_source[0x0c] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOPX, FWD);
  92. data_source[0x0d] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOP, HITM);
  93. }
  94. void __init intel_pmu_pebs_data_source_skl(bool pmem)
  95. {
  96. __intel_pmu_pebs_data_source_skl(pmem, pebs_data_source);
  97. }
  98. static void __init __intel_pmu_pebs_data_source_grt(u64 *data_source)
  99. {
  100. data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT);
  101. data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
  102. data_source[0x08] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD);
  103. }
  104. void __init intel_pmu_pebs_data_source_grt(void)
  105. {
  106. __intel_pmu_pebs_data_source_grt(pebs_data_source);
  107. }
  108. void __init intel_pmu_pebs_data_source_adl(void)
  109. {
  110. u64 *data_source;
  111. data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].pebs_data_source;
  112. memcpy(data_source, pebs_data_source, sizeof(pebs_data_source));
  113. __intel_pmu_pebs_data_source_skl(false, data_source);
  114. data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX].pebs_data_source;
  115. memcpy(data_source, pebs_data_source, sizeof(pebs_data_source));
  116. __intel_pmu_pebs_data_source_grt(data_source);
  117. }
  118. static u64 precise_store_data(u64 status)
  119. {
  120. union intel_x86_pebs_dse dse;
  121. u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
  122. dse.val = status;
  123. /*
  124. * bit 4: TLB access
  125. * 1 = stored missed 2nd level TLB
  126. *
  127. * so it either hit the walker or the OS
  128. * otherwise hit 2nd level TLB
  129. */
  130. if (dse.st_stlb_miss)
  131. val |= P(TLB, MISS);
  132. else
  133. val |= P(TLB, HIT);
  134. /*
  135. * bit 0: hit L1 data cache
  136. * if not set, then all we know is that
  137. * it missed L1D
  138. */
  139. if (dse.st_l1d_hit)
  140. val |= P(LVL, HIT);
  141. else
  142. val |= P(LVL, MISS);
  143. /*
  144. * bit 5: Locked prefix
  145. */
  146. if (dse.st_locked)
  147. val |= P(LOCK, LOCKED);
  148. return val;
  149. }
  150. static u64 precise_datala_hsw(struct perf_event *event, u64 status)
  151. {
  152. union perf_mem_data_src dse;
  153. dse.val = PERF_MEM_NA;
  154. if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
  155. dse.mem_op = PERF_MEM_OP_STORE;
  156. else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW)
  157. dse.mem_op = PERF_MEM_OP_LOAD;
  158. /*
  159. * L1 info only valid for following events:
  160. *
  161. * MEM_UOPS_RETIRED.STLB_MISS_STORES
  162. * MEM_UOPS_RETIRED.LOCK_STORES
  163. * MEM_UOPS_RETIRED.SPLIT_STORES
  164. * MEM_UOPS_RETIRED.ALL_STORES
  165. */
  166. if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) {
  167. if (status & 1)
  168. dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
  169. else
  170. dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
  171. }
  172. return dse.val;
  173. }
  174. static inline void pebs_set_tlb_lock(u64 *val, bool tlb, bool lock)
  175. {
  176. /*
  177. * TLB access
  178. * 0 = did not miss 2nd level TLB
  179. * 1 = missed 2nd level TLB
  180. */
  181. if (tlb)
  182. *val |= P(TLB, MISS) | P(TLB, L2);
  183. else
  184. *val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
  185. /* locked prefix */
  186. if (lock)
  187. *val |= P(LOCK, LOCKED);
  188. }
  189. /* Retrieve the latency data for e-core of ADL */
  190. u64 adl_latency_data_small(struct perf_event *event, u64 status)
  191. {
  192. union intel_x86_pebs_dse dse;
  193. u64 val;
  194. WARN_ON_ONCE(hybrid_pmu(event->pmu)->cpu_type == hybrid_big);
  195. dse.val = status;
  196. val = hybrid_var(event->pmu, pebs_data_source)[dse.ld_dse];
  197. /*
  198. * For the atom core on ADL,
  199. * bit 4: lock, bit 5: TLB access.
  200. */
  201. pebs_set_tlb_lock(&val, dse.ld_locked, dse.ld_stlb_miss);
  202. if (dse.ld_data_blk)
  203. val |= P(BLK, DATA);
  204. else
  205. val |= P(BLK, NA);
  206. return val;
  207. }
  208. static u64 load_latency_data(struct perf_event *event, u64 status)
  209. {
  210. union intel_x86_pebs_dse dse;
  211. u64 val;
  212. dse.val = status;
  213. /*
  214. * use the mapping table for bit 0-3
  215. */
  216. val = hybrid_var(event->pmu, pebs_data_source)[dse.ld_dse];
  217. /*
  218. * Nehalem models do not support TLB, Lock infos
  219. */
  220. if (x86_pmu.pebs_no_tlb) {
  221. val |= P(TLB, NA) | P(LOCK, NA);
  222. return val;
  223. }
  224. pebs_set_tlb_lock(&val, dse.ld_stlb_miss, dse.ld_locked);
  225. /*
  226. * Ice Lake and earlier models do not support block infos.
  227. */
  228. if (!x86_pmu.pebs_block) {
  229. val |= P(BLK, NA);
  230. return val;
  231. }
  232. /*
  233. * bit 6: load was blocked since its data could not be forwarded
  234. * from a preceding store
  235. */
  236. if (dse.ld_data_blk)
  237. val |= P(BLK, DATA);
  238. /*
  239. * bit 7: load was blocked due to potential address conflict with
  240. * a preceding store
  241. */
  242. if (dse.ld_addr_blk)
  243. val |= P(BLK, ADDR);
  244. if (!dse.ld_data_blk && !dse.ld_addr_blk)
  245. val |= P(BLK, NA);
  246. return val;
  247. }
  248. static u64 store_latency_data(struct perf_event *event, u64 status)
  249. {
  250. union intel_x86_pebs_dse dse;
  251. union perf_mem_data_src src;
  252. u64 val;
  253. dse.val = status;
  254. /*
  255. * use the mapping table for bit 0-3
  256. */
  257. val = hybrid_var(event->pmu, pebs_data_source)[dse.st_lat_dse];
  258. pebs_set_tlb_lock(&val, dse.st_lat_stlb_miss, dse.st_lat_locked);
  259. val |= P(BLK, NA);
  260. /*
  261. * the pebs_data_source table is only for loads
  262. * so override the mem_op to say STORE instead
  263. */
  264. src.val = val;
  265. src.mem_op = P(OP,STORE);
  266. return src.val;
  267. }
  268. struct pebs_record_core {
  269. u64 flags, ip;
  270. u64 ax, bx, cx, dx;
  271. u64 si, di, bp, sp;
  272. u64 r8, r9, r10, r11;
  273. u64 r12, r13, r14, r15;
  274. };
  275. struct pebs_record_nhm {
  276. u64 flags, ip;
  277. u64 ax, bx, cx, dx;
  278. u64 si, di, bp, sp;
  279. u64 r8, r9, r10, r11;
  280. u64 r12, r13, r14, r15;
  281. u64 status, dla, dse, lat;
  282. };
  283. /*
  284. * Same as pebs_record_nhm, with two additional fields.
  285. */
  286. struct pebs_record_hsw {
  287. u64 flags, ip;
  288. u64 ax, bx, cx, dx;
  289. u64 si, di, bp, sp;
  290. u64 r8, r9, r10, r11;
  291. u64 r12, r13, r14, r15;
  292. u64 status, dla, dse, lat;
  293. u64 real_ip, tsx_tuning;
  294. };
  295. union hsw_tsx_tuning {
  296. struct {
  297. u32 cycles_last_block : 32,
  298. hle_abort : 1,
  299. rtm_abort : 1,
  300. instruction_abort : 1,
  301. non_instruction_abort : 1,
  302. retry : 1,
  303. data_conflict : 1,
  304. capacity_writes : 1,
  305. capacity_reads : 1;
  306. };
  307. u64 value;
  308. };
  309. #define PEBS_HSW_TSX_FLAGS 0xff00000000ULL
  310. /* Same as HSW, plus TSC */
  311. struct pebs_record_skl {
  312. u64 flags, ip;
  313. u64 ax, bx, cx, dx;
  314. u64 si, di, bp, sp;
  315. u64 r8, r9, r10, r11;
  316. u64 r12, r13, r14, r15;
  317. u64 status, dla, dse, lat;
  318. u64 real_ip, tsx_tuning;
  319. u64 tsc;
  320. };
  321. void init_debug_store_on_cpu(int cpu)
  322. {
  323. struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
  324. if (!ds)
  325. return;
  326. wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
  327. (u32)((u64)(unsigned long)ds),
  328. (u32)((u64)(unsigned long)ds >> 32));
  329. }
  330. void fini_debug_store_on_cpu(int cpu)
  331. {
  332. if (!per_cpu(cpu_hw_events, cpu).ds)
  333. return;
  334. wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
  335. }
  336. static DEFINE_PER_CPU(void *, insn_buffer);
  337. static void ds_update_cea(void *cea, void *addr, size_t size, pgprot_t prot)
  338. {
  339. unsigned long start = (unsigned long)cea;
  340. phys_addr_t pa;
  341. size_t msz = 0;
  342. pa = virt_to_phys(addr);
  343. preempt_disable();
  344. for (; msz < size; msz += PAGE_SIZE, pa += PAGE_SIZE, cea += PAGE_SIZE)
  345. cea_set_pte(cea, pa, prot);
  346. /*
  347. * This is a cross-CPU update of the cpu_entry_area, we must shoot down
  348. * all TLB entries for it.
  349. */
  350. flush_tlb_kernel_range(start, start + size);
  351. preempt_enable();
  352. }
  353. static void ds_clear_cea(void *cea, size_t size)
  354. {
  355. unsigned long start = (unsigned long)cea;
  356. size_t msz = 0;
  357. preempt_disable();
  358. for (; msz < size; msz += PAGE_SIZE, cea += PAGE_SIZE)
  359. cea_set_pte(cea, 0, PAGE_NONE);
  360. flush_tlb_kernel_range(start, start + size);
  361. preempt_enable();
  362. }
  363. static void *dsalloc_pages(size_t size, gfp_t flags, int cpu)
  364. {
  365. unsigned int order = get_order(size);
  366. int node = cpu_to_node(cpu);
  367. struct page *page;
  368. page = __alloc_pages_node(node, flags | __GFP_ZERO, order);
  369. return page ? page_address(page) : NULL;
  370. }
  371. static void dsfree_pages(const void *buffer, size_t size)
  372. {
  373. if (buffer)
  374. free_pages((unsigned long)buffer, get_order(size));
  375. }
  376. static int alloc_pebs_buffer(int cpu)
  377. {
  378. struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
  379. struct debug_store *ds = hwev->ds;
  380. size_t bsiz = x86_pmu.pebs_buffer_size;
  381. int max, node = cpu_to_node(cpu);
  382. void *buffer, *insn_buff, *cea;
  383. if (!x86_pmu.pebs)
  384. return 0;
  385. buffer = dsalloc_pages(bsiz, GFP_KERNEL, cpu);
  386. if (unlikely(!buffer))
  387. return -ENOMEM;
  388. /*
  389. * HSW+ already provides us the eventing ip; no need to allocate this
  390. * buffer then.
  391. */
  392. if (x86_pmu.intel_cap.pebs_format < 2) {
  393. insn_buff = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
  394. if (!insn_buff) {
  395. dsfree_pages(buffer, bsiz);
  396. return -ENOMEM;
  397. }
  398. per_cpu(insn_buffer, cpu) = insn_buff;
  399. }
  400. hwev->ds_pebs_vaddr = buffer;
  401. /* Update the cpu entry area mapping */
  402. cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer;
  403. ds->pebs_buffer_base = (unsigned long) cea;
  404. ds_update_cea(cea, buffer, bsiz, PAGE_KERNEL);
  405. ds->pebs_index = ds->pebs_buffer_base;
  406. max = x86_pmu.pebs_record_size * (bsiz / x86_pmu.pebs_record_size);
  407. ds->pebs_absolute_maximum = ds->pebs_buffer_base + max;
  408. return 0;
  409. }
  410. static void release_pebs_buffer(int cpu)
  411. {
  412. struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
  413. void *cea;
  414. if (!x86_pmu.pebs)
  415. return;
  416. kfree(per_cpu(insn_buffer, cpu));
  417. per_cpu(insn_buffer, cpu) = NULL;
  418. /* Clear the fixmap */
  419. cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer;
  420. ds_clear_cea(cea, x86_pmu.pebs_buffer_size);
  421. dsfree_pages(hwev->ds_pebs_vaddr, x86_pmu.pebs_buffer_size);
  422. hwev->ds_pebs_vaddr = NULL;
  423. }
  424. static int alloc_bts_buffer(int cpu)
  425. {
  426. struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
  427. struct debug_store *ds = hwev->ds;
  428. void *buffer, *cea;
  429. int max;
  430. if (!x86_pmu.bts)
  431. return 0;
  432. buffer = dsalloc_pages(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, cpu);
  433. if (unlikely(!buffer)) {
  434. WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
  435. return -ENOMEM;
  436. }
  437. hwev->ds_bts_vaddr = buffer;
  438. /* Update the fixmap */
  439. cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer;
  440. ds->bts_buffer_base = (unsigned long) cea;
  441. ds_update_cea(cea, buffer, BTS_BUFFER_SIZE, PAGE_KERNEL);
  442. ds->bts_index = ds->bts_buffer_base;
  443. max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
  444. ds->bts_absolute_maximum = ds->bts_buffer_base +
  445. max * BTS_RECORD_SIZE;
  446. ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
  447. (max / 16) * BTS_RECORD_SIZE;
  448. return 0;
  449. }
  450. static void release_bts_buffer(int cpu)
  451. {
  452. struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
  453. void *cea;
  454. if (!x86_pmu.bts)
  455. return;
  456. /* Clear the fixmap */
  457. cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer;
  458. ds_clear_cea(cea, BTS_BUFFER_SIZE);
  459. dsfree_pages(hwev->ds_bts_vaddr, BTS_BUFFER_SIZE);
  460. hwev->ds_bts_vaddr = NULL;
  461. }
  462. static int alloc_ds_buffer(int cpu)
  463. {
  464. struct debug_store *ds = &get_cpu_entry_area(cpu)->cpu_debug_store;
  465. memset(ds, 0, sizeof(*ds));
  466. per_cpu(cpu_hw_events, cpu).ds = ds;
  467. return 0;
  468. }
  469. static void release_ds_buffer(int cpu)
  470. {
  471. per_cpu(cpu_hw_events, cpu).ds = NULL;
  472. }
  473. void release_ds_buffers(void)
  474. {
  475. int cpu;
  476. if (!x86_pmu.bts && !x86_pmu.pebs)
  477. return;
  478. for_each_possible_cpu(cpu)
  479. release_ds_buffer(cpu);
  480. for_each_possible_cpu(cpu) {
  481. /*
  482. * Again, ignore errors from offline CPUs, they will no longer
  483. * observe cpu_hw_events.ds and not program the DS_AREA when
  484. * they come up.
  485. */
  486. fini_debug_store_on_cpu(cpu);
  487. }
  488. for_each_possible_cpu(cpu) {
  489. release_pebs_buffer(cpu);
  490. release_bts_buffer(cpu);
  491. }
  492. }
  493. void reserve_ds_buffers(void)
  494. {
  495. int bts_err = 0, pebs_err = 0;
  496. int cpu;
  497. x86_pmu.bts_active = 0;
  498. x86_pmu.pebs_active = 0;
  499. if (!x86_pmu.bts && !x86_pmu.pebs)
  500. return;
  501. if (!x86_pmu.bts)
  502. bts_err = 1;
  503. if (!x86_pmu.pebs)
  504. pebs_err = 1;
  505. for_each_possible_cpu(cpu) {
  506. if (alloc_ds_buffer(cpu)) {
  507. bts_err = 1;
  508. pebs_err = 1;
  509. }
  510. if (!bts_err && alloc_bts_buffer(cpu))
  511. bts_err = 1;
  512. if (!pebs_err && alloc_pebs_buffer(cpu))
  513. pebs_err = 1;
  514. if (bts_err && pebs_err)
  515. break;
  516. }
  517. if (bts_err) {
  518. for_each_possible_cpu(cpu)
  519. release_bts_buffer(cpu);
  520. }
  521. if (pebs_err) {
  522. for_each_possible_cpu(cpu)
  523. release_pebs_buffer(cpu);
  524. }
  525. if (bts_err && pebs_err) {
  526. for_each_possible_cpu(cpu)
  527. release_ds_buffer(cpu);
  528. } else {
  529. if (x86_pmu.bts && !bts_err)
  530. x86_pmu.bts_active = 1;
  531. if (x86_pmu.pebs && !pebs_err)
  532. x86_pmu.pebs_active = 1;
  533. for_each_possible_cpu(cpu) {
  534. /*
  535. * Ignores wrmsr_on_cpu() errors for offline CPUs they
  536. * will get this call through intel_pmu_cpu_starting().
  537. */
  538. init_debug_store_on_cpu(cpu);
  539. }
  540. }
  541. }
  542. /*
  543. * BTS
  544. */
  545. struct event_constraint bts_constraint =
  546. EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
  547. void intel_pmu_enable_bts(u64 config)
  548. {
  549. unsigned long debugctlmsr;
  550. debugctlmsr = get_debugctlmsr();
  551. debugctlmsr |= DEBUGCTLMSR_TR;
  552. debugctlmsr |= DEBUGCTLMSR_BTS;
  553. if (config & ARCH_PERFMON_EVENTSEL_INT)
  554. debugctlmsr |= DEBUGCTLMSR_BTINT;
  555. if (!(config & ARCH_PERFMON_EVENTSEL_OS))
  556. debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
  557. if (!(config & ARCH_PERFMON_EVENTSEL_USR))
  558. debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
  559. update_debugctlmsr(debugctlmsr);
  560. }
  561. void intel_pmu_disable_bts(void)
  562. {
  563. struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
  564. unsigned long debugctlmsr;
  565. if (!cpuc->ds)
  566. return;
  567. debugctlmsr = get_debugctlmsr();
  568. debugctlmsr &=
  569. ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
  570. DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
  571. update_debugctlmsr(debugctlmsr);
  572. }
  573. int intel_pmu_drain_bts_buffer(void)
  574. {
  575. struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
  576. struct debug_store *ds = cpuc->ds;
  577. struct bts_record {
  578. u64 from;
  579. u64 to;
  580. u64 flags;
  581. };
  582. struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
  583. struct bts_record *at, *base, *top;
  584. struct perf_output_handle handle;
  585. struct perf_event_header header;
  586. struct perf_sample_data data;
  587. unsigned long skip = 0;
  588. struct pt_regs regs;
  589. if (!event)
  590. return 0;
  591. if (!x86_pmu.bts_active)
  592. return 0;
  593. base = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
  594. top = (struct bts_record *)(unsigned long)ds->bts_index;
  595. if (top <= base)
  596. return 0;
  597. memset(&regs, 0, sizeof(regs));
  598. ds->bts_index = ds->bts_buffer_base;
  599. perf_sample_data_init(&data, 0, event->hw.last_period);
  600. /*
  601. * BTS leaks kernel addresses in branches across the cpl boundary,
  602. * such as traps or system calls, so unless the user is asking for
  603. * kernel tracing (and right now it's not possible), we'd need to
  604. * filter them out. But first we need to count how many of those we
  605. * have in the current batch. This is an extra O(n) pass, however,
  606. * it's much faster than the other one especially considering that
  607. * n <= 2560 (BTS_BUFFER_SIZE / BTS_RECORD_SIZE * 15/16; see the
  608. * alloc_bts_buffer()).
  609. */
  610. for (at = base; at < top; at++) {
  611. /*
  612. * Note that right now *this* BTS code only works if
  613. * attr::exclude_kernel is set, but let's keep this extra
  614. * check here in case that changes.
  615. */
  616. if (event->attr.exclude_kernel &&
  617. (kernel_ip(at->from) || kernel_ip(at->to)))
  618. skip++;
  619. }
  620. /*
  621. * Prepare a generic sample, i.e. fill in the invariant fields.
  622. * We will overwrite the from and to address before we output
  623. * the sample.
  624. */
  625. rcu_read_lock();
  626. perf_prepare_sample(&header, &data, event, &regs);
  627. if (perf_output_begin(&handle, &data, event,
  628. header.size * (top - base - skip)))
  629. goto unlock;
  630. for (at = base; at < top; at++) {
  631. /* Filter out any records that contain kernel addresses. */
  632. if (event->attr.exclude_kernel &&
  633. (kernel_ip(at->from) || kernel_ip(at->to)))
  634. continue;
  635. data.ip = at->from;
  636. data.addr = at->to;
  637. perf_output_sample(&handle, &header, &data, event);
  638. }
  639. perf_output_end(&handle);
  640. /* There's new data available. */
  641. event->hw.interrupts++;
  642. event->pending_kill = POLL_IN;
  643. unlock:
  644. rcu_read_unlock();
  645. return 1;
  646. }
  647. static inline void intel_pmu_drain_pebs_buffer(void)
  648. {
  649. struct perf_sample_data data;
  650. x86_pmu.drain_pebs(NULL, &data);
  651. }
  652. /*
  653. * PEBS
  654. */
  655. struct event_constraint intel_core2_pebs_event_constraints[] = {
  656. INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
  657. INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
  658. INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
  659. INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
  660. INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
  661. /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
  662. INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01),
  663. EVENT_CONSTRAINT_END
  664. };
  665. struct event_constraint intel_atom_pebs_event_constraints[] = {
  666. INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
  667. INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
  668. INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
  669. /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
  670. INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01),
  671. /* Allow all events as PEBS with no flags */
  672. INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
  673. EVENT_CONSTRAINT_END
  674. };
  675. struct event_constraint intel_slm_pebs_event_constraints[] = {
  676. /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
  677. INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x1),
  678. /* Allow all events as PEBS with no flags */
  679. INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
  680. EVENT_CONSTRAINT_END
  681. };
  682. struct event_constraint intel_glm_pebs_event_constraints[] = {
  683. /* Allow all events as PEBS with no flags */
  684. INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
  685. EVENT_CONSTRAINT_END
  686. };
  687. struct event_constraint intel_grt_pebs_event_constraints[] = {
  688. /* Allow all events as PEBS with no flags */
  689. INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0x3),
  690. INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xf),
  691. EVENT_CONSTRAINT_END
  692. };
  693. struct event_constraint intel_nehalem_pebs_event_constraints[] = {
  694. INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
  695. INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
  696. INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
  697. INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */
  698. INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
  699. INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
  700. INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
  701. INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
  702. INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
  703. INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
  704. INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
  705. /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
  706. INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
  707. EVENT_CONSTRAINT_END
  708. };
  709. struct event_constraint intel_westmere_pebs_event_constraints[] = {
  710. INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
  711. INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
  712. INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
  713. INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */
  714. INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
  715. INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
  716. INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
  717. INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
  718. INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
  719. INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
  720. INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
  721. /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
  722. INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
  723. EVENT_CONSTRAINT_END
  724. };
  725. struct event_constraint intel_snb_pebs_event_constraints[] = {
  726. INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
  727. INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
  728. INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
  729. /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
  730. INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
  731. INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
  732. INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
  733. INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
  734. INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
  735. /* Allow all events as PEBS with no flags */
  736. INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
  737. EVENT_CONSTRAINT_END
  738. };
  739. struct event_constraint intel_ivb_pebs_event_constraints[] = {
  740. INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
  741. INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
  742. INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
  743. /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
  744. INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
  745. /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
  746. INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
  747. INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
  748. INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
  749. INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
  750. INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
  751. /* Allow all events as PEBS with no flags */
  752. INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
  753. EVENT_CONSTRAINT_END
  754. };
  755. struct event_constraint intel_hsw_pebs_event_constraints[] = {
  756. INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
  757. INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
  758. /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
  759. INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
  760. /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
  761. INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
  762. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
  763. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
  764. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
  765. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
  766. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
  767. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
  768. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
  769. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
  770. INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
  771. INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
  772. INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
  773. /* Allow all events as PEBS with no flags */
  774. INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
  775. EVENT_CONSTRAINT_END
  776. };
  777. struct event_constraint intel_bdw_pebs_event_constraints[] = {
  778. INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
  779. INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
  780. /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
  781. INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
  782. /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
  783. INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
  784. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
  785. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
  786. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
  787. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
  788. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
  789. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
  790. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
  791. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
  792. INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
  793. INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
  794. INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
  795. /* Allow all events as PEBS with no flags */
  796. INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
  797. EVENT_CONSTRAINT_END
  798. };
  799. struct event_constraint intel_skl_pebs_event_constraints[] = {
  800. INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
  801. /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
  802. INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
  803. /* INST_RETIRED.TOTAL_CYCLES_PS (inv=1, cmask=16) (cycles:p). */
  804. INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
  805. INTEL_PLD_CONSTRAINT(0x1cd, 0xf), /* MEM_TRANS_RETIRED.* */
  806. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
  807. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
  808. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
  809. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */
  810. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
  811. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
  812. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
  813. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
  814. INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
  815. INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
  816. INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_L3_MISS_RETIRED.* */
  817. /* Allow all events as PEBS with no flags */
  818. INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
  819. EVENT_CONSTRAINT_END
  820. };
  821. struct event_constraint intel_icl_pebs_event_constraints[] = {
  822. INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x100000000ULL), /* old INST_RETIRED.PREC_DIST */
  823. INTEL_FLAGS_UEVENT_CONSTRAINT(0x0100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */
  824. INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL), /* SLOTS */
  825. INTEL_PLD_CONSTRAINT(0x1cd, 0xff), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
  826. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
  827. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
  828. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
  829. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
  830. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
  831. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
  832. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
  833. INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf), /* MEM_LOAD_*_RETIRED.* */
  834. INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
  835. /*
  836. * Everything else is handled by PMU_FL_PEBS_ALL, because we
  837. * need the full constraints from the main table.
  838. */
  839. EVENT_CONSTRAINT_END
  840. };
  841. struct event_constraint intel_spr_pebs_event_constraints[] = {
  842. INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */
  843. INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),
  844. INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xfe),
  845. INTEL_PLD_CONSTRAINT(0x1cd, 0xfe),
  846. INTEL_PSD_CONSTRAINT(0x2cd, 0x1),
  847. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
  848. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
  849. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
  850. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
  851. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
  852. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
  853. INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
  854. INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf),
  855. INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf),
  856. /*
  857. * Everything else is handled by PMU_FL_PEBS_ALL, because we
  858. * need the full constraints from the main table.
  859. */
  860. EVENT_CONSTRAINT_END
  861. };
  862. struct event_constraint *intel_pebs_constraints(struct perf_event *event)
  863. {
  864. struct event_constraint *pebs_constraints = hybrid(event->pmu, pebs_constraints);
  865. struct event_constraint *c;
  866. if (!event->attr.precise_ip)
  867. return NULL;
  868. if (pebs_constraints) {
  869. for_each_event_constraint(c, pebs_constraints) {
  870. if (constraint_match(c, event->hw.config)) {
  871. event->hw.flags |= c->flags;
  872. return c;
  873. }
  874. }
  875. }
  876. /*
  877. * Extended PEBS support
  878. * Makes the PEBS code search the normal constraints.
  879. */
  880. if (x86_pmu.flags & PMU_FL_PEBS_ALL)
  881. return NULL;
  882. return &emptyconstraint;
  883. }
  884. /*
  885. * We need the sched_task callback even for per-cpu events when we use
  886. * the large interrupt threshold, such that we can provide PID and TID
  887. * to PEBS samples.
  888. */
  889. static inline bool pebs_needs_sched_cb(struct cpu_hw_events *cpuc)
  890. {
  891. if (cpuc->n_pebs == cpuc->n_pebs_via_pt)
  892. return false;
  893. return cpuc->n_pebs && (cpuc->n_pebs == cpuc->n_large_pebs);
  894. }
  895. void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in)
  896. {
  897. struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
  898. if (!sched_in && pebs_needs_sched_cb(cpuc))
  899. intel_pmu_drain_pebs_buffer();
  900. }
  901. static inline void pebs_update_threshold(struct cpu_hw_events *cpuc)
  902. {
  903. struct debug_store *ds = cpuc->ds;
  904. int max_pebs_events = hybrid(cpuc->pmu, max_pebs_events);
  905. int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
  906. u64 threshold;
  907. int reserved;
  908. if (cpuc->n_pebs_via_pt)
  909. return;
  910. if (x86_pmu.flags & PMU_FL_PEBS_ALL)
  911. reserved = max_pebs_events + num_counters_fixed;
  912. else
  913. reserved = max_pebs_events;
  914. if (cpuc->n_pebs == cpuc->n_large_pebs) {
  915. threshold = ds->pebs_absolute_maximum -
  916. reserved * cpuc->pebs_record_size;
  917. } else {
  918. threshold = ds->pebs_buffer_base + cpuc->pebs_record_size;
  919. }
  920. ds->pebs_interrupt_threshold = threshold;
  921. }
  922. static void adaptive_pebs_record_size_update(void)
  923. {
  924. struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
  925. u64 pebs_data_cfg = cpuc->pebs_data_cfg;
  926. int sz = sizeof(struct pebs_basic);
  927. if (pebs_data_cfg & PEBS_DATACFG_MEMINFO)
  928. sz += sizeof(struct pebs_meminfo);
  929. if (pebs_data_cfg & PEBS_DATACFG_GP)
  930. sz += sizeof(struct pebs_gprs);
  931. if (pebs_data_cfg & PEBS_DATACFG_XMMS)
  932. sz += sizeof(struct pebs_xmm);
  933. if (pebs_data_cfg & PEBS_DATACFG_LBRS)
  934. sz += x86_pmu.lbr_nr * sizeof(struct lbr_entry);
  935. cpuc->pebs_record_size = sz;
  936. }
  937. #define PERF_PEBS_MEMINFO_TYPE (PERF_SAMPLE_ADDR | PERF_SAMPLE_DATA_SRC | \
  938. PERF_SAMPLE_PHYS_ADDR | \
  939. PERF_SAMPLE_WEIGHT_TYPE | \
  940. PERF_SAMPLE_TRANSACTION | \
  941. PERF_SAMPLE_DATA_PAGE_SIZE)
  942. static u64 pebs_update_adaptive_cfg(struct perf_event *event)
  943. {
  944. struct perf_event_attr *attr = &event->attr;
  945. u64 sample_type = attr->sample_type;
  946. u64 pebs_data_cfg = 0;
  947. bool gprs, tsx_weight;
  948. if (!(sample_type & ~(PERF_SAMPLE_IP|PERF_SAMPLE_TIME)) &&
  949. attr->precise_ip > 1)
  950. return pebs_data_cfg;
  951. if (sample_type & PERF_PEBS_MEMINFO_TYPE)
  952. pebs_data_cfg |= PEBS_DATACFG_MEMINFO;
  953. /*
  954. * We need GPRs when:
  955. * + user requested them
  956. * + precise_ip < 2 for the non event IP
  957. * + For RTM TSX weight we need GPRs for the abort code.
  958. */
  959. gprs = (sample_type & PERF_SAMPLE_REGS_INTR) &&
  960. (attr->sample_regs_intr & PEBS_GP_REGS);
  961. tsx_weight = (sample_type & PERF_SAMPLE_WEIGHT_TYPE) &&
  962. ((attr->config & INTEL_ARCH_EVENT_MASK) ==
  963. x86_pmu.rtm_abort_event);
  964. if (gprs || (attr->precise_ip < 2) || tsx_weight)
  965. pebs_data_cfg |= PEBS_DATACFG_GP;
  966. if ((sample_type & PERF_SAMPLE_REGS_INTR) &&
  967. (attr->sample_regs_intr & PERF_REG_EXTENDED_MASK))
  968. pebs_data_cfg |= PEBS_DATACFG_XMMS;
  969. if (sample_type & PERF_SAMPLE_BRANCH_STACK) {
  970. /*
  971. * For now always log all LBRs. Could configure this
  972. * later.
  973. */
  974. pebs_data_cfg |= PEBS_DATACFG_LBRS |
  975. ((x86_pmu.lbr_nr-1) << PEBS_DATACFG_LBR_SHIFT);
  976. }
  977. return pebs_data_cfg;
  978. }
  979. static void
  980. pebs_update_state(bool needed_cb, struct cpu_hw_events *cpuc,
  981. struct perf_event *event, bool add)
  982. {
  983. struct pmu *pmu = event->ctx->pmu;
  984. /*
  985. * Make sure we get updated with the first PEBS
  986. * event. It will trigger also during removal, but
  987. * that does not hurt:
  988. */
  989. bool update = cpuc->n_pebs == 1;
  990. if (needed_cb != pebs_needs_sched_cb(cpuc)) {
  991. if (!needed_cb)
  992. perf_sched_cb_inc(pmu);
  993. else
  994. perf_sched_cb_dec(pmu);
  995. update = true;
  996. }
  997. /*
  998. * The PEBS record doesn't shrink on pmu::del(). Doing so would require
  999. * iterating all remaining PEBS events to reconstruct the config.
  1000. */
  1001. if (x86_pmu.intel_cap.pebs_baseline && add) {
  1002. u64 pebs_data_cfg;
  1003. /* Clear pebs_data_cfg and pebs_record_size for first PEBS. */
  1004. if (cpuc->n_pebs == 1) {
  1005. cpuc->pebs_data_cfg = 0;
  1006. cpuc->pebs_record_size = sizeof(struct pebs_basic);
  1007. }
  1008. pebs_data_cfg = pebs_update_adaptive_cfg(event);
  1009. /* Update pebs_record_size if new event requires more data. */
  1010. if (pebs_data_cfg & ~cpuc->pebs_data_cfg) {
  1011. cpuc->pebs_data_cfg |= pebs_data_cfg;
  1012. adaptive_pebs_record_size_update();
  1013. update = true;
  1014. }
  1015. }
  1016. if (update)
  1017. pebs_update_threshold(cpuc);
  1018. }
  1019. void intel_pmu_pebs_add(struct perf_event *event)
  1020. {
  1021. struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
  1022. struct hw_perf_event *hwc = &event->hw;
  1023. bool needed_cb = pebs_needs_sched_cb(cpuc);
  1024. cpuc->n_pebs++;
  1025. if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS)
  1026. cpuc->n_large_pebs++;
  1027. if (hwc->flags & PERF_X86_EVENT_PEBS_VIA_PT)
  1028. cpuc->n_pebs_via_pt++;
  1029. pebs_update_state(needed_cb, cpuc, event, true);
  1030. }
  1031. static void intel_pmu_pebs_via_pt_disable(struct perf_event *event)
  1032. {
  1033. struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
  1034. if (!is_pebs_pt(event))
  1035. return;
  1036. if (!(cpuc->pebs_enabled & ~PEBS_VIA_PT_MASK))
  1037. cpuc->pebs_enabled &= ~PEBS_VIA_PT_MASK;
  1038. }
  1039. static void intel_pmu_pebs_via_pt_enable(struct perf_event *event)
  1040. {
  1041. struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
  1042. struct hw_perf_event *hwc = &event->hw;
  1043. struct debug_store *ds = cpuc->ds;
  1044. u64 value = ds->pebs_event_reset[hwc->idx];
  1045. u32 base = MSR_RELOAD_PMC0;
  1046. unsigned int idx = hwc->idx;
  1047. if (!is_pebs_pt(event))
  1048. return;
  1049. if (!(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS))
  1050. cpuc->pebs_enabled |= PEBS_PMI_AFTER_EACH_RECORD;
  1051. cpuc->pebs_enabled |= PEBS_OUTPUT_PT;
  1052. if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
  1053. base = MSR_RELOAD_FIXED_CTR0;
  1054. idx = hwc->idx - INTEL_PMC_IDX_FIXED;
  1055. if (x86_pmu.intel_cap.pebs_format < 5)
  1056. value = ds->pebs_event_reset[MAX_PEBS_EVENTS_FMT4 + idx];
  1057. else
  1058. value = ds->pebs_event_reset[MAX_PEBS_EVENTS + idx];
  1059. }
  1060. wrmsrl(base + idx, value);
  1061. }
  1062. void intel_pmu_pebs_enable(struct perf_event *event)
  1063. {
  1064. struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
  1065. struct hw_perf_event *hwc = &event->hw;
  1066. struct debug_store *ds = cpuc->ds;
  1067. unsigned int idx = hwc->idx;
  1068. hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
  1069. cpuc->pebs_enabled |= 1ULL << hwc->idx;
  1070. if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) && (x86_pmu.version < 5))
  1071. cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
  1072. else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
  1073. cpuc->pebs_enabled |= 1ULL << 63;
  1074. if (x86_pmu.intel_cap.pebs_baseline) {
  1075. hwc->config |= ICL_EVENTSEL_ADAPTIVE;
  1076. if (cpuc->pebs_data_cfg != cpuc->active_pebs_data_cfg) {
  1077. wrmsrl(MSR_PEBS_DATA_CFG, cpuc->pebs_data_cfg);
  1078. cpuc->active_pebs_data_cfg = cpuc->pebs_data_cfg;
  1079. }
  1080. }
  1081. if (idx >= INTEL_PMC_IDX_FIXED) {
  1082. if (x86_pmu.intel_cap.pebs_format < 5)
  1083. idx = MAX_PEBS_EVENTS_FMT4 + (idx - INTEL_PMC_IDX_FIXED);
  1084. else
  1085. idx = MAX_PEBS_EVENTS + (idx - INTEL_PMC_IDX_FIXED);
  1086. }
  1087. /*
  1088. * Use auto-reload if possible to save a MSR write in the PMI.
  1089. * This must be done in pmu::start(), because PERF_EVENT_IOC_PERIOD.
  1090. */
  1091. if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
  1092. ds->pebs_event_reset[idx] =
  1093. (u64)(-hwc->sample_period) & x86_pmu.cntval_mask;
  1094. } else {
  1095. ds->pebs_event_reset[idx] = 0;
  1096. }
  1097. intel_pmu_pebs_via_pt_enable(event);
  1098. }
  1099. void intel_pmu_pebs_del(struct perf_event *event)
  1100. {
  1101. struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
  1102. struct hw_perf_event *hwc = &event->hw;
  1103. bool needed_cb = pebs_needs_sched_cb(cpuc);
  1104. cpuc->n_pebs--;
  1105. if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS)
  1106. cpuc->n_large_pebs--;
  1107. if (hwc->flags & PERF_X86_EVENT_PEBS_VIA_PT)
  1108. cpuc->n_pebs_via_pt--;
  1109. pebs_update_state(needed_cb, cpuc, event, false);
  1110. }
  1111. void intel_pmu_pebs_disable(struct perf_event *event)
  1112. {
  1113. struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
  1114. struct hw_perf_event *hwc = &event->hw;
  1115. if (cpuc->n_pebs == cpuc->n_large_pebs &&
  1116. cpuc->n_pebs != cpuc->n_pebs_via_pt)
  1117. intel_pmu_drain_pebs_buffer();
  1118. cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
  1119. if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) &&
  1120. (x86_pmu.version < 5))
  1121. cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
  1122. else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
  1123. cpuc->pebs_enabled &= ~(1ULL << 63);
  1124. intel_pmu_pebs_via_pt_disable(event);
  1125. if (cpuc->enabled)
  1126. wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
  1127. hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
  1128. }
  1129. void intel_pmu_pebs_enable_all(void)
  1130. {
  1131. struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
  1132. if (cpuc->pebs_enabled)
  1133. wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
  1134. }
  1135. void intel_pmu_pebs_disable_all(void)
  1136. {
  1137. struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
  1138. if (cpuc->pebs_enabled)
  1139. __intel_pmu_pebs_disable_all();
  1140. }
  1141. static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
  1142. {
  1143. struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
  1144. unsigned long from = cpuc->lbr_entries[0].from;
  1145. unsigned long old_to, to = cpuc->lbr_entries[0].to;
  1146. unsigned long ip = regs->ip;
  1147. int is_64bit = 0;
  1148. void *kaddr;
  1149. int size;
  1150. /*
  1151. * We don't need to fixup if the PEBS assist is fault like
  1152. */
  1153. if (!x86_pmu.intel_cap.pebs_trap)
  1154. return 1;
  1155. /*
  1156. * No LBR entry, no basic block, no rewinding
  1157. */
  1158. if (!cpuc->lbr_stack.nr || !from || !to)
  1159. return 0;
  1160. /*
  1161. * Basic blocks should never cross user/kernel boundaries
  1162. */
  1163. if (kernel_ip(ip) != kernel_ip(to))
  1164. return 0;
  1165. /*
  1166. * unsigned math, either ip is before the start (impossible) or
  1167. * the basic block is larger than 1 page (sanity)
  1168. */
  1169. if ((ip - to) > PEBS_FIXUP_SIZE)
  1170. return 0;
  1171. /*
  1172. * We sampled a branch insn, rewind using the LBR stack
  1173. */
  1174. if (ip == to) {
  1175. set_linear_ip(regs, from);
  1176. return 1;
  1177. }
  1178. size = ip - to;
  1179. if (!kernel_ip(ip)) {
  1180. int bytes;
  1181. u8 *buf = this_cpu_read(insn_buffer);
  1182. /* 'size' must fit our buffer, see above */
  1183. bytes = copy_from_user_nmi(buf, (void __user *)to, size);
  1184. if (bytes != 0)
  1185. return 0;
  1186. kaddr = buf;
  1187. } else {
  1188. kaddr = (void *)to;
  1189. }
  1190. do {
  1191. struct insn insn;
  1192. old_to = to;
  1193. #ifdef CONFIG_X86_64
  1194. is_64bit = kernel_ip(to) || any_64bit_mode(regs);
  1195. #endif
  1196. insn_init(&insn, kaddr, size, is_64bit);
  1197. /*
  1198. * Make sure there was not a problem decoding the instruction.
  1199. * This is doubly important because we have an infinite loop if
  1200. * insn.length=0.
  1201. */
  1202. if (insn_get_length(&insn))
  1203. break;
  1204. to += insn.length;
  1205. kaddr += insn.length;
  1206. size -= insn.length;
  1207. } while (to < ip);
  1208. if (to == ip) {
  1209. set_linear_ip(regs, old_to);
  1210. return 1;
  1211. }
  1212. /*
  1213. * Even though we decoded the basic block, the instruction stream
  1214. * never matched the given IP, either the TO or the IP got corrupted.
  1215. */
  1216. return 0;
  1217. }
  1218. static inline u64 intel_get_tsx_weight(u64 tsx_tuning)
  1219. {
  1220. if (tsx_tuning) {
  1221. union hsw_tsx_tuning tsx = { .value = tsx_tuning };
  1222. return tsx.cycles_last_block;
  1223. }
  1224. return 0;
  1225. }
  1226. static inline u64 intel_get_tsx_transaction(u64 tsx_tuning, u64 ax)
  1227. {
  1228. u64 txn = (tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
  1229. /* For RTM XABORTs also log the abort code from AX */
  1230. if ((txn & PERF_TXN_TRANSACTION) && (ax & 1))
  1231. txn |= ((ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
  1232. return txn;
  1233. }
  1234. static inline u64 get_pebs_status(void *n)
  1235. {
  1236. if (x86_pmu.intel_cap.pebs_format < 4)
  1237. return ((struct pebs_record_nhm *)n)->status;
  1238. return ((struct pebs_basic *)n)->applicable_counters;
  1239. }
  1240. #define PERF_X86_EVENT_PEBS_HSW_PREC \
  1241. (PERF_X86_EVENT_PEBS_ST_HSW | \
  1242. PERF_X86_EVENT_PEBS_LD_HSW | \
  1243. PERF_X86_EVENT_PEBS_NA_HSW)
  1244. static u64 get_data_src(struct perf_event *event, u64 aux)
  1245. {
  1246. u64 val = PERF_MEM_NA;
  1247. int fl = event->hw.flags;
  1248. bool fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC);
  1249. if (fl & PERF_X86_EVENT_PEBS_LDLAT)
  1250. val = load_latency_data(event, aux);
  1251. else if (fl & PERF_X86_EVENT_PEBS_STLAT)
  1252. val = store_latency_data(event, aux);
  1253. else if (fl & PERF_X86_EVENT_PEBS_LAT_HYBRID)
  1254. val = x86_pmu.pebs_latency_data(event, aux);
  1255. else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC))
  1256. val = precise_datala_hsw(event, aux);
  1257. else if (fst)
  1258. val = precise_store_data(aux);
  1259. return val;
  1260. }
  1261. static void setup_pebs_time(struct perf_event *event,
  1262. struct perf_sample_data *data,
  1263. u64 tsc)
  1264. {
  1265. /* Converting to a user-defined clock is not supported yet. */
  1266. if (event->attr.use_clockid != 0)
  1267. return;
  1268. /*
  1269. * Doesn't support the conversion when the TSC is unstable.
  1270. * The TSC unstable case is a corner case and very unlikely to
  1271. * happen. If it happens, the TSC in a PEBS record will be
  1272. * dropped and fall back to perf_event_clock().
  1273. */
  1274. if (!using_native_sched_clock() || !sched_clock_stable())
  1275. return;
  1276. data->time = native_sched_clock_from_tsc(tsc) + __sched_clock_offset;
  1277. data->sample_flags |= PERF_SAMPLE_TIME;
  1278. }
  1279. #define PERF_SAMPLE_ADDR_TYPE (PERF_SAMPLE_ADDR | \
  1280. PERF_SAMPLE_PHYS_ADDR | \
  1281. PERF_SAMPLE_DATA_PAGE_SIZE)
  1282. static void setup_pebs_fixed_sample_data(struct perf_event *event,
  1283. struct pt_regs *iregs, void *__pebs,
  1284. struct perf_sample_data *data,
  1285. struct pt_regs *regs)
  1286. {
  1287. /*
  1288. * We cast to the biggest pebs_record but are careful not to
  1289. * unconditionally access the 'extra' entries.
  1290. */
  1291. struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
  1292. struct pebs_record_skl *pebs = __pebs;
  1293. u64 sample_type;
  1294. int fll;
  1295. if (pebs == NULL)
  1296. return;
  1297. sample_type = event->attr.sample_type;
  1298. fll = event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT;
  1299. perf_sample_data_init(data, 0, event->hw.last_period);
  1300. data->period = event->hw.last_period;
  1301. /*
  1302. * Use latency for weight (only avail with PEBS-LL)
  1303. */
  1304. if (fll && (sample_type & PERF_SAMPLE_WEIGHT_TYPE)) {
  1305. data->weight.full = pebs->lat;
  1306. data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE;
  1307. }
  1308. /*
  1309. * data.data_src encodes the data source
  1310. */
  1311. if (sample_type & PERF_SAMPLE_DATA_SRC) {
  1312. data->data_src.val = get_data_src(event, pebs->dse);
  1313. data->sample_flags |= PERF_SAMPLE_DATA_SRC;
  1314. }
  1315. /*
  1316. * We must however always use iregs for the unwinder to stay sane; the
  1317. * record BP,SP,IP can point into thin air when the record is from a
  1318. * previous PMI context or an (I)RET happened between the record and
  1319. * PMI.
  1320. */
  1321. if (sample_type & PERF_SAMPLE_CALLCHAIN) {
  1322. data->callchain = perf_callchain(event, iregs);
  1323. data->sample_flags |= PERF_SAMPLE_CALLCHAIN;
  1324. }
  1325. /*
  1326. * We use the interrupt regs as a base because the PEBS record does not
  1327. * contain a full regs set, specifically it seems to lack segment
  1328. * descriptors, which get used by things like user_mode().
  1329. *
  1330. * In the simple case fix up only the IP for PERF_SAMPLE_IP.
  1331. */
  1332. *regs = *iregs;
  1333. /*
  1334. * Initialize regs_>flags from PEBS,
  1335. * Clear exact bit (which uses x86 EFLAGS Reserved bit 3),
  1336. * i.e., do not rely on it being zero:
  1337. */
  1338. regs->flags = pebs->flags & ~PERF_EFLAGS_EXACT;
  1339. if (sample_type & PERF_SAMPLE_REGS_INTR) {
  1340. regs->ax = pebs->ax;
  1341. regs->bx = pebs->bx;
  1342. regs->cx = pebs->cx;
  1343. regs->dx = pebs->dx;
  1344. regs->si = pebs->si;
  1345. regs->di = pebs->di;
  1346. regs->bp = pebs->bp;
  1347. regs->sp = pebs->sp;
  1348. #ifndef CONFIG_X86_32
  1349. regs->r8 = pebs->r8;
  1350. regs->r9 = pebs->r9;
  1351. regs->r10 = pebs->r10;
  1352. regs->r11 = pebs->r11;
  1353. regs->r12 = pebs->r12;
  1354. regs->r13 = pebs->r13;
  1355. regs->r14 = pebs->r14;
  1356. regs->r15 = pebs->r15;
  1357. #endif
  1358. }
  1359. if (event->attr.precise_ip > 1) {
  1360. /*
  1361. * Haswell and later processors have an 'eventing IP'
  1362. * (real IP) which fixes the off-by-1 skid in hardware.
  1363. * Use it when precise_ip >= 2 :
  1364. */
  1365. if (x86_pmu.intel_cap.pebs_format >= 2) {
  1366. set_linear_ip(regs, pebs->real_ip);
  1367. regs->flags |= PERF_EFLAGS_EXACT;
  1368. } else {
  1369. /* Otherwise, use PEBS off-by-1 IP: */
  1370. set_linear_ip(regs, pebs->ip);
  1371. /*
  1372. * With precise_ip >= 2, try to fix up the off-by-1 IP
  1373. * using the LBR. If successful, the fixup function
  1374. * corrects regs->ip and calls set_linear_ip() on regs:
  1375. */
  1376. if (intel_pmu_pebs_fixup_ip(regs))
  1377. regs->flags |= PERF_EFLAGS_EXACT;
  1378. }
  1379. } else {
  1380. /*
  1381. * When precise_ip == 1, return the PEBS off-by-1 IP,
  1382. * no fixup attempted:
  1383. */
  1384. set_linear_ip(regs, pebs->ip);
  1385. }
  1386. if ((sample_type & PERF_SAMPLE_ADDR_TYPE) &&
  1387. x86_pmu.intel_cap.pebs_format >= 1) {
  1388. data->addr = pebs->dla;
  1389. data->sample_flags |= PERF_SAMPLE_ADDR;
  1390. }
  1391. if (x86_pmu.intel_cap.pebs_format >= 2) {
  1392. /* Only set the TSX weight when no memory weight. */
  1393. if ((sample_type & PERF_SAMPLE_WEIGHT_TYPE) && !fll) {
  1394. data->weight.full = intel_get_tsx_weight(pebs->tsx_tuning);
  1395. data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE;
  1396. }
  1397. if (sample_type & PERF_SAMPLE_TRANSACTION) {
  1398. data->txn = intel_get_tsx_transaction(pebs->tsx_tuning,
  1399. pebs->ax);
  1400. data->sample_flags |= PERF_SAMPLE_TRANSACTION;
  1401. }
  1402. }
  1403. /*
  1404. * v3 supplies an accurate time stamp, so we use that
  1405. * for the time stamp.
  1406. *
  1407. * We can only do this for the default trace clock.
  1408. */
  1409. if (x86_pmu.intel_cap.pebs_format >= 3)
  1410. setup_pebs_time(event, data, pebs->tsc);
  1411. if (has_branch_stack(event)) {
  1412. data->br_stack = &cpuc->lbr_stack;
  1413. data->sample_flags |= PERF_SAMPLE_BRANCH_STACK;
  1414. }
  1415. }
  1416. static void adaptive_pebs_save_regs(struct pt_regs *regs,
  1417. struct pebs_gprs *gprs)
  1418. {
  1419. regs->ax = gprs->ax;
  1420. regs->bx = gprs->bx;
  1421. regs->cx = gprs->cx;
  1422. regs->dx = gprs->dx;
  1423. regs->si = gprs->si;
  1424. regs->di = gprs->di;
  1425. regs->bp = gprs->bp;
  1426. regs->sp = gprs->sp;
  1427. #ifndef CONFIG_X86_32
  1428. regs->r8 = gprs->r8;
  1429. regs->r9 = gprs->r9;
  1430. regs->r10 = gprs->r10;
  1431. regs->r11 = gprs->r11;
  1432. regs->r12 = gprs->r12;
  1433. regs->r13 = gprs->r13;
  1434. regs->r14 = gprs->r14;
  1435. regs->r15 = gprs->r15;
  1436. #endif
  1437. }
  1438. #define PEBS_LATENCY_MASK 0xffff
  1439. #define PEBS_CACHE_LATENCY_OFFSET 32
  1440. /*
  1441. * With adaptive PEBS the layout depends on what fields are configured.
  1442. */
  1443. static void setup_pebs_adaptive_sample_data(struct perf_event *event,
  1444. struct pt_regs *iregs, void *__pebs,
  1445. struct perf_sample_data *data,
  1446. struct pt_regs *regs)
  1447. {
  1448. struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
  1449. struct pebs_basic *basic = __pebs;
  1450. void *next_record = basic + 1;
  1451. u64 sample_type;
  1452. u64 format_size;
  1453. struct pebs_meminfo *meminfo = NULL;
  1454. struct pebs_gprs *gprs = NULL;
  1455. struct x86_perf_regs *perf_regs;
  1456. if (basic == NULL)
  1457. return;
  1458. perf_regs = container_of(regs, struct x86_perf_regs, regs);
  1459. perf_regs->xmm_regs = NULL;
  1460. sample_type = event->attr.sample_type;
  1461. format_size = basic->format_size;
  1462. perf_sample_data_init(data, 0, event->hw.last_period);
  1463. data->period = event->hw.last_period;
  1464. setup_pebs_time(event, data, basic->tsc);
  1465. /*
  1466. * We must however always use iregs for the unwinder to stay sane; the
  1467. * record BP,SP,IP can point into thin air when the record is from a
  1468. * previous PMI context or an (I)RET happened between the record and
  1469. * PMI.
  1470. */
  1471. if (sample_type & PERF_SAMPLE_CALLCHAIN) {
  1472. data->callchain = perf_callchain(event, iregs);
  1473. data->sample_flags |= PERF_SAMPLE_CALLCHAIN;
  1474. }
  1475. *regs = *iregs;
  1476. /* The ip in basic is EventingIP */
  1477. set_linear_ip(regs, basic->ip);
  1478. regs->flags = PERF_EFLAGS_EXACT;
  1479. /*
  1480. * The record for MEMINFO is in front of GP
  1481. * But PERF_SAMPLE_TRANSACTION needs gprs->ax.
  1482. * Save the pointer here but process later.
  1483. */
  1484. if (format_size & PEBS_DATACFG_MEMINFO) {
  1485. meminfo = next_record;
  1486. next_record = meminfo + 1;
  1487. }
  1488. if (format_size & PEBS_DATACFG_GP) {
  1489. gprs = next_record;
  1490. next_record = gprs + 1;
  1491. if (event->attr.precise_ip < 2) {
  1492. set_linear_ip(regs, gprs->ip);
  1493. regs->flags &= ~PERF_EFLAGS_EXACT;
  1494. }
  1495. if (sample_type & PERF_SAMPLE_REGS_INTR)
  1496. adaptive_pebs_save_regs(regs, gprs);
  1497. }
  1498. if (format_size & PEBS_DATACFG_MEMINFO) {
  1499. if (sample_type & PERF_SAMPLE_WEIGHT_TYPE) {
  1500. u64 weight = meminfo->latency;
  1501. if (x86_pmu.flags & PMU_FL_INSTR_LATENCY) {
  1502. data->weight.var2_w = weight & PEBS_LATENCY_MASK;
  1503. weight >>= PEBS_CACHE_LATENCY_OFFSET;
  1504. }
  1505. /*
  1506. * Although meminfo::latency is defined as a u64,
  1507. * only the lower 32 bits include the valid data
  1508. * in practice on Ice Lake and earlier platforms.
  1509. */
  1510. if (sample_type & PERF_SAMPLE_WEIGHT) {
  1511. data->weight.full = weight ?:
  1512. intel_get_tsx_weight(meminfo->tsx_tuning);
  1513. } else {
  1514. data->weight.var1_dw = (u32)(weight & PEBS_LATENCY_MASK) ?:
  1515. intel_get_tsx_weight(meminfo->tsx_tuning);
  1516. }
  1517. data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE;
  1518. }
  1519. if (sample_type & PERF_SAMPLE_DATA_SRC) {
  1520. data->data_src.val = get_data_src(event, meminfo->aux);
  1521. data->sample_flags |= PERF_SAMPLE_DATA_SRC;
  1522. }
  1523. if (sample_type & PERF_SAMPLE_ADDR_TYPE) {
  1524. data->addr = meminfo->address;
  1525. data->sample_flags |= PERF_SAMPLE_ADDR;
  1526. }
  1527. if (sample_type & PERF_SAMPLE_TRANSACTION) {
  1528. data->txn = intel_get_tsx_transaction(meminfo->tsx_tuning,
  1529. gprs ? gprs->ax : 0);
  1530. data->sample_flags |= PERF_SAMPLE_TRANSACTION;
  1531. }
  1532. }
  1533. if (format_size & PEBS_DATACFG_XMMS) {
  1534. struct pebs_xmm *xmm = next_record;
  1535. next_record = xmm + 1;
  1536. perf_regs->xmm_regs = xmm->xmm;
  1537. }
  1538. if (format_size & PEBS_DATACFG_LBRS) {
  1539. struct lbr_entry *lbr = next_record;
  1540. int num_lbr = ((format_size >> PEBS_DATACFG_LBR_SHIFT)
  1541. & 0xff) + 1;
  1542. next_record = next_record + num_lbr * sizeof(struct lbr_entry);
  1543. if (has_branch_stack(event)) {
  1544. intel_pmu_store_pebs_lbrs(lbr);
  1545. data->br_stack = &cpuc->lbr_stack;
  1546. data->sample_flags |= PERF_SAMPLE_BRANCH_STACK;
  1547. }
  1548. }
  1549. WARN_ONCE(next_record != __pebs + (format_size >> 48),
  1550. "PEBS record size %llu, expected %llu, config %llx\n",
  1551. format_size >> 48,
  1552. (u64)(next_record - __pebs),
  1553. basic->format_size);
  1554. }
  1555. static inline void *
  1556. get_next_pebs_record_by_bit(void *base, void *top, int bit)
  1557. {
  1558. struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
  1559. void *at;
  1560. u64 pebs_status;
  1561. /*
  1562. * fmt0 does not have a status bitfield (does not use
  1563. * perf_record_nhm format)
  1564. */
  1565. if (x86_pmu.intel_cap.pebs_format < 1)
  1566. return base;
  1567. if (base == NULL)
  1568. return NULL;
  1569. for (at = base; at < top; at += cpuc->pebs_record_size) {
  1570. unsigned long status = get_pebs_status(at);
  1571. if (test_bit(bit, (unsigned long *)&status)) {
  1572. /* PEBS v3 has accurate status bits */
  1573. if (x86_pmu.intel_cap.pebs_format >= 3)
  1574. return at;
  1575. if (status == (1 << bit))
  1576. return at;
  1577. /* clear non-PEBS bit and re-check */
  1578. pebs_status = status & cpuc->pebs_enabled;
  1579. pebs_status &= PEBS_COUNTER_MASK;
  1580. if (pebs_status == (1 << bit))
  1581. return at;
  1582. }
  1583. }
  1584. return NULL;
  1585. }
  1586. void intel_pmu_auto_reload_read(struct perf_event *event)
  1587. {
  1588. WARN_ON(!(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD));
  1589. perf_pmu_disable(event->pmu);
  1590. intel_pmu_drain_pebs_buffer();
  1591. perf_pmu_enable(event->pmu);
  1592. }
  1593. /*
  1594. * Special variant of intel_pmu_save_and_restart() for auto-reload.
  1595. */
  1596. static int
  1597. intel_pmu_save_and_restart_reload(struct perf_event *event, int count)
  1598. {
  1599. struct hw_perf_event *hwc = &event->hw;
  1600. int shift = 64 - x86_pmu.cntval_bits;
  1601. u64 period = hwc->sample_period;
  1602. u64 prev_raw_count, new_raw_count;
  1603. s64 new, old;
  1604. WARN_ON(!period);
  1605. /*
  1606. * drain_pebs() only happens when the PMU is disabled.
  1607. */
  1608. WARN_ON(this_cpu_read(cpu_hw_events.enabled));
  1609. prev_raw_count = local64_read(&hwc->prev_count);
  1610. rdpmcl(hwc->event_base_rdpmc, new_raw_count);
  1611. local64_set(&hwc->prev_count, new_raw_count);
  1612. /*
  1613. * Since the counter increments a negative counter value and
  1614. * overflows on the sign switch, giving the interval:
  1615. *
  1616. * [-period, 0]
  1617. *
  1618. * the difference between two consecutive reads is:
  1619. *
  1620. * A) value2 - value1;
  1621. * when no overflows have happened in between,
  1622. *
  1623. * B) (0 - value1) + (value2 - (-period));
  1624. * when one overflow happened in between,
  1625. *
  1626. * C) (0 - value1) + (n - 1) * (period) + (value2 - (-period));
  1627. * when @n overflows happened in between.
  1628. *
  1629. * Here A) is the obvious difference, B) is the extension to the
  1630. * discrete interval, where the first term is to the top of the
  1631. * interval and the second term is from the bottom of the next
  1632. * interval and C) the extension to multiple intervals, where the
  1633. * middle term is the whole intervals covered.
  1634. *
  1635. * An equivalent of C, by reduction, is:
  1636. *
  1637. * value2 - value1 + n * period
  1638. */
  1639. new = ((s64)(new_raw_count << shift) >> shift);
  1640. old = ((s64)(prev_raw_count << shift) >> shift);
  1641. local64_add(new - old + count * period, &event->count);
  1642. local64_set(&hwc->period_left, -new);
  1643. perf_event_update_userpage(event);
  1644. return 0;
  1645. }
  1646. static __always_inline void
  1647. __intel_pmu_pebs_event(struct perf_event *event,
  1648. struct pt_regs *iregs,
  1649. struct perf_sample_data *data,
  1650. void *base, void *top,
  1651. int bit, int count,
  1652. void (*setup_sample)(struct perf_event *,
  1653. struct pt_regs *,
  1654. void *,
  1655. struct perf_sample_data *,
  1656. struct pt_regs *))
  1657. {
  1658. struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
  1659. struct hw_perf_event *hwc = &event->hw;
  1660. struct x86_perf_regs perf_regs;
  1661. struct pt_regs *regs = &perf_regs.regs;
  1662. void *at = get_next_pebs_record_by_bit(base, top, bit);
  1663. static struct pt_regs dummy_iregs;
  1664. if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
  1665. /*
  1666. * Now, auto-reload is only enabled in fixed period mode.
  1667. * The reload value is always hwc->sample_period.
  1668. * May need to change it, if auto-reload is enabled in
  1669. * freq mode later.
  1670. */
  1671. intel_pmu_save_and_restart_reload(event, count);
  1672. } else if (!intel_pmu_save_and_restart(event))
  1673. return;
  1674. if (!iregs)
  1675. iregs = &dummy_iregs;
  1676. while (count > 1) {
  1677. setup_sample(event, iregs, at, data, regs);
  1678. perf_event_output(event, data, regs);
  1679. at += cpuc->pebs_record_size;
  1680. at = get_next_pebs_record_by_bit(at, top, bit);
  1681. count--;
  1682. }
  1683. setup_sample(event, iregs, at, data, regs);
  1684. if (iregs == &dummy_iregs) {
  1685. /*
  1686. * The PEBS records may be drained in the non-overflow context,
  1687. * e.g., large PEBS + context switch. Perf should treat the
  1688. * last record the same as other PEBS records, and doesn't
  1689. * invoke the generic overflow handler.
  1690. */
  1691. perf_event_output(event, data, regs);
  1692. } else {
  1693. /*
  1694. * All but the last records are processed.
  1695. * The last one is left to be able to call the overflow handler.
  1696. */
  1697. if (perf_event_overflow(event, data, regs))
  1698. x86_pmu_stop(event, 0);
  1699. }
  1700. }
  1701. static void intel_pmu_drain_pebs_core(struct pt_regs *iregs, struct perf_sample_data *data)
  1702. {
  1703. struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
  1704. struct debug_store *ds = cpuc->ds;
  1705. struct perf_event *event = cpuc->events[0]; /* PMC0 only */
  1706. struct pebs_record_core *at, *top;
  1707. int n;
  1708. if (!x86_pmu.pebs_active)
  1709. return;
  1710. at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
  1711. top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
  1712. /*
  1713. * Whatever else happens, drain the thing
  1714. */
  1715. ds->pebs_index = ds->pebs_buffer_base;
  1716. if (!test_bit(0, cpuc->active_mask))
  1717. return;
  1718. WARN_ON_ONCE(!event);
  1719. if (!event->attr.precise_ip)
  1720. return;
  1721. n = top - at;
  1722. if (n <= 0) {
  1723. if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
  1724. intel_pmu_save_and_restart_reload(event, 0);
  1725. return;
  1726. }
  1727. __intel_pmu_pebs_event(event, iregs, data, at, top, 0, n,
  1728. setup_pebs_fixed_sample_data);
  1729. }
  1730. static void intel_pmu_pebs_event_update_no_drain(struct cpu_hw_events *cpuc, int size)
  1731. {
  1732. struct perf_event *event;
  1733. int bit;
  1734. /*
  1735. * The drain_pebs() could be called twice in a short period
  1736. * for auto-reload event in pmu::read(). There are no
  1737. * overflows have happened in between.
  1738. * It needs to call intel_pmu_save_and_restart_reload() to
  1739. * update the event->count for this case.
  1740. */
  1741. for_each_set_bit(bit, (unsigned long *)&cpuc->pebs_enabled, size) {
  1742. event = cpuc->events[bit];
  1743. if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
  1744. intel_pmu_save_and_restart_reload(event, 0);
  1745. }
  1746. }
  1747. static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_data *data)
  1748. {
  1749. struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
  1750. struct debug_store *ds = cpuc->ds;
  1751. struct perf_event *event;
  1752. void *base, *at, *top;
  1753. short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
  1754. short error[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
  1755. int bit, i, size;
  1756. u64 mask;
  1757. if (!x86_pmu.pebs_active)
  1758. return;
  1759. base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
  1760. top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
  1761. ds->pebs_index = ds->pebs_buffer_base;
  1762. mask = (1ULL << x86_pmu.max_pebs_events) - 1;
  1763. size = x86_pmu.max_pebs_events;
  1764. if (x86_pmu.flags & PMU_FL_PEBS_ALL) {
  1765. mask |= ((1ULL << x86_pmu.num_counters_fixed) - 1) << INTEL_PMC_IDX_FIXED;
  1766. size = INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed;
  1767. }
  1768. if (unlikely(base >= top)) {
  1769. intel_pmu_pebs_event_update_no_drain(cpuc, size);
  1770. return;
  1771. }
  1772. for (at = base; at < top; at += x86_pmu.pebs_record_size) {
  1773. struct pebs_record_nhm *p = at;
  1774. u64 pebs_status;
  1775. pebs_status = p->status & cpuc->pebs_enabled;
  1776. pebs_status &= mask;
  1777. /* PEBS v3 has more accurate status bits */
  1778. if (x86_pmu.intel_cap.pebs_format >= 3) {
  1779. for_each_set_bit(bit, (unsigned long *)&pebs_status, size)
  1780. counts[bit]++;
  1781. continue;
  1782. }
  1783. /*
  1784. * On some CPUs the PEBS status can be zero when PEBS is
  1785. * racing with clearing of GLOBAL_STATUS.
  1786. *
  1787. * Normally we would drop that record, but in the
  1788. * case when there is only a single active PEBS event
  1789. * we can assume it's for that event.
  1790. */
  1791. if (!pebs_status && cpuc->pebs_enabled &&
  1792. !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1)))
  1793. pebs_status = p->status = cpuc->pebs_enabled;
  1794. bit = find_first_bit((unsigned long *)&pebs_status,
  1795. x86_pmu.max_pebs_events);
  1796. if (bit >= x86_pmu.max_pebs_events)
  1797. continue;
  1798. /*
  1799. * The PEBS hardware does not deal well with the situation
  1800. * when events happen near to each other and multiple bits
  1801. * are set. But it should happen rarely.
  1802. *
  1803. * If these events include one PEBS and multiple non-PEBS
  1804. * events, it doesn't impact PEBS record. The record will
  1805. * be handled normally. (slow path)
  1806. *
  1807. * If these events include two or more PEBS events, the
  1808. * records for the events can be collapsed into a single
  1809. * one, and it's not possible to reconstruct all events
  1810. * that caused the PEBS record. It's called collision.
  1811. * If collision happened, the record will be dropped.
  1812. */
  1813. if (pebs_status != (1ULL << bit)) {
  1814. for_each_set_bit(i, (unsigned long *)&pebs_status, size)
  1815. error[i]++;
  1816. continue;
  1817. }
  1818. counts[bit]++;
  1819. }
  1820. for_each_set_bit(bit, (unsigned long *)&mask, size) {
  1821. if ((counts[bit] == 0) && (error[bit] == 0))
  1822. continue;
  1823. event = cpuc->events[bit];
  1824. if (WARN_ON_ONCE(!event))
  1825. continue;
  1826. if (WARN_ON_ONCE(!event->attr.precise_ip))
  1827. continue;
  1828. /* log dropped samples number */
  1829. if (error[bit]) {
  1830. perf_log_lost_samples(event, error[bit]);
  1831. if (iregs && perf_event_account_interrupt(event))
  1832. x86_pmu_stop(event, 0);
  1833. }
  1834. if (counts[bit]) {
  1835. __intel_pmu_pebs_event(event, iregs, data, base,
  1836. top, bit, counts[bit],
  1837. setup_pebs_fixed_sample_data);
  1838. }
  1839. }
  1840. }
  1841. static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_data *data)
  1842. {
  1843. short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
  1844. struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
  1845. int max_pebs_events = hybrid(cpuc->pmu, max_pebs_events);
  1846. int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
  1847. struct debug_store *ds = cpuc->ds;
  1848. struct perf_event *event;
  1849. void *base, *at, *top;
  1850. int bit, size;
  1851. u64 mask;
  1852. if (!x86_pmu.pebs_active)
  1853. return;
  1854. base = (struct pebs_basic *)(unsigned long)ds->pebs_buffer_base;
  1855. top = (struct pebs_basic *)(unsigned long)ds->pebs_index;
  1856. ds->pebs_index = ds->pebs_buffer_base;
  1857. mask = ((1ULL << max_pebs_events) - 1) |
  1858. (((1ULL << num_counters_fixed) - 1) << INTEL_PMC_IDX_FIXED);
  1859. size = INTEL_PMC_IDX_FIXED + num_counters_fixed;
  1860. if (unlikely(base >= top)) {
  1861. intel_pmu_pebs_event_update_no_drain(cpuc, size);
  1862. return;
  1863. }
  1864. for (at = base; at < top; at += cpuc->pebs_record_size) {
  1865. u64 pebs_status;
  1866. pebs_status = get_pebs_status(at) & cpuc->pebs_enabled;
  1867. pebs_status &= mask;
  1868. for_each_set_bit(bit, (unsigned long *)&pebs_status, size)
  1869. counts[bit]++;
  1870. }
  1871. for_each_set_bit(bit, (unsigned long *)&mask, size) {
  1872. if (counts[bit] == 0)
  1873. continue;
  1874. event = cpuc->events[bit];
  1875. if (WARN_ON_ONCE(!event))
  1876. continue;
  1877. if (WARN_ON_ONCE(!event->attr.precise_ip))
  1878. continue;
  1879. __intel_pmu_pebs_event(event, iregs, data, base,
  1880. top, bit, counts[bit],
  1881. setup_pebs_adaptive_sample_data);
  1882. }
  1883. }
  1884. /*
  1885. * BTS, PEBS probe and setup
  1886. */
  1887. void __init intel_ds_init(void)
  1888. {
  1889. /*
  1890. * No support for 32bit formats
  1891. */
  1892. if (!boot_cpu_has(X86_FEATURE_DTES64))
  1893. return;
  1894. x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS);
  1895. x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
  1896. x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
  1897. if (x86_pmu.version <= 4)
  1898. x86_pmu.pebs_no_isolation = 1;
  1899. if (x86_pmu.pebs) {
  1900. char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-';
  1901. char *pebs_qual = "";
  1902. int format = x86_pmu.intel_cap.pebs_format;
  1903. if (format < 4)
  1904. x86_pmu.intel_cap.pebs_baseline = 0;
  1905. switch (format) {
  1906. case 0:
  1907. pr_cont("PEBS fmt0%c, ", pebs_type);
  1908. x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
  1909. /*
  1910. * Using >PAGE_SIZE buffers makes the WRMSR to
  1911. * PERF_GLOBAL_CTRL in intel_pmu_enable_all()
  1912. * mysteriously hang on Core2.
  1913. *
  1914. * As a workaround, we don't do this.
  1915. */
  1916. x86_pmu.pebs_buffer_size = PAGE_SIZE;
  1917. x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
  1918. break;
  1919. case 1:
  1920. pr_cont("PEBS fmt1%c, ", pebs_type);
  1921. x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
  1922. x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
  1923. break;
  1924. case 2:
  1925. pr_cont("PEBS fmt2%c, ", pebs_type);
  1926. x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
  1927. x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
  1928. break;
  1929. case 3:
  1930. pr_cont("PEBS fmt3%c, ", pebs_type);
  1931. x86_pmu.pebs_record_size =
  1932. sizeof(struct pebs_record_skl);
  1933. x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
  1934. x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME;
  1935. break;
  1936. case 4:
  1937. case 5:
  1938. x86_pmu.drain_pebs = intel_pmu_drain_pebs_icl;
  1939. x86_pmu.pebs_record_size = sizeof(struct pebs_basic);
  1940. if (x86_pmu.intel_cap.pebs_baseline) {
  1941. x86_pmu.large_pebs_flags |=
  1942. PERF_SAMPLE_BRANCH_STACK |
  1943. PERF_SAMPLE_TIME;
  1944. x86_pmu.flags |= PMU_FL_PEBS_ALL;
  1945. x86_pmu.pebs_capable = ~0ULL;
  1946. pebs_qual = "-baseline";
  1947. x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_EXTENDED_REGS;
  1948. } else {
  1949. /* Only basic record supported */
  1950. x86_pmu.large_pebs_flags &=
  1951. ~(PERF_SAMPLE_ADDR |
  1952. PERF_SAMPLE_TIME |
  1953. PERF_SAMPLE_DATA_SRC |
  1954. PERF_SAMPLE_TRANSACTION |
  1955. PERF_SAMPLE_REGS_USER |
  1956. PERF_SAMPLE_REGS_INTR);
  1957. }
  1958. pr_cont("PEBS fmt4%c%s, ", pebs_type, pebs_qual);
  1959. if (!is_hybrid() && x86_pmu.intel_cap.pebs_output_pt_available) {
  1960. pr_cont("PEBS-via-PT, ");
  1961. x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_AUX_OUTPUT;
  1962. }
  1963. break;
  1964. default:
  1965. pr_cont("no PEBS fmt%d%c, ", format, pebs_type);
  1966. x86_pmu.pebs = 0;
  1967. }
  1968. }
  1969. }
  1970. void perf_restore_debug_store(void)
  1971. {
  1972. struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
  1973. if (!x86_pmu.bts && !x86_pmu.pebs)
  1974. return;
  1975. wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
  1976. }