cpucheck.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /* -*- linux-c -*- ------------------------------------------------------- *
  3. *
  4. * Copyright (C) 1991, 1992 Linus Torvalds
  5. * Copyright 2007 rPath, Inc. - All Rights Reserved
  6. *
  7. * ----------------------------------------------------------------------- */
  8. /*
  9. * Check for obligatory CPU features and abort if the features are not
  10. * present. This code should be compilable as 16-, 32- or 64-bit
  11. * code, so be very careful with types and inline assembly.
  12. *
  13. * This code should not contain any messages; that requires an
  14. * additional wrapper.
  15. *
  16. * As written, this code is not safe for inclusion into the kernel
  17. * proper (after FPU initialization, in particular).
  18. */
  19. #ifdef _SETUP
  20. # include "boot.h"
  21. #endif
  22. #include <linux/types.h>
  23. #include <asm/intel-family.h>
  24. #include <asm/processor-flags.h>
  25. #include <asm/required-features.h>
  26. #include <asm/msr-index.h>
  27. #include "string.h"
  28. #include "msr.h"
  29. static u32 err_flags[NCAPINTS];
  30. static const int req_level = CONFIG_X86_MINIMUM_CPU_FAMILY;
  31. static const u32 req_flags[NCAPINTS] =
  32. {
  33. REQUIRED_MASK0,
  34. REQUIRED_MASK1,
  35. 0, /* REQUIRED_MASK2 not implemented in this file */
  36. 0, /* REQUIRED_MASK3 not implemented in this file */
  37. REQUIRED_MASK4,
  38. 0, /* REQUIRED_MASK5 not implemented in this file */
  39. REQUIRED_MASK6,
  40. 0, /* REQUIRED_MASK7 not implemented in this file */
  41. 0, /* REQUIRED_MASK8 not implemented in this file */
  42. 0, /* REQUIRED_MASK9 not implemented in this file */
  43. 0, /* REQUIRED_MASK10 not implemented in this file */
  44. 0, /* REQUIRED_MASK11 not implemented in this file */
  45. 0, /* REQUIRED_MASK12 not implemented in this file */
  46. 0, /* REQUIRED_MASK13 not implemented in this file */
  47. 0, /* REQUIRED_MASK14 not implemented in this file */
  48. 0, /* REQUIRED_MASK15 not implemented in this file */
  49. REQUIRED_MASK16,
  50. };
  51. #define A32(a, b, c, d) (((d) << 24)+((c) << 16)+((b) << 8)+(a))
  52. static int is_amd(void)
  53. {
  54. return cpu_vendor[0] == A32('A', 'u', 't', 'h') &&
  55. cpu_vendor[1] == A32('e', 'n', 't', 'i') &&
  56. cpu_vendor[2] == A32('c', 'A', 'M', 'D');
  57. }
  58. static int is_centaur(void)
  59. {
  60. return cpu_vendor[0] == A32('C', 'e', 'n', 't') &&
  61. cpu_vendor[1] == A32('a', 'u', 'r', 'H') &&
  62. cpu_vendor[2] == A32('a', 'u', 'l', 's');
  63. }
  64. static int is_transmeta(void)
  65. {
  66. return cpu_vendor[0] == A32('G', 'e', 'n', 'u') &&
  67. cpu_vendor[1] == A32('i', 'n', 'e', 'T') &&
  68. cpu_vendor[2] == A32('M', 'x', '8', '6');
  69. }
  70. static int is_intel(void)
  71. {
  72. return cpu_vendor[0] == A32('G', 'e', 'n', 'u') &&
  73. cpu_vendor[1] == A32('i', 'n', 'e', 'I') &&
  74. cpu_vendor[2] == A32('n', 't', 'e', 'l');
  75. }
  76. /* Returns a bitmask of which words we have error bits in */
  77. static int check_cpuflags(void)
  78. {
  79. u32 err;
  80. int i;
  81. err = 0;
  82. for (i = 0; i < NCAPINTS; i++) {
  83. err_flags[i] = req_flags[i] & ~cpu.flags[i];
  84. if (err_flags[i])
  85. err |= 1 << i;
  86. }
  87. return err;
  88. }
  89. /*
  90. * Returns -1 on error.
  91. *
  92. * *cpu_level is set to the current CPU level; *req_level to the required
  93. * level. x86-64 is considered level 64 for this purpose.
  94. *
  95. * *err_flags_ptr is set to the flags error array if there are flags missing.
  96. */
  97. int check_cpu(int *cpu_level_ptr, int *req_level_ptr, u32 **err_flags_ptr)
  98. {
  99. int err;
  100. memset(&cpu.flags, 0, sizeof(cpu.flags));
  101. cpu.level = 3;
  102. if (has_eflag(X86_EFLAGS_AC))
  103. cpu.level = 4;
  104. get_cpuflags();
  105. err = check_cpuflags();
  106. if (test_bit(X86_FEATURE_LM, cpu.flags))
  107. cpu.level = 64;
  108. if (err == 0x01 &&
  109. !(err_flags[0] &
  110. ~((1 << X86_FEATURE_XMM)|(1 << X86_FEATURE_XMM2))) &&
  111. is_amd()) {
  112. /* If this is an AMD and we're only missing SSE+SSE2, try to
  113. turn them on */
  114. struct msr m;
  115. boot_rdmsr(MSR_K7_HWCR, &m);
  116. m.l &= ~(1 << 15);
  117. boot_wrmsr(MSR_K7_HWCR, &m);
  118. get_cpuflags(); /* Make sure it really did something */
  119. err = check_cpuflags();
  120. } else if (err == 0x01 &&
  121. !(err_flags[0] & ~(1 << X86_FEATURE_CX8)) &&
  122. is_centaur() && cpu.model >= 6) {
  123. /* If this is a VIA C3, we might have to enable CX8
  124. explicitly */
  125. struct msr m;
  126. boot_rdmsr(MSR_VIA_FCR, &m);
  127. m.l |= (1 << 1) | (1 << 7);
  128. boot_wrmsr(MSR_VIA_FCR, &m);
  129. set_bit(X86_FEATURE_CX8, cpu.flags);
  130. err = check_cpuflags();
  131. } else if (err == 0x01 && is_transmeta()) {
  132. /* Transmeta might have masked feature bits in word 0 */
  133. struct msr m, m_tmp;
  134. u32 level = 1;
  135. boot_rdmsr(0x80860004, &m);
  136. m_tmp = m;
  137. m_tmp.l = ~0;
  138. boot_wrmsr(0x80860004, &m_tmp);
  139. asm("cpuid"
  140. : "+a" (level), "=d" (cpu.flags[0])
  141. : : "ecx", "ebx");
  142. boot_wrmsr(0x80860004, &m);
  143. err = check_cpuflags();
  144. } else if (err == 0x01 &&
  145. !(err_flags[0] & ~(1 << X86_FEATURE_PAE)) &&
  146. is_intel() && cpu.level == 6 &&
  147. (cpu.model == 9 || cpu.model == 13)) {
  148. /* PAE is disabled on this Pentium M but can be forced */
  149. if (cmdline_find_option_bool("forcepae")) {
  150. puts("WARNING: Forcing PAE in CPU flags\n");
  151. set_bit(X86_FEATURE_PAE, cpu.flags);
  152. err = check_cpuflags();
  153. }
  154. else {
  155. puts("WARNING: PAE disabled. Use parameter 'forcepae' to enable at your own risk!\n");
  156. }
  157. }
  158. if (!err)
  159. err = check_knl_erratum();
  160. if (err_flags_ptr)
  161. *err_flags_ptr = err ? err_flags : NULL;
  162. if (cpu_level_ptr)
  163. *cpu_level_ptr = cpu.level;
  164. if (req_level_ptr)
  165. *req_level_ptr = req_level;
  166. return (cpu.level < req_level || err) ? -1 : 0;
  167. }
  168. int check_knl_erratum(void)
  169. {
  170. /*
  171. * First check for the affected model/family:
  172. */
  173. if (!is_intel() ||
  174. cpu.family != 6 ||
  175. cpu.model != INTEL_FAM6_XEON_PHI_KNL)
  176. return 0;
  177. /*
  178. * This erratum affects the Accessed/Dirty bits, and can
  179. * cause stray bits to be set in !Present PTEs. We have
  180. * enough bits in our 64-bit PTEs (which we have on real
  181. * 64-bit mode or PAE) to avoid using these troublesome
  182. * bits. But, we do not have enough space in our 32-bit
  183. * PTEs. So, refuse to run on 32-bit non-PAE kernels.
  184. */
  185. if (IS_ENABLED(CONFIG_X86_64) || IS_ENABLED(CONFIG_X86_PAE))
  186. return 0;
  187. puts("This 32-bit kernel can not run on this Xeon Phi x200\n"
  188. "processor due to a processor erratum. Use a 64-bit\n"
  189. "kernel, or enable PAE in this 32-bit kernel.\n\n");
  190. return -1;
  191. }