cache-sh7705.c 4.8 KB

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  1. /*
  2. * arch/sh/mm/cache-sh7705.c
  3. *
  4. * Copyright (C) 1999, 2000 Niibe Yutaka
  5. * Copyright (C) 2004 Alex Song
  6. *
  7. * This file is subject to the terms and conditions of the GNU General Public
  8. * License. See the file "COPYING" in the main directory of this archive
  9. * for more details.
  10. *
  11. */
  12. #include <linux/init.h>
  13. #include <linux/mman.h>
  14. #include <linux/mm.h>
  15. #include <linux/fs.h>
  16. #include <linux/pagemap.h>
  17. #include <linux/threads.h>
  18. #include <asm/addrspace.h>
  19. #include <asm/page.h>
  20. #include <asm/processor.h>
  21. #include <asm/cache.h>
  22. #include <asm/io.h>
  23. #include <linux/uaccess.h>
  24. #include <asm/mmu_context.h>
  25. #include <asm/cacheflush.h>
  26. /*
  27. * The 32KB cache on the SH7705 suffers from the same synonym problem
  28. * as SH4 CPUs
  29. */
  30. static inline void cache_wback_all(void)
  31. {
  32. unsigned long ways, waysize, addrstart;
  33. ways = current_cpu_data.dcache.ways;
  34. waysize = current_cpu_data.dcache.sets;
  35. waysize <<= current_cpu_data.dcache.entry_shift;
  36. addrstart = CACHE_OC_ADDRESS_ARRAY;
  37. do {
  38. unsigned long addr;
  39. for (addr = addrstart;
  40. addr < addrstart + waysize;
  41. addr += current_cpu_data.dcache.linesz) {
  42. unsigned long data;
  43. int v = SH_CACHE_UPDATED | SH_CACHE_VALID;
  44. data = __raw_readl(addr);
  45. if ((data & v) == v)
  46. __raw_writel(data & ~v, addr);
  47. }
  48. addrstart += current_cpu_data.dcache.way_incr;
  49. } while (--ways);
  50. }
  51. /*
  52. * Write back the range of D-cache, and purge the I-cache.
  53. *
  54. * Called from kernel/module.c:sys_init_module and routine for a.out format.
  55. */
  56. static void sh7705_flush_icache_range(void *args)
  57. {
  58. struct flusher_data *data = args;
  59. unsigned long start, end;
  60. start = data->addr1;
  61. end = data->addr2;
  62. __flush_wback_region((void *)start, end - start);
  63. }
  64. /*
  65. * Writeback&Invalidate the D-cache of the page
  66. */
  67. static void __flush_dcache_page(unsigned long phys)
  68. {
  69. unsigned long ways, waysize, addrstart;
  70. unsigned long flags;
  71. phys |= SH_CACHE_VALID;
  72. /*
  73. * Here, phys is the physical address of the page. We check all the
  74. * tags in the cache for those with the same page number as this page
  75. * (by masking off the lowest 2 bits of the 19-bit tag; these bits are
  76. * derived from the offset within in the 4k page). Matching valid
  77. * entries are invalidated.
  78. *
  79. * Since 2 bits of the cache index are derived from the virtual page
  80. * number, knowing this would reduce the number of cache entries to be
  81. * searched by a factor of 4. However this function exists to deal with
  82. * potential cache aliasing, therefore the optimisation is probably not
  83. * possible.
  84. */
  85. local_irq_save(flags);
  86. jump_to_uncached();
  87. ways = current_cpu_data.dcache.ways;
  88. waysize = current_cpu_data.dcache.sets;
  89. waysize <<= current_cpu_data.dcache.entry_shift;
  90. addrstart = CACHE_OC_ADDRESS_ARRAY;
  91. do {
  92. unsigned long addr;
  93. for (addr = addrstart;
  94. addr < addrstart + waysize;
  95. addr += current_cpu_data.dcache.linesz) {
  96. unsigned long data;
  97. data = __raw_readl(addr) & (0x1ffffC00 | SH_CACHE_VALID);
  98. if (data == phys) {
  99. data &= ~(SH_CACHE_VALID | SH_CACHE_UPDATED);
  100. __raw_writel(data, addr);
  101. }
  102. }
  103. addrstart += current_cpu_data.dcache.way_incr;
  104. } while (--ways);
  105. back_to_cached();
  106. local_irq_restore(flags);
  107. }
  108. /*
  109. * Write back & invalidate the D-cache of the page.
  110. * (To avoid "alias" issues)
  111. */
  112. static void sh7705_flush_dcache_page(void *arg)
  113. {
  114. struct page *page = arg;
  115. struct address_space *mapping = page_mapping_file(page);
  116. if (mapping && !mapping_mapped(mapping))
  117. clear_bit(PG_dcache_clean, &page->flags);
  118. else
  119. __flush_dcache_page(__pa(page_address(page)));
  120. }
  121. static void sh7705_flush_cache_all(void *args)
  122. {
  123. unsigned long flags;
  124. local_irq_save(flags);
  125. jump_to_uncached();
  126. cache_wback_all();
  127. back_to_cached();
  128. local_irq_restore(flags);
  129. }
  130. /*
  131. * Write back and invalidate I/D-caches for the page.
  132. *
  133. * ADDRESS: Virtual Address (U0 address)
  134. */
  135. static void sh7705_flush_cache_page(void *args)
  136. {
  137. struct flusher_data *data = args;
  138. unsigned long pfn = data->addr2;
  139. __flush_dcache_page(pfn << PAGE_SHIFT);
  140. }
  141. /*
  142. * This is called when a page-cache page is about to be mapped into a
  143. * user process' address space. It offers an opportunity for a
  144. * port to ensure d-cache/i-cache coherency if necessary.
  145. *
  146. * Not entirely sure why this is necessary on SH3 with 32K cache but
  147. * without it we get occasional "Memory fault" when loading a program.
  148. */
  149. static void sh7705_flush_icache_page(void *page)
  150. {
  151. __flush_purge_region(page_address(page), PAGE_SIZE);
  152. }
  153. void __init sh7705_cache_init(void)
  154. {
  155. local_flush_icache_range = sh7705_flush_icache_range;
  156. local_flush_dcache_page = sh7705_flush_dcache_page;
  157. local_flush_cache_all = sh7705_flush_cache_all;
  158. local_flush_cache_mm = sh7705_flush_cache_all;
  159. local_flush_cache_dup_mm = sh7705_flush_cache_all;
  160. local_flush_cache_range = sh7705_flush_cache_all;
  161. local_flush_cache_page = sh7705_flush_cache_page;
  162. local_flush_icache_page = sh7705_flush_icache_page;
  163. }