traps_32.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * 'traps.c' handles hardware traps and faults after we have saved some
  4. * state in 'entry.S'.
  5. *
  6. * SuperH version: Copyright (C) 1999 Niibe Yutaka
  7. * Copyright (C) 2000 Philipp Rumpf
  8. * Copyright (C) 2000 David Howells
  9. * Copyright (C) 2002 - 2010 Paul Mundt
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/ptrace.h>
  13. #include <linux/hardirq.h>
  14. #include <linux/init.h>
  15. #include <linux/spinlock.h>
  16. #include <linux/kallsyms.h>
  17. #include <linux/io.h>
  18. #include <linux/bug.h>
  19. #include <linux/debug_locks.h>
  20. #include <linux/kdebug.h>
  21. #include <linux/limits.h>
  22. #include <linux/sysfs.h>
  23. #include <linux/uaccess.h>
  24. #include <linux/perf_event.h>
  25. #include <linux/sched/task_stack.h>
  26. #include <asm/alignment.h>
  27. #include <asm/fpu.h>
  28. #include <asm/kprobes.h>
  29. #include <asm/traps.h>
  30. #include <asm/bl_bit.h>
  31. #ifdef CONFIG_CPU_SH2
  32. # define TRAP_RESERVED_INST 4
  33. # define TRAP_ILLEGAL_SLOT_INST 6
  34. # define TRAP_ADDRESS_ERROR 9
  35. # ifdef CONFIG_CPU_SH2A
  36. # define TRAP_UBC 12
  37. # define TRAP_FPU_ERROR 13
  38. # define TRAP_DIVZERO_ERROR 17
  39. # define TRAP_DIVOVF_ERROR 18
  40. # endif
  41. #else
  42. #define TRAP_RESERVED_INST 12
  43. #define TRAP_ILLEGAL_SLOT_INST 13
  44. #endif
  45. static inline void sign_extend(unsigned int count, unsigned char *dst)
  46. {
  47. #ifdef __LITTLE_ENDIAN__
  48. if ((count == 1) && dst[0] & 0x80) {
  49. dst[1] = 0xff;
  50. dst[2] = 0xff;
  51. dst[3] = 0xff;
  52. }
  53. if ((count == 2) && dst[1] & 0x80) {
  54. dst[2] = 0xff;
  55. dst[3] = 0xff;
  56. }
  57. #else
  58. if ((count == 1) && dst[3] & 0x80) {
  59. dst[2] = 0xff;
  60. dst[1] = 0xff;
  61. dst[0] = 0xff;
  62. }
  63. if ((count == 2) && dst[2] & 0x80) {
  64. dst[1] = 0xff;
  65. dst[0] = 0xff;
  66. }
  67. #endif
  68. }
  69. static struct mem_access user_mem_access = {
  70. copy_from_user,
  71. copy_to_user,
  72. };
  73. static unsigned long copy_from_kernel_wrapper(void *dst, const void __user *src,
  74. unsigned long cnt)
  75. {
  76. return copy_from_kernel_nofault(dst, (const void __force *)src, cnt);
  77. }
  78. static unsigned long copy_to_kernel_wrapper(void __user *dst, const void *src,
  79. unsigned long cnt)
  80. {
  81. return copy_to_kernel_nofault((void __force *)dst, src, cnt);
  82. }
  83. static struct mem_access kernel_mem_access = {
  84. copy_from_kernel_wrapper,
  85. copy_to_kernel_wrapper,
  86. };
  87. /*
  88. * handle an instruction that does an unaligned memory access by emulating the
  89. * desired behaviour
  90. * - note that PC _may not_ point to the faulting instruction
  91. * (if that instruction is in a branch delay slot)
  92. * - return 0 if emulation okay, -EFAULT on existential error
  93. */
  94. static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs,
  95. struct mem_access *ma)
  96. {
  97. int ret, index, count;
  98. unsigned long *rm, *rn;
  99. unsigned char *src, *dst;
  100. unsigned char __user *srcu, *dstu;
  101. index = (instruction>>8)&15; /* 0x0F00 */
  102. rn = &regs->regs[index];
  103. index = (instruction>>4)&15; /* 0x00F0 */
  104. rm = &regs->regs[index];
  105. count = 1<<(instruction&3);
  106. switch (count) {
  107. case 1: inc_unaligned_byte_access(); break;
  108. case 2: inc_unaligned_word_access(); break;
  109. case 4: inc_unaligned_dword_access(); break;
  110. case 8: inc_unaligned_multi_access(); break;
  111. }
  112. ret = -EFAULT;
  113. switch (instruction>>12) {
  114. case 0: /* mov.[bwl] to/from memory via r0+rn */
  115. if (instruction & 8) {
  116. /* from memory */
  117. srcu = (unsigned char __user *)*rm;
  118. srcu += regs->regs[0];
  119. dst = (unsigned char *)rn;
  120. *(unsigned long *)dst = 0;
  121. #if !defined(__LITTLE_ENDIAN__)
  122. dst += 4-count;
  123. #endif
  124. if (ma->from(dst, srcu, count))
  125. goto fetch_fault;
  126. sign_extend(count, dst);
  127. } else {
  128. /* to memory */
  129. src = (unsigned char *)rm;
  130. #if !defined(__LITTLE_ENDIAN__)
  131. src += 4-count;
  132. #endif
  133. dstu = (unsigned char __user *)*rn;
  134. dstu += regs->regs[0];
  135. if (ma->to(dstu, src, count))
  136. goto fetch_fault;
  137. }
  138. ret = 0;
  139. break;
  140. case 1: /* mov.l Rm,@(disp,Rn) */
  141. src = (unsigned char*) rm;
  142. dstu = (unsigned char __user *)*rn;
  143. dstu += (instruction&0x000F)<<2;
  144. if (ma->to(dstu, src, 4))
  145. goto fetch_fault;
  146. ret = 0;
  147. break;
  148. case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
  149. if (instruction & 4)
  150. *rn -= count;
  151. src = (unsigned char*) rm;
  152. dstu = (unsigned char __user *)*rn;
  153. #if !defined(__LITTLE_ENDIAN__)
  154. src += 4-count;
  155. #endif
  156. if (ma->to(dstu, src, count))
  157. goto fetch_fault;
  158. ret = 0;
  159. break;
  160. case 5: /* mov.l @(disp,Rm),Rn */
  161. srcu = (unsigned char __user *)*rm;
  162. srcu += (instruction & 0x000F) << 2;
  163. dst = (unsigned char *)rn;
  164. *(unsigned long *)dst = 0;
  165. if (ma->from(dst, srcu, 4))
  166. goto fetch_fault;
  167. ret = 0;
  168. break;
  169. case 6: /* mov.[bwl] from memory, possibly with post-increment */
  170. srcu = (unsigned char __user *)*rm;
  171. if (instruction & 4)
  172. *rm += count;
  173. dst = (unsigned char*) rn;
  174. *(unsigned long*)dst = 0;
  175. #if !defined(__LITTLE_ENDIAN__)
  176. dst += 4-count;
  177. #endif
  178. if (ma->from(dst, srcu, count))
  179. goto fetch_fault;
  180. sign_extend(count, dst);
  181. ret = 0;
  182. break;
  183. case 8:
  184. switch ((instruction&0xFF00)>>8) {
  185. case 0x81: /* mov.w R0,@(disp,Rn) */
  186. src = (unsigned char *) &regs->regs[0];
  187. #if !defined(__LITTLE_ENDIAN__)
  188. src += 2;
  189. #endif
  190. dstu = (unsigned char __user *)*rm; /* called Rn in the spec */
  191. dstu += (instruction & 0x000F) << 1;
  192. if (ma->to(dstu, src, 2))
  193. goto fetch_fault;
  194. ret = 0;
  195. break;
  196. case 0x85: /* mov.w @(disp,Rm),R0 */
  197. srcu = (unsigned char __user *)*rm;
  198. srcu += (instruction & 0x000F) << 1;
  199. dst = (unsigned char *) &regs->regs[0];
  200. *(unsigned long *)dst = 0;
  201. #if !defined(__LITTLE_ENDIAN__)
  202. dst += 2;
  203. #endif
  204. if (ma->from(dst, srcu, 2))
  205. goto fetch_fault;
  206. sign_extend(2, dst);
  207. ret = 0;
  208. break;
  209. }
  210. break;
  211. case 9: /* mov.w @(disp,PC),Rn */
  212. srcu = (unsigned char __user *)regs->pc;
  213. srcu += 4;
  214. srcu += (instruction & 0x00FF) << 1;
  215. dst = (unsigned char *)rn;
  216. *(unsigned long *)dst = 0;
  217. #if !defined(__LITTLE_ENDIAN__)
  218. dst += 2;
  219. #endif
  220. if (ma->from(dst, srcu, 2))
  221. goto fetch_fault;
  222. sign_extend(2, dst);
  223. ret = 0;
  224. break;
  225. case 0xd: /* mov.l @(disp,PC),Rn */
  226. srcu = (unsigned char __user *)(regs->pc & ~0x3);
  227. srcu += 4;
  228. srcu += (instruction & 0x00FF) << 2;
  229. dst = (unsigned char *)rn;
  230. *(unsigned long *)dst = 0;
  231. if (ma->from(dst, srcu, 4))
  232. goto fetch_fault;
  233. ret = 0;
  234. break;
  235. }
  236. return ret;
  237. fetch_fault:
  238. /* Argh. Address not only misaligned but also non-existent.
  239. * Raise an EFAULT and see if it's trapped
  240. */
  241. die_if_no_fixup("Fault in unaligned fixup", regs, 0);
  242. return -EFAULT;
  243. }
  244. /*
  245. * emulate the instruction in the delay slot
  246. * - fetches the instruction from PC+2
  247. */
  248. static inline int handle_delayslot(struct pt_regs *regs,
  249. insn_size_t old_instruction,
  250. struct mem_access *ma)
  251. {
  252. insn_size_t instruction;
  253. void __user *addr = (void __user *)(regs->pc +
  254. instruction_size(old_instruction));
  255. if (copy_from_user(&instruction, addr, sizeof(instruction))) {
  256. /* the instruction-fetch faulted */
  257. if (user_mode(regs))
  258. return -EFAULT;
  259. /* kernel */
  260. die("delay-slot-insn faulting in handle_unaligned_delayslot",
  261. regs, 0);
  262. }
  263. return handle_unaligned_ins(instruction, regs, ma);
  264. }
  265. /*
  266. * handle an instruction that does an unaligned memory access
  267. * - have to be careful of branch delay-slot instructions that fault
  268. * SH3:
  269. * - if the branch would be taken PC points to the branch
  270. * - if the branch would not be taken, PC points to delay-slot
  271. * SH4:
  272. * - PC always points to delayed branch
  273. * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
  274. */
  275. /* Macros to determine offset from current PC for branch instructions */
  276. /* Explicit type coercion is used to force sign extension where needed */
  277. #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
  278. #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
  279. int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
  280. struct mem_access *ma, int expected,
  281. unsigned long address)
  282. {
  283. u_int rm;
  284. int ret, index;
  285. /*
  286. * XXX: We can't handle mixed 16/32-bit instructions yet
  287. */
  288. if (instruction_size(instruction) != 2)
  289. return -EINVAL;
  290. index = (instruction>>8)&15; /* 0x0F00 */
  291. rm = regs->regs[index];
  292. /*
  293. * Log the unexpected fixups, and then pass them on to perf.
  294. *
  295. * We intentionally don't report the expected cases to perf as
  296. * otherwise the trapped I/O case will skew the results too much
  297. * to be useful.
  298. */
  299. if (!expected) {
  300. unaligned_fixups_notify(current, instruction, regs);
  301. perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1,
  302. regs, address);
  303. }
  304. ret = -EFAULT;
  305. switch (instruction&0xF000) {
  306. case 0x0000:
  307. if (instruction==0x000B) {
  308. /* rts */
  309. ret = handle_delayslot(regs, instruction, ma);
  310. if (ret==0)
  311. regs->pc = regs->pr;
  312. }
  313. else if ((instruction&0x00FF)==0x0023) {
  314. /* braf @Rm */
  315. ret = handle_delayslot(regs, instruction, ma);
  316. if (ret==0)
  317. regs->pc += rm + 4;
  318. }
  319. else if ((instruction&0x00FF)==0x0003) {
  320. /* bsrf @Rm */
  321. ret = handle_delayslot(regs, instruction, ma);
  322. if (ret==0) {
  323. regs->pr = regs->pc + 4;
  324. regs->pc += rm + 4;
  325. }
  326. }
  327. else {
  328. /* mov.[bwl] to/from memory via r0+rn */
  329. goto simple;
  330. }
  331. break;
  332. case 0x1000: /* mov.l Rm,@(disp,Rn) */
  333. goto simple;
  334. case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
  335. goto simple;
  336. case 0x4000:
  337. if ((instruction&0x00FF)==0x002B) {
  338. /* jmp @Rm */
  339. ret = handle_delayslot(regs, instruction, ma);
  340. if (ret==0)
  341. regs->pc = rm;
  342. }
  343. else if ((instruction&0x00FF)==0x000B) {
  344. /* jsr @Rm */
  345. ret = handle_delayslot(regs, instruction, ma);
  346. if (ret==0) {
  347. regs->pr = regs->pc + 4;
  348. regs->pc = rm;
  349. }
  350. }
  351. else {
  352. /* mov.[bwl] to/from memory via r0+rn */
  353. goto simple;
  354. }
  355. break;
  356. case 0x5000: /* mov.l @(disp,Rm),Rn */
  357. goto simple;
  358. case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
  359. goto simple;
  360. case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
  361. switch (instruction&0x0F00) {
  362. case 0x0100: /* mov.w R0,@(disp,Rm) */
  363. goto simple;
  364. case 0x0500: /* mov.w @(disp,Rm),R0 */
  365. goto simple;
  366. case 0x0B00: /* bf lab - no delayslot*/
  367. ret = 0;
  368. break;
  369. case 0x0F00: /* bf/s lab */
  370. ret = handle_delayslot(regs, instruction, ma);
  371. if (ret==0) {
  372. #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
  373. if ((regs->sr & 0x00000001) != 0)
  374. regs->pc += 4; /* next after slot */
  375. else
  376. #endif
  377. regs->pc += SH_PC_8BIT_OFFSET(instruction);
  378. }
  379. break;
  380. case 0x0900: /* bt lab - no delayslot */
  381. ret = 0;
  382. break;
  383. case 0x0D00: /* bt/s lab */
  384. ret = handle_delayslot(regs, instruction, ma);
  385. if (ret==0) {
  386. #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
  387. if ((regs->sr & 0x00000001) == 0)
  388. regs->pc += 4; /* next after slot */
  389. else
  390. #endif
  391. regs->pc += SH_PC_8BIT_OFFSET(instruction);
  392. }
  393. break;
  394. }
  395. break;
  396. case 0x9000: /* mov.w @(disp,Rm),Rn */
  397. goto simple;
  398. case 0xA000: /* bra label */
  399. ret = handle_delayslot(regs, instruction, ma);
  400. if (ret==0)
  401. regs->pc += SH_PC_12BIT_OFFSET(instruction);
  402. break;
  403. case 0xB000: /* bsr label */
  404. ret = handle_delayslot(regs, instruction, ma);
  405. if (ret==0) {
  406. regs->pr = regs->pc + 4;
  407. regs->pc += SH_PC_12BIT_OFFSET(instruction);
  408. }
  409. break;
  410. case 0xD000: /* mov.l @(disp,Rm),Rn */
  411. goto simple;
  412. }
  413. return ret;
  414. /* handle non-delay-slot instruction */
  415. simple:
  416. ret = handle_unaligned_ins(instruction, regs, ma);
  417. if (ret==0)
  418. regs->pc += instruction_size(instruction);
  419. return ret;
  420. }
  421. /*
  422. * Handle various address error exceptions:
  423. * - instruction address error:
  424. * misaligned PC
  425. * PC >= 0x80000000 in user mode
  426. * - data address error (read and write)
  427. * misaligned data access
  428. * access to >= 0x80000000 is user mode
  429. * Unfortuntaly we can't distinguish between instruction address error
  430. * and data address errors caused by read accesses.
  431. */
  432. asmlinkage void do_address_error(struct pt_regs *regs,
  433. unsigned long writeaccess,
  434. unsigned long address)
  435. {
  436. unsigned long error_code = 0;
  437. insn_size_t instruction;
  438. int tmp;
  439. /* Intentional ifdef */
  440. #ifdef CONFIG_CPU_HAS_SR_RB
  441. error_code = lookup_exception_vector();
  442. #endif
  443. if (user_mode(regs)) {
  444. int si_code = BUS_ADRERR;
  445. unsigned int user_action;
  446. local_irq_enable();
  447. inc_unaligned_user_access();
  448. if (copy_from_user(&instruction, (insn_size_t __user *)(regs->pc & ~1),
  449. sizeof(instruction))) {
  450. goto uspace_segv;
  451. }
  452. /* shout about userspace fixups */
  453. unaligned_fixups_notify(current, instruction, regs);
  454. user_action = unaligned_user_action();
  455. if (user_action & UM_FIXUP)
  456. goto fixup;
  457. if (user_action & UM_SIGNAL)
  458. goto uspace_segv;
  459. else {
  460. /* ignore */
  461. regs->pc += instruction_size(instruction);
  462. return;
  463. }
  464. fixup:
  465. /* bad PC is not something we can fix */
  466. if (regs->pc & 1) {
  467. si_code = BUS_ADRALN;
  468. goto uspace_segv;
  469. }
  470. tmp = handle_unaligned_access(instruction, regs,
  471. &user_mem_access, 0,
  472. address);
  473. if (tmp == 0)
  474. return; /* sorted */
  475. uspace_segv:
  476. printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
  477. "access (PC %lx PR %lx)\n", current->comm, regs->pc,
  478. regs->pr);
  479. force_sig_fault(SIGBUS, si_code, (void __user *)address);
  480. } else {
  481. inc_unaligned_kernel_access();
  482. if (regs->pc & 1)
  483. die("unaligned program counter", regs, error_code);
  484. if (copy_from_kernel_nofault(&instruction, (void *)(regs->pc),
  485. sizeof(instruction))) {
  486. /* Argh. Fault on the instruction itself.
  487. This should never happen non-SMP
  488. */
  489. die("insn faulting in do_address_error", regs, 0);
  490. }
  491. unaligned_fixups_notify(current, instruction, regs);
  492. handle_unaligned_access(instruction, regs, &kernel_mem_access,
  493. 0, address);
  494. }
  495. }
  496. #ifdef CONFIG_SH_DSP
  497. /*
  498. * SH-DSP support [email protected].
  499. */
  500. int is_dsp_inst(struct pt_regs *regs)
  501. {
  502. unsigned short inst = 0;
  503. /*
  504. * Safe guard if DSP mode is already enabled or we're lacking
  505. * the DSP altogether.
  506. */
  507. if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
  508. return 0;
  509. get_user(inst, ((unsigned short *) regs->pc));
  510. inst &= 0xf000;
  511. /* Check for any type of DSP or support instruction */
  512. if ((inst == 0xf000) || (inst == 0x4000))
  513. return 1;
  514. return 0;
  515. }
  516. #else
  517. #define is_dsp_inst(regs) (0)
  518. #endif /* CONFIG_SH_DSP */
  519. #ifdef CONFIG_CPU_SH2A
  520. asmlinkage void do_divide_error(unsigned long r4)
  521. {
  522. int code;
  523. switch (r4) {
  524. case TRAP_DIVZERO_ERROR:
  525. code = FPE_INTDIV;
  526. break;
  527. case TRAP_DIVOVF_ERROR:
  528. code = FPE_INTOVF;
  529. break;
  530. default:
  531. /* Let gcc know unhandled cases don't make it past here */
  532. return;
  533. }
  534. force_sig_fault(SIGFPE, code, NULL);
  535. }
  536. #endif
  537. asmlinkage void do_reserved_inst(void)
  538. {
  539. struct pt_regs *regs = current_pt_regs();
  540. unsigned long error_code;
  541. #ifdef CONFIG_SH_FPU_EMU
  542. unsigned short inst = 0;
  543. int err;
  544. get_user(inst, (unsigned short __user *)regs->pc);
  545. err = do_fpu_inst(inst, regs);
  546. if (!err) {
  547. regs->pc += instruction_size(inst);
  548. return;
  549. }
  550. /* not a FPU inst. */
  551. #endif
  552. #ifdef CONFIG_SH_DSP
  553. /* Check if it's a DSP instruction */
  554. if (is_dsp_inst(regs)) {
  555. /* Enable DSP mode, and restart instruction. */
  556. regs->sr |= SR_DSP;
  557. /* Save DSP mode */
  558. current->thread.dsp_status.status |= SR_DSP;
  559. return;
  560. }
  561. #endif
  562. error_code = lookup_exception_vector();
  563. local_irq_enable();
  564. force_sig(SIGILL);
  565. die_if_no_fixup("reserved instruction", regs, error_code);
  566. }
  567. #ifdef CONFIG_SH_FPU_EMU
  568. static int emulate_branch(unsigned short inst, struct pt_regs *regs)
  569. {
  570. /*
  571. * bfs: 8fxx: PC+=d*2+4;
  572. * bts: 8dxx: PC+=d*2+4;
  573. * bra: axxx: PC+=D*2+4;
  574. * bsr: bxxx: PC+=D*2+4 after PR=PC+4;
  575. * braf:0x23: PC+=Rn*2+4;
  576. * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
  577. * jmp: 4x2b: PC=Rn;
  578. * jsr: 4x0b: PC=Rn after PR=PC+4;
  579. * rts: 000b: PC=PR;
  580. */
  581. if (((inst & 0xf000) == 0xb000) || /* bsr */
  582. ((inst & 0xf0ff) == 0x0003) || /* bsrf */
  583. ((inst & 0xf0ff) == 0x400b)) /* jsr */
  584. regs->pr = regs->pc + 4;
  585. if ((inst & 0xfd00) == 0x8d00) { /* bfs, bts */
  586. regs->pc += SH_PC_8BIT_OFFSET(inst);
  587. return 0;
  588. }
  589. if ((inst & 0xe000) == 0xa000) { /* bra, bsr */
  590. regs->pc += SH_PC_12BIT_OFFSET(inst);
  591. return 0;
  592. }
  593. if ((inst & 0xf0df) == 0x0003) { /* braf, bsrf */
  594. regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
  595. return 0;
  596. }
  597. if ((inst & 0xf0df) == 0x400b) { /* jmp, jsr */
  598. regs->pc = regs->regs[(inst & 0x0f00) >> 8];
  599. return 0;
  600. }
  601. if ((inst & 0xffff) == 0x000b) { /* rts */
  602. regs->pc = regs->pr;
  603. return 0;
  604. }
  605. return 1;
  606. }
  607. #endif
  608. asmlinkage void do_illegal_slot_inst(void)
  609. {
  610. struct pt_regs *regs = current_pt_regs();
  611. unsigned long inst;
  612. if (kprobe_handle_illslot(regs->pc) == 0)
  613. return;
  614. #ifdef CONFIG_SH_FPU_EMU
  615. get_user(inst, (unsigned short __user *)regs->pc + 1);
  616. if (!do_fpu_inst(inst, regs)) {
  617. get_user(inst, (unsigned short __user *)regs->pc);
  618. if (!emulate_branch(inst, regs))
  619. return;
  620. /* fault in branch.*/
  621. }
  622. /* not a FPU inst. */
  623. #endif
  624. inst = lookup_exception_vector();
  625. local_irq_enable();
  626. force_sig(SIGILL);
  627. die_if_no_fixup("illegal slot instruction", regs, inst);
  628. }
  629. asmlinkage void do_exception_error(void)
  630. {
  631. long ex;
  632. ex = lookup_exception_vector();
  633. die_if_kernel("exception", current_pt_regs(), ex);
  634. }
  635. void per_cpu_trap_init(void)
  636. {
  637. extern void *vbr_base;
  638. /* NOTE: The VBR value should be at P1
  639. (or P2, virtural "fixed" address space).
  640. It's definitely should not in physical address. */
  641. asm volatile("ldc %0, vbr"
  642. : /* no output */
  643. : "r" (&vbr_base)
  644. : "memory");
  645. /* disable exception blocking now when the vbr has been setup */
  646. clear_bl_bit();
  647. }
  648. void *set_exception_table_vec(unsigned int vec, void *handler)
  649. {
  650. extern void *exception_handling_table[];
  651. void *old_handler;
  652. old_handler = exception_handling_table[vec];
  653. exception_handling_table[vec] = handler;
  654. return old_handler;
  655. }
  656. void __init trap_init(void)
  657. {
  658. set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
  659. set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
  660. #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
  661. defined(CONFIG_SH_FPU_EMU)
  662. /*
  663. * For SH-4 lacking an FPU, treat floating point instructions as
  664. * reserved. They'll be handled in the math-emu case, or faulted on
  665. * otherwise.
  666. */
  667. set_exception_table_evt(0x800, do_reserved_inst);
  668. set_exception_table_evt(0x820, do_illegal_slot_inst);
  669. #elif defined(CONFIG_SH_FPU)
  670. set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
  671. set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
  672. #endif
  673. #ifdef CONFIG_CPU_SH2
  674. set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
  675. #endif
  676. #ifdef CONFIG_CPU_SH2A
  677. set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
  678. set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
  679. #ifdef CONFIG_SH_FPU
  680. set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler);
  681. #endif
  682. #endif
  683. #ifdef TRAP_UBC
  684. set_exception_table_vec(TRAP_UBC, breakpoint_trap_handler);
  685. #endif
  686. }