perf_event.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Performance event support framework for SuperH hardware counters.
  4. *
  5. * Copyright (C) 2009 Paul Mundt
  6. *
  7. * Heavily based on the x86 and PowerPC implementations.
  8. *
  9. * x86:
  10. * Copyright (C) 2008 Thomas Gleixner <[email protected]>
  11. * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
  12. * Copyright (C) 2009 Jaswinder Singh Rajput
  13. * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
  14. * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
  15. * Copyright (C) 2009 Intel Corporation, <[email protected]>
  16. *
  17. * ppc:
  18. * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
  19. */
  20. #include <linux/kernel.h>
  21. #include <linux/init.h>
  22. #include <linux/io.h>
  23. #include <linux/irq.h>
  24. #include <linux/perf_event.h>
  25. #include <linux/export.h>
  26. #include <asm/processor.h>
  27. struct cpu_hw_events {
  28. struct perf_event *events[MAX_HWEVENTS];
  29. unsigned long used_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
  30. unsigned long active_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
  31. };
  32. DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
  33. static struct sh_pmu *sh_pmu __read_mostly;
  34. /* Number of perf_events counting hardware events */
  35. static atomic_t num_events;
  36. /* Used to avoid races in calling reserve/release_pmc_hardware */
  37. static DEFINE_MUTEX(pmc_reserve_mutex);
  38. /*
  39. * Stub these out for now, do something more profound later.
  40. */
  41. int reserve_pmc_hardware(void)
  42. {
  43. return 0;
  44. }
  45. void release_pmc_hardware(void)
  46. {
  47. }
  48. static inline int sh_pmu_initialized(void)
  49. {
  50. return !!sh_pmu;
  51. }
  52. /*
  53. * Release the PMU if this is the last perf_event.
  54. */
  55. static void hw_perf_event_destroy(struct perf_event *event)
  56. {
  57. if (!atomic_add_unless(&num_events, -1, 1)) {
  58. mutex_lock(&pmc_reserve_mutex);
  59. if (atomic_dec_return(&num_events) == 0)
  60. release_pmc_hardware();
  61. mutex_unlock(&pmc_reserve_mutex);
  62. }
  63. }
  64. static int hw_perf_cache_event(int config, int *evp)
  65. {
  66. unsigned long type, op, result;
  67. int ev;
  68. if (!sh_pmu->cache_events)
  69. return -EINVAL;
  70. /* unpack config */
  71. type = config & 0xff;
  72. op = (config >> 8) & 0xff;
  73. result = (config >> 16) & 0xff;
  74. if (type >= PERF_COUNT_HW_CACHE_MAX ||
  75. op >= PERF_COUNT_HW_CACHE_OP_MAX ||
  76. result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
  77. return -EINVAL;
  78. ev = (*sh_pmu->cache_events)[type][op][result];
  79. if (ev == 0)
  80. return -EOPNOTSUPP;
  81. if (ev == -1)
  82. return -EINVAL;
  83. *evp = ev;
  84. return 0;
  85. }
  86. static int __hw_perf_event_init(struct perf_event *event)
  87. {
  88. struct perf_event_attr *attr = &event->attr;
  89. struct hw_perf_event *hwc = &event->hw;
  90. int config = -1;
  91. int err;
  92. if (!sh_pmu_initialized())
  93. return -ENODEV;
  94. /*
  95. * See if we need to reserve the counter.
  96. *
  97. * If no events are currently in use, then we have to take a
  98. * mutex to ensure that we don't race with another task doing
  99. * reserve_pmc_hardware or release_pmc_hardware.
  100. */
  101. err = 0;
  102. if (!atomic_inc_not_zero(&num_events)) {
  103. mutex_lock(&pmc_reserve_mutex);
  104. if (atomic_read(&num_events) == 0 &&
  105. reserve_pmc_hardware())
  106. err = -EBUSY;
  107. else
  108. atomic_inc(&num_events);
  109. mutex_unlock(&pmc_reserve_mutex);
  110. }
  111. if (err)
  112. return err;
  113. event->destroy = hw_perf_event_destroy;
  114. switch (attr->type) {
  115. case PERF_TYPE_RAW:
  116. config = attr->config & sh_pmu->raw_event_mask;
  117. break;
  118. case PERF_TYPE_HW_CACHE:
  119. err = hw_perf_cache_event(attr->config, &config);
  120. if (err)
  121. return err;
  122. break;
  123. case PERF_TYPE_HARDWARE:
  124. if (attr->config >= sh_pmu->max_events)
  125. return -EINVAL;
  126. config = sh_pmu->event_map(attr->config);
  127. break;
  128. }
  129. if (config == -1)
  130. return -EINVAL;
  131. hwc->config |= config;
  132. return 0;
  133. }
  134. static void sh_perf_event_update(struct perf_event *event,
  135. struct hw_perf_event *hwc, int idx)
  136. {
  137. u64 prev_raw_count, new_raw_count;
  138. s64 delta;
  139. int shift = 0;
  140. /*
  141. * Depending on the counter configuration, they may or may not
  142. * be chained, in which case the previous counter value can be
  143. * updated underneath us if the lower-half overflows.
  144. *
  145. * Our tactic to handle this is to first atomically read and
  146. * exchange a new raw count - then add that new-prev delta
  147. * count to the generic counter atomically.
  148. *
  149. * As there is no interrupt associated with the overflow events,
  150. * this is the simplest approach for maintaining consistency.
  151. */
  152. again:
  153. prev_raw_count = local64_read(&hwc->prev_count);
  154. new_raw_count = sh_pmu->read(idx);
  155. if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
  156. new_raw_count) != prev_raw_count)
  157. goto again;
  158. /*
  159. * Now we have the new raw value and have updated the prev
  160. * timestamp already. We can now calculate the elapsed delta
  161. * (counter-)time and add that to the generic counter.
  162. *
  163. * Careful, not all hw sign-extends above the physical width
  164. * of the count.
  165. */
  166. delta = (new_raw_count << shift) - (prev_raw_count << shift);
  167. delta >>= shift;
  168. local64_add(delta, &event->count);
  169. }
  170. static void sh_pmu_stop(struct perf_event *event, int flags)
  171. {
  172. struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
  173. struct hw_perf_event *hwc = &event->hw;
  174. int idx = hwc->idx;
  175. if (!(event->hw.state & PERF_HES_STOPPED)) {
  176. sh_pmu->disable(hwc, idx);
  177. cpuc->events[idx] = NULL;
  178. event->hw.state |= PERF_HES_STOPPED;
  179. }
  180. if ((flags & PERF_EF_UPDATE) && !(event->hw.state & PERF_HES_UPTODATE)) {
  181. sh_perf_event_update(event, &event->hw, idx);
  182. event->hw.state |= PERF_HES_UPTODATE;
  183. }
  184. }
  185. static void sh_pmu_start(struct perf_event *event, int flags)
  186. {
  187. struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
  188. struct hw_perf_event *hwc = &event->hw;
  189. int idx = hwc->idx;
  190. if (WARN_ON_ONCE(idx == -1))
  191. return;
  192. if (flags & PERF_EF_RELOAD)
  193. WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
  194. cpuc->events[idx] = event;
  195. event->hw.state = 0;
  196. sh_pmu->enable(hwc, idx);
  197. }
  198. static void sh_pmu_del(struct perf_event *event, int flags)
  199. {
  200. struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
  201. sh_pmu_stop(event, PERF_EF_UPDATE);
  202. __clear_bit(event->hw.idx, cpuc->used_mask);
  203. perf_event_update_userpage(event);
  204. }
  205. static int sh_pmu_add(struct perf_event *event, int flags)
  206. {
  207. struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
  208. struct hw_perf_event *hwc = &event->hw;
  209. int idx = hwc->idx;
  210. int ret = -EAGAIN;
  211. perf_pmu_disable(event->pmu);
  212. if (__test_and_set_bit(idx, cpuc->used_mask)) {
  213. idx = find_first_zero_bit(cpuc->used_mask, sh_pmu->num_events);
  214. if (idx == sh_pmu->num_events)
  215. goto out;
  216. __set_bit(idx, cpuc->used_mask);
  217. hwc->idx = idx;
  218. }
  219. sh_pmu->disable(hwc, idx);
  220. event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
  221. if (flags & PERF_EF_START)
  222. sh_pmu_start(event, PERF_EF_RELOAD);
  223. perf_event_update_userpage(event);
  224. ret = 0;
  225. out:
  226. perf_pmu_enable(event->pmu);
  227. return ret;
  228. }
  229. static void sh_pmu_read(struct perf_event *event)
  230. {
  231. sh_perf_event_update(event, &event->hw, event->hw.idx);
  232. }
  233. static int sh_pmu_event_init(struct perf_event *event)
  234. {
  235. int err;
  236. /* does not support taken branch sampling */
  237. if (has_branch_stack(event))
  238. return -EOPNOTSUPP;
  239. switch (event->attr.type) {
  240. case PERF_TYPE_RAW:
  241. case PERF_TYPE_HW_CACHE:
  242. case PERF_TYPE_HARDWARE:
  243. err = __hw_perf_event_init(event);
  244. break;
  245. default:
  246. return -ENOENT;
  247. }
  248. if (unlikely(err)) {
  249. if (event->destroy)
  250. event->destroy(event);
  251. }
  252. return err;
  253. }
  254. static void sh_pmu_enable(struct pmu *pmu)
  255. {
  256. if (!sh_pmu_initialized())
  257. return;
  258. sh_pmu->enable_all();
  259. }
  260. static void sh_pmu_disable(struct pmu *pmu)
  261. {
  262. if (!sh_pmu_initialized())
  263. return;
  264. sh_pmu->disable_all();
  265. }
  266. static struct pmu pmu = {
  267. .pmu_enable = sh_pmu_enable,
  268. .pmu_disable = sh_pmu_disable,
  269. .event_init = sh_pmu_event_init,
  270. .add = sh_pmu_add,
  271. .del = sh_pmu_del,
  272. .start = sh_pmu_start,
  273. .stop = sh_pmu_stop,
  274. .read = sh_pmu_read,
  275. };
  276. static int sh_pmu_prepare_cpu(unsigned int cpu)
  277. {
  278. struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
  279. memset(cpuhw, 0, sizeof(struct cpu_hw_events));
  280. return 0;
  281. }
  282. int register_sh_pmu(struct sh_pmu *_pmu)
  283. {
  284. if (sh_pmu)
  285. return -EBUSY;
  286. sh_pmu = _pmu;
  287. pr_info("Performance Events: %s support registered\n", _pmu->name);
  288. /*
  289. * All of the on-chip counters are "limited", in that they have
  290. * no interrupts, and are therefore unable to do sampling without
  291. * further work and timer assistance.
  292. */
  293. pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
  294. WARN_ON(_pmu->num_events > MAX_HWEVENTS);
  295. perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
  296. cpuhp_setup_state(CPUHP_PERF_SUPERH, "PERF_SUPERH", sh_pmu_prepare_cpu,
  297. NULL);
  298. return 0;
  299. }