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cpu-sh4
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cpu
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freq.h

freq.h 1.9 KB
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  1. /* SPDX-License-Identifier: GPL-2.0
    2. 

  2.  *
    3. 

  3.  * include/asm-sh/cpu-sh4/freq.h
    4. 

  4.  *
    5. 

  5.  * Copyright (C) 2002, 2003 Paul Mundt
    6. 

  6.  */
    7. 

  7. #ifndef __ASM_CPU_SH4_FREQ_H
    8. 

  8. #define __ASM_CPU_SH4_FREQ_H
    9. 

  9. 

  10. #if defined(CONFIG_CPU_SUBTYPE_SH7722) || \
    11. 

  11.     defined(CONFIG_CPU_SUBTYPE_SH7723) || \
    12. 

  12.     defined(CONFIG_CPU_SUBTYPE_SH7343) || \
    13. 

  13.     defined(CONFIG_CPU_SUBTYPE_SH7366)
    14. 

  14. #define FRQCR		        0xa4150000
    15. 

  15. #define VCLKCR			0xa4150004
    16. 

  16. #define SCLKACR			0xa4150008
    17. 

  17. #define SCLKBCR			0xa415000c
    18. 

  18. #define IrDACLKCR		0xa4150010
    19. 

  19. #define MSTPCR0			0xa4150030
    20. 

  20. #define MSTPCR1			0xa4150034
    21. 

  21. #define MSTPCR2			0xa4150038
    22. 

  22. #elif defined(CONFIG_CPU_SUBTYPE_SH7757)
    23. 

  23. #define	FRQCR			0xffc80000
    24. 

  24. #define	OSCCR			0xffc80018
    25. 

  25. #define	PLLCR			0xffc80024
    26. 

  26. #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
    27. 

  27.       defined(CONFIG_CPU_SUBTYPE_SH7780)
    28. 

  28. #define	FRQCR			0xffc80000
    29. 

  29. #elif defined(CONFIG_CPU_SUBTYPE_SH7724)
    30. 

  30. #define FRQCRA			0xa4150000
    31. 

  31. #define FRQCRB			0xa4150004
    32. 

  32. #define VCLKCR			0xa4150048
    33. 

  33. 

  34. #define FCLKACR			0xa4150008
    35. 

  35. #define FCLKBCR			0xa415000c
    36. 

  36. #define FRQCR			FRQCRA
    37. 

  37. #define SCLKACR			FCLKACR
    38. 

  38. #define SCLKBCR			FCLKBCR
    39. 

  39. #define FCLKACR			0xa4150008
    40. 

  40. #define FCLKBCR			0xa415000c
    41. 

  41. #define IrDACLKCR		0xa4150018
    42. 

  42. 

  43. #define MSTPCR0			0xa4150030
    44. 

  44. #define MSTPCR1			0xa4150034
    45. 

  45. #define MSTPCR2			0xa4150038
    46. 

  46. 

  47. #elif defined(CONFIG_CPU_SUBTYPE_SH7734)
    48. 

  48. #define FRQCR0			0xffc80000
    49. 

  49. #define FRQCR2			0xffc80008
    50. 

  50. #define FRQMR1			0xffc80014
    51. 

  51. #define FRQMR2			0xffc80018
    52. 

  52. #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
    53. 

  53. #define FRQCR0			0xffc80000
    54. 

  54. #define FRQCR1			0xffc80004
    55. 

  55. #define FRQMR1			0xffc80014
    56. 

  56. #elif defined(CONFIG_CPU_SUBTYPE_SH7786)
    57. 

  57. #define FRQCR0			0xffc40000
    58. 

  58. #define FRQCR1			0xffc40004
    59. 

  59. #define FRQMR1			0xffc40014
    60. 

  60. #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
    61. 

  61. #define FRQCR0			0xffc00000
    62. 

  62. #define FRQCR1			0xffc00004
    63. 

  63. #define FRQMR1			0xffc00014
    64. 

  64. #else
    65. 

  65. #define FRQCR			0xffc00000
    66. 

  66. #define FRQCR_PSTBY		0x0200
    67. 

  67. #define FRQCR_PLLEN		0x0400
    68. 

  68. #define FRQCR_CKOEN		0x0800
    69. 

  69. #endif
    70. 

  70. #define MIN_DIVISOR_NR		0
    71. 

  71. #define MAX_DIVISOR_NR		3
    72. 

  72. 

  73. #endif /* __ASM_CPU_SH4_FREQ_H */
    74. 

  74.