cache.h 1.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0
  2. *
  3. * include/asm-sh/cpu-sh4/cache.h
  4. *
  5. * Copyright (C) 1999 Niibe Yutaka
  6. */
  7. #ifndef __ASM_CPU_SH4_CACHE_H
  8. #define __ASM_CPU_SH4_CACHE_H
  9. #define L1_CACHE_SHIFT 5
  10. #define SH_CACHE_VALID 1
  11. #define SH_CACHE_UPDATED 2
  12. #define SH_CACHE_COMBINED 4
  13. #define SH_CACHE_ASSOC 8
  14. #define SH_CCR 0xff00001c /* Address of Cache Control Register */
  15. #define CCR_CACHE_OCE 0x0001 /* Operand Cache Enable */
  16. #define CCR_CACHE_WT 0x0002 /* Write-Through (for P0,U0,P3) (else writeback)*/
  17. #define CCR_CACHE_CB 0x0004 /* Copy-Back (for P1) (else writethrough) */
  18. #define CCR_CACHE_OCI 0x0008 /* OC Invalidate */
  19. #define CCR_CACHE_ORA 0x0020 /* OC RAM Mode */
  20. #define CCR_CACHE_OIX 0x0080 /* OC Index Enable */
  21. #define CCR_CACHE_ICE 0x0100 /* Instruction Cache Enable */
  22. #define CCR_CACHE_ICI 0x0800 /* IC Invalidate */
  23. #define CCR_CACHE_IIX 0x8000 /* IC Index Enable */
  24. #ifndef CONFIG_CPU_SH4A
  25. #define CCR_CACHE_EMODE 0x80000000 /* EMODE Enable */
  26. #endif
  27. /* Default CCR setup: 8k+16k-byte cache,P1-wb,enable */
  28. #define CCR_CACHE_ENABLE (CCR_CACHE_OCE|CCR_CACHE_ICE)
  29. #define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI|CCR_CACHE_ICI)
  30. #define CACHE_IC_ADDRESS_ARRAY 0xf0000000
  31. #define CACHE_OC_ADDRESS_ARRAY 0xf4000000
  32. #define RAMCR 0xFF000074
  33. #endif /* __ASM_CPU_SH4_CACHE_H */