cache.h 1.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0
  2. *
  3. * include/asm-sh/cpu-sh3/cache.h
  4. *
  5. * Copyright (C) 1999 Niibe Yutaka
  6. */
  7. #ifndef __ASM_CPU_SH3_CACHE_H
  8. #define __ASM_CPU_SH3_CACHE_H
  9. #define L1_CACHE_SHIFT 4
  10. #define SH_CACHE_VALID 1
  11. #define SH_CACHE_UPDATED 2
  12. #define SH_CACHE_COMBINED 4
  13. #define SH_CACHE_ASSOC 8
  14. #define SH_CCR 0xffffffec /* Address of Cache Control Register */
  15. #define CCR_CACHE_CE 0x01 /* Cache Enable */
  16. #define CCR_CACHE_WT 0x02 /* Write-Through (for P0,U0,P3) (else writeback) */
  17. #define CCR_CACHE_CB 0x04 /* Write-Back (for P1) (else writethrough) */
  18. #define CCR_CACHE_CF 0x08 /* Cache Flush */
  19. #define CCR_CACHE_ORA 0x20 /* RAM mode */
  20. #define CACHE_OC_ADDRESS_ARRAY 0xf0000000
  21. #define CACHE_PHYSADDR_MASK 0x1ffffc00
  22. #define CCR_CACHE_ENABLE CCR_CACHE_CE
  23. #define CCR_CACHE_INVALIDATE CCR_CACHE_CF
  24. #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
  25. defined(CONFIG_CPU_SUBTYPE_SH7710) || \
  26. defined(CONFIG_CPU_SUBTYPE_SH7720) || \
  27. defined(CONFIG_CPU_SUBTYPE_SH7721)
  28. #define CCR3_REG 0xa40000b4
  29. #define CCR_CACHE_16KB 0x00010000
  30. #define CCR_CACHE_32KB 0x00020000
  31. #endif
  32. #endif /* __ASM_CPU_SH3_CACHE_H */