mmcif-sh7724.c 2.0 KB

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  1. /*
  2. * sh7724 MMCIF loader
  3. *
  4. * Copyright (C) 2010 Magnus Damm
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #include <linux/platform_data/sh_mmcif.h>
  11. #include <mach/romimage.h>
  12. #define MMCIF_BASE (void __iomem *)0xa4ca0000
  13. #define MSTPCR2 0xa4150038
  14. #define PTWCR 0xa4050146
  15. #define PTXCR 0xa4050148
  16. #define PSELA 0xa405014e
  17. #define PSELE 0xa4050156
  18. #define HIZCRC 0xa405015c
  19. #define DRVCRA 0xa405018a
  20. enum {
  21. MMCIF_PROGRESS_ENTER,
  22. MMCIF_PROGRESS_INIT,
  23. MMCIF_PROGRESS_LOAD,
  24. MMCIF_PROGRESS_DONE
  25. };
  26. /* SH7724 specific MMCIF loader
  27. *
  28. * loads the romImage from an MMC card starting from block 512
  29. * use the following line to write the romImage to an MMC card
  30. * # dd if=arch/sh/boot/romImage of=/dev/sdx bs=512 seek=512
  31. */
  32. asmlinkage void mmcif_loader(unsigned char *buf, unsigned long no_bytes)
  33. {
  34. mmcif_update_progress(MMCIF_PROGRESS_ENTER);
  35. /* enable clock to the MMCIF hardware block */
  36. __raw_writel(__raw_readl(MSTPCR2) & ~0x20000000, MSTPCR2);
  37. /* setup pins D7-D0 */
  38. __raw_writew(0x0000, PTWCR);
  39. /* setup pins MMC_CLK, MMC_CMD */
  40. __raw_writew(__raw_readw(PTXCR) & ~0x000f, PTXCR);
  41. /* select D3-D0 pin function */
  42. __raw_writew(__raw_readw(PSELA) & ~0x2000, PSELA);
  43. /* select D7-D4 pin function */
  44. __raw_writew(__raw_readw(PSELE) & ~0x3000, PSELE);
  45. /* disable Hi-Z for the MMC pins */
  46. __raw_writew(__raw_readw(HIZCRC) & ~0x0620, HIZCRC);
  47. /* high drive capability for MMC pins */
  48. __raw_writew(__raw_readw(DRVCRA) | 0x3000, DRVCRA);
  49. mmcif_update_progress(MMCIF_PROGRESS_INIT);
  50. /* setup MMCIF hardware */
  51. sh_mmcif_boot_init(MMCIF_BASE);
  52. mmcif_update_progress(MMCIF_PROGRESS_LOAD);
  53. /* load kernel via MMCIF interface */
  54. sh_mmcif_boot_do_read(MMCIF_BASE, 512,
  55. (no_bytes + SH_MMCIF_BBS - 1) / SH_MMCIF_BBS,
  56. buf);
  57. /* disable clock to the MMCIF hardware block */
  58. __raw_writel(__raw_readl(MSTPCR2) | 0x20000000, MSTPCR2);
  59. mmcif_update_progress(MMCIF_PROGRESS_DONE);
  60. }