uprobes.c 9.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * User-space Probes (UProbes) for s390
  4. *
  5. * Copyright IBM Corp. 2014
  6. * Author(s): Jan Willeke,
  7. */
  8. #include <linux/uaccess.h>
  9. #include <linux/uprobes.h>
  10. #include <linux/compat.h>
  11. #include <linux/kdebug.h>
  12. #include <linux/sched/task_stack.h>
  13. #include <asm/switch_to.h>
  14. #include <asm/facility.h>
  15. #include <asm/kprobes.h>
  16. #include <asm/dis.h>
  17. #include "entry.h"
  18. #define UPROBE_TRAP_NR UINT_MAX
  19. int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm,
  20. unsigned long addr)
  21. {
  22. return probe_is_prohibited_opcode(auprobe->insn);
  23. }
  24. int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
  25. {
  26. if (psw_bits(regs->psw).eaba == PSW_BITS_AMODE_24BIT)
  27. return -EINVAL;
  28. if (!is_compat_task() && psw_bits(regs->psw).eaba == PSW_BITS_AMODE_31BIT)
  29. return -EINVAL;
  30. clear_thread_flag(TIF_PER_TRAP);
  31. auprobe->saved_per = psw_bits(regs->psw).per;
  32. auprobe->saved_int_code = regs->int_code;
  33. regs->int_code = UPROBE_TRAP_NR;
  34. regs->psw.addr = current->utask->xol_vaddr;
  35. set_tsk_thread_flag(current, TIF_UPROBE_SINGLESTEP);
  36. update_cr_regs(current);
  37. return 0;
  38. }
  39. bool arch_uprobe_xol_was_trapped(struct task_struct *tsk)
  40. {
  41. struct pt_regs *regs = task_pt_regs(tsk);
  42. if (regs->int_code != UPROBE_TRAP_NR)
  43. return true;
  44. return false;
  45. }
  46. static int check_per_event(unsigned short cause, unsigned long control,
  47. struct pt_regs *regs)
  48. {
  49. if (!(regs->psw.mask & PSW_MASK_PER))
  50. return 0;
  51. /* user space single step */
  52. if (control == 0)
  53. return 1;
  54. /* over indication for storage alteration */
  55. if ((control & 0x20200000) && (cause & 0x2000))
  56. return 1;
  57. if (cause & 0x8000) {
  58. /* all branches */
  59. if ((control & 0x80800000) == 0x80000000)
  60. return 1;
  61. /* branch into selected range */
  62. if (((control & 0x80800000) == 0x80800000) &&
  63. regs->psw.addr >= current->thread.per_user.start &&
  64. regs->psw.addr <= current->thread.per_user.end)
  65. return 1;
  66. }
  67. return 0;
  68. }
  69. int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
  70. {
  71. int fixup = probe_get_fixup_type(auprobe->insn);
  72. struct uprobe_task *utask = current->utask;
  73. clear_tsk_thread_flag(current, TIF_UPROBE_SINGLESTEP);
  74. update_cr_regs(current);
  75. psw_bits(regs->psw).per = auprobe->saved_per;
  76. regs->int_code = auprobe->saved_int_code;
  77. if (fixup & FIXUP_PSW_NORMAL)
  78. regs->psw.addr += utask->vaddr - utask->xol_vaddr;
  79. if (fixup & FIXUP_RETURN_REGISTER) {
  80. int reg = (auprobe->insn[0] & 0xf0) >> 4;
  81. regs->gprs[reg] += utask->vaddr - utask->xol_vaddr;
  82. }
  83. if (fixup & FIXUP_BRANCH_NOT_TAKEN) {
  84. int ilen = insn_length(auprobe->insn[0] >> 8);
  85. if (regs->psw.addr - utask->xol_vaddr == ilen)
  86. regs->psw.addr = utask->vaddr + ilen;
  87. }
  88. if (check_per_event(current->thread.per_event.cause,
  89. current->thread.per_user.control, regs)) {
  90. /* fix per address */
  91. current->thread.per_event.address = utask->vaddr;
  92. /* trigger per event */
  93. set_thread_flag(TIF_PER_TRAP);
  94. }
  95. return 0;
  96. }
  97. int arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val,
  98. void *data)
  99. {
  100. struct die_args *args = data;
  101. struct pt_regs *regs = args->regs;
  102. if (!user_mode(regs))
  103. return NOTIFY_DONE;
  104. if (regs->int_code & 0x200) /* Trap during transaction */
  105. return NOTIFY_DONE;
  106. switch (val) {
  107. case DIE_BPT:
  108. if (uprobe_pre_sstep_notifier(regs))
  109. return NOTIFY_STOP;
  110. break;
  111. case DIE_SSTEP:
  112. if (uprobe_post_sstep_notifier(regs))
  113. return NOTIFY_STOP;
  114. break;
  115. default:
  116. break;
  117. }
  118. return NOTIFY_DONE;
  119. }
  120. void arch_uprobe_abort_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
  121. {
  122. clear_thread_flag(TIF_UPROBE_SINGLESTEP);
  123. regs->int_code = auprobe->saved_int_code;
  124. regs->psw.addr = current->utask->vaddr;
  125. current->thread.per_event.address = current->utask->vaddr;
  126. }
  127. unsigned long arch_uretprobe_hijack_return_addr(unsigned long trampoline,
  128. struct pt_regs *regs)
  129. {
  130. unsigned long orig;
  131. orig = regs->gprs[14];
  132. regs->gprs[14] = trampoline;
  133. return orig;
  134. }
  135. bool arch_uretprobe_is_alive(struct return_instance *ret, enum rp_check ctx,
  136. struct pt_regs *regs)
  137. {
  138. if (ctx == RP_CHECK_CHAIN_CALL)
  139. return user_stack_pointer(regs) <= ret->stack;
  140. else
  141. return user_stack_pointer(regs) < ret->stack;
  142. }
  143. /* Instruction Emulation */
  144. static void adjust_psw_addr(psw_t *psw, unsigned long len)
  145. {
  146. psw->addr = __rewind_psw(*psw, -len);
  147. }
  148. #define EMU_ILLEGAL_OP 1
  149. #define EMU_SPECIFICATION 2
  150. #define EMU_ADDRESSING 3
  151. #define emu_load_ril(ptr, output) \
  152. ({ \
  153. unsigned int mask = sizeof(*(ptr)) - 1; \
  154. __typeof__(*(ptr)) input; \
  155. int __rc = 0; \
  156. \
  157. if ((u64 __force)ptr & mask) \
  158. __rc = EMU_SPECIFICATION; \
  159. else if (get_user(input, ptr)) \
  160. __rc = EMU_ADDRESSING; \
  161. else \
  162. *(output) = input; \
  163. __rc; \
  164. })
  165. #define emu_store_ril(regs, ptr, input) \
  166. ({ \
  167. unsigned int mask = sizeof(*(ptr)) - 1; \
  168. __typeof__(ptr) __ptr = (ptr); \
  169. int __rc = 0; \
  170. \
  171. if ((u64 __force)__ptr & mask) \
  172. __rc = EMU_SPECIFICATION; \
  173. else if (put_user(*(input), __ptr)) \
  174. __rc = EMU_ADDRESSING; \
  175. if (__rc == 0) \
  176. sim_stor_event(regs, \
  177. (void __force *)__ptr, \
  178. mask + 1); \
  179. __rc; \
  180. })
  181. #define emu_cmp_ril(regs, ptr, cmp) \
  182. ({ \
  183. unsigned int mask = sizeof(*(ptr)) - 1; \
  184. __typeof__(*(ptr)) input; \
  185. int __rc = 0; \
  186. \
  187. if ((u64 __force)ptr & mask) \
  188. __rc = EMU_SPECIFICATION; \
  189. else if (get_user(input, ptr)) \
  190. __rc = EMU_ADDRESSING; \
  191. else if (input > *(cmp)) \
  192. psw_bits((regs)->psw).cc = 1; \
  193. else if (input < *(cmp)) \
  194. psw_bits((regs)->psw).cc = 2; \
  195. else \
  196. psw_bits((regs)->psw).cc = 0; \
  197. __rc; \
  198. })
  199. struct insn_ril {
  200. u8 opc0;
  201. u8 reg : 4;
  202. u8 opc1 : 4;
  203. s32 disp;
  204. } __packed;
  205. union split_register {
  206. u64 u64;
  207. u32 u32[2];
  208. u16 u16[4];
  209. s64 s64;
  210. s32 s32[2];
  211. s16 s16[4];
  212. };
  213. /*
  214. * If user per registers are setup to trace storage alterations and an
  215. * emulated store took place on a fitting address a user trap is generated.
  216. */
  217. static void sim_stor_event(struct pt_regs *regs, void *addr, int len)
  218. {
  219. if (!(regs->psw.mask & PSW_MASK_PER))
  220. return;
  221. if (!(current->thread.per_user.control & PER_EVENT_STORE))
  222. return;
  223. if ((void *)current->thread.per_user.start > (addr + len))
  224. return;
  225. if ((void *)current->thread.per_user.end < addr)
  226. return;
  227. current->thread.per_event.address = regs->psw.addr;
  228. current->thread.per_event.cause = PER_EVENT_STORE >> 16;
  229. set_thread_flag(TIF_PER_TRAP);
  230. }
  231. /*
  232. * pc relative instructions are emulated, since parameters may not be
  233. * accessible from the xol area due to range limitations.
  234. */
  235. static void handle_insn_ril(struct arch_uprobe *auprobe, struct pt_regs *regs)
  236. {
  237. union split_register *rx;
  238. struct insn_ril *insn;
  239. unsigned int ilen;
  240. void *uptr;
  241. int rc = 0;
  242. insn = (struct insn_ril *) &auprobe->insn;
  243. rx = (union split_register *) &regs->gprs[insn->reg];
  244. uptr = (void *)(regs->psw.addr + (insn->disp * 2));
  245. ilen = insn_length(insn->opc0);
  246. switch (insn->opc0) {
  247. case 0xc0:
  248. switch (insn->opc1) {
  249. case 0x00: /* larl */
  250. rx->u64 = (unsigned long)uptr;
  251. break;
  252. }
  253. break;
  254. case 0xc4:
  255. switch (insn->opc1) {
  256. case 0x02: /* llhrl */
  257. rc = emu_load_ril((u16 __user *)uptr, &rx->u32[1]);
  258. break;
  259. case 0x04: /* lghrl */
  260. rc = emu_load_ril((s16 __user *)uptr, &rx->u64);
  261. break;
  262. case 0x05: /* lhrl */
  263. rc = emu_load_ril((s16 __user *)uptr, &rx->u32[1]);
  264. break;
  265. case 0x06: /* llghrl */
  266. rc = emu_load_ril((u16 __user *)uptr, &rx->u64);
  267. break;
  268. case 0x08: /* lgrl */
  269. rc = emu_load_ril((u64 __user *)uptr, &rx->u64);
  270. break;
  271. case 0x0c: /* lgfrl */
  272. rc = emu_load_ril((s32 __user *)uptr, &rx->u64);
  273. break;
  274. case 0x0d: /* lrl */
  275. rc = emu_load_ril((u32 __user *)uptr, &rx->u32[1]);
  276. break;
  277. case 0x0e: /* llgfrl */
  278. rc = emu_load_ril((u32 __user *)uptr, &rx->u64);
  279. break;
  280. case 0x07: /* sthrl */
  281. rc = emu_store_ril(regs, (u16 __user *)uptr, &rx->u16[3]);
  282. break;
  283. case 0x0b: /* stgrl */
  284. rc = emu_store_ril(regs, (u64 __user *)uptr, &rx->u64);
  285. break;
  286. case 0x0f: /* strl */
  287. rc = emu_store_ril(regs, (u32 __user *)uptr, &rx->u32[1]);
  288. break;
  289. }
  290. break;
  291. case 0xc6:
  292. switch (insn->opc1) {
  293. case 0x04: /* cghrl */
  294. rc = emu_cmp_ril(regs, (s16 __user *)uptr, &rx->s64);
  295. break;
  296. case 0x05: /* chrl */
  297. rc = emu_cmp_ril(regs, (s16 __user *)uptr, &rx->s32[1]);
  298. break;
  299. case 0x06: /* clghrl */
  300. rc = emu_cmp_ril(regs, (u16 __user *)uptr, &rx->u64);
  301. break;
  302. case 0x07: /* clhrl */
  303. rc = emu_cmp_ril(regs, (u16 __user *)uptr, &rx->u32[1]);
  304. break;
  305. case 0x08: /* cgrl */
  306. rc = emu_cmp_ril(regs, (s64 __user *)uptr, &rx->s64);
  307. break;
  308. case 0x0a: /* clgrl */
  309. rc = emu_cmp_ril(regs, (u64 __user *)uptr, &rx->u64);
  310. break;
  311. case 0x0c: /* cgfrl */
  312. rc = emu_cmp_ril(regs, (s32 __user *)uptr, &rx->s64);
  313. break;
  314. case 0x0d: /* crl */
  315. rc = emu_cmp_ril(regs, (s32 __user *)uptr, &rx->s32[1]);
  316. break;
  317. case 0x0e: /* clgfrl */
  318. rc = emu_cmp_ril(regs, (u32 __user *)uptr, &rx->u64);
  319. break;
  320. case 0x0f: /* clrl */
  321. rc = emu_cmp_ril(regs, (u32 __user *)uptr, &rx->u32[1]);
  322. break;
  323. }
  324. break;
  325. }
  326. adjust_psw_addr(&regs->psw, ilen);
  327. switch (rc) {
  328. case EMU_ILLEGAL_OP:
  329. regs->int_code = ilen << 16 | 0x0001;
  330. do_report_trap(regs, SIGILL, ILL_ILLOPC, NULL);
  331. break;
  332. case EMU_SPECIFICATION:
  333. regs->int_code = ilen << 16 | 0x0006;
  334. do_report_trap(regs, SIGILL, ILL_ILLOPC , NULL);
  335. break;
  336. case EMU_ADDRESSING:
  337. regs->int_code = ilen << 16 | 0x0005;
  338. do_report_trap(regs, SIGSEGV, SEGV_MAPERR, NULL);
  339. break;
  340. }
  341. }
  342. bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
  343. {
  344. if ((psw_bits(regs->psw).eaba == PSW_BITS_AMODE_24BIT) ||
  345. ((psw_bits(regs->psw).eaba == PSW_BITS_AMODE_31BIT) &&
  346. !is_compat_task())) {
  347. regs->psw.addr = __rewind_psw(regs->psw, UPROBE_SWBP_INSN_SIZE);
  348. do_report_trap(regs, SIGILL, ILL_ILLADR, NULL);
  349. return true;
  350. }
  351. if (probe_is_insn_relative_long(auprobe->insn)) {
  352. handle_insn_ril(auprobe, regs);
  353. return true;
  354. }
  355. return false;
  356. }