smp.c 33 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * SMP related functions
  4. *
  5. * Copyright IBM Corp. 1999, 2012
  6. * Author(s): Denis Joseph Barrow,
  7. * Martin Schwidefsky <[email protected]>,
  8. *
  9. * based on other smp stuff by
  10. * (c) 1995 Alan Cox, CymruNET Ltd <[email protected]>
  11. * (c) 1998 Ingo Molnar
  12. *
  13. * The code outside of smp.c uses logical cpu numbers, only smp.c does
  14. * the translation of logical to physical cpu ids. All new code that
  15. * operates on physical cpu numbers needs to go into smp.c.
  16. */
  17. #define KMSG_COMPONENT "cpu"
  18. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  19. #include <linux/workqueue.h>
  20. #include <linux/memblock.h>
  21. #include <linux/export.h>
  22. #include <linux/init.h>
  23. #include <linux/mm.h>
  24. #include <linux/err.h>
  25. #include <linux/spinlock.h>
  26. #include <linux/kernel_stat.h>
  27. #include <linux/delay.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/irqflags.h>
  30. #include <linux/irq_work.h>
  31. #include <linux/cpu.h>
  32. #include <linux/slab.h>
  33. #include <linux/sched/hotplug.h>
  34. #include <linux/sched/task_stack.h>
  35. #include <linux/crash_dump.h>
  36. #include <linux/kprobes.h>
  37. #include <asm/asm-offsets.h>
  38. #include <asm/diag.h>
  39. #include <asm/switch_to.h>
  40. #include <asm/facility.h>
  41. #include <asm/ipl.h>
  42. #include <asm/setup.h>
  43. #include <asm/irq.h>
  44. #include <asm/tlbflush.h>
  45. #include <asm/vtimer.h>
  46. #include <asm/abs_lowcore.h>
  47. #include <asm/sclp.h>
  48. #include <asm/debug.h>
  49. #include <asm/os_info.h>
  50. #include <asm/sigp.h>
  51. #include <asm/idle.h>
  52. #include <asm/nmi.h>
  53. #include <asm/stacktrace.h>
  54. #include <asm/topology.h>
  55. #include <asm/vdso.h>
  56. #include <asm/maccess.h>
  57. #include "entry.h"
  58. enum {
  59. ec_schedule = 0,
  60. ec_call_function_single,
  61. ec_stop_cpu,
  62. ec_mcck_pending,
  63. ec_irq_work,
  64. };
  65. enum {
  66. CPU_STATE_STANDBY,
  67. CPU_STATE_CONFIGURED,
  68. };
  69. static DEFINE_PER_CPU(struct cpu *, cpu_device);
  70. struct pcpu {
  71. unsigned long ec_mask; /* bit mask for ec_xxx functions */
  72. unsigned long ec_clk; /* sigp timestamp for ec_xxx */
  73. signed char state; /* physical cpu state */
  74. signed char polarization; /* physical polarization */
  75. u16 address; /* physical cpu address */
  76. };
  77. static u8 boot_core_type;
  78. static struct pcpu pcpu_devices[NR_CPUS];
  79. unsigned int smp_cpu_mt_shift;
  80. EXPORT_SYMBOL(smp_cpu_mt_shift);
  81. unsigned int smp_cpu_mtid;
  82. EXPORT_SYMBOL(smp_cpu_mtid);
  83. #ifdef CONFIG_CRASH_DUMP
  84. __vector128 __initdata boot_cpu_vector_save_area[__NUM_VXRS];
  85. #endif
  86. static unsigned int smp_max_threads __initdata = -1U;
  87. cpumask_t cpu_setup_mask;
  88. static int __init early_nosmt(char *s)
  89. {
  90. smp_max_threads = 1;
  91. return 0;
  92. }
  93. early_param("nosmt", early_nosmt);
  94. static int __init early_smt(char *s)
  95. {
  96. get_option(&s, &smp_max_threads);
  97. return 0;
  98. }
  99. early_param("smt", early_smt);
  100. /*
  101. * The smp_cpu_state_mutex must be held when changing the state or polarization
  102. * member of a pcpu data structure within the pcpu_devices arreay.
  103. */
  104. DEFINE_MUTEX(smp_cpu_state_mutex);
  105. /*
  106. * Signal processor helper functions.
  107. */
  108. static inline int __pcpu_sigp_relax(u16 addr, u8 order, unsigned long parm)
  109. {
  110. int cc;
  111. while (1) {
  112. cc = __pcpu_sigp(addr, order, parm, NULL);
  113. if (cc != SIGP_CC_BUSY)
  114. return cc;
  115. cpu_relax();
  116. }
  117. }
  118. static int pcpu_sigp_retry(struct pcpu *pcpu, u8 order, u32 parm)
  119. {
  120. int cc, retry;
  121. for (retry = 0; ; retry++) {
  122. cc = __pcpu_sigp(pcpu->address, order, parm, NULL);
  123. if (cc != SIGP_CC_BUSY)
  124. break;
  125. if (retry >= 3)
  126. udelay(10);
  127. }
  128. return cc;
  129. }
  130. static inline int pcpu_stopped(struct pcpu *pcpu)
  131. {
  132. u32 status;
  133. if (__pcpu_sigp(pcpu->address, SIGP_SENSE,
  134. 0, &status) != SIGP_CC_STATUS_STORED)
  135. return 0;
  136. return !!(status & (SIGP_STATUS_CHECK_STOP|SIGP_STATUS_STOPPED));
  137. }
  138. static inline int pcpu_running(struct pcpu *pcpu)
  139. {
  140. if (__pcpu_sigp(pcpu->address, SIGP_SENSE_RUNNING,
  141. 0, NULL) != SIGP_CC_STATUS_STORED)
  142. return 1;
  143. /* Status stored condition code is equivalent to cpu not running. */
  144. return 0;
  145. }
  146. /*
  147. * Find struct pcpu by cpu address.
  148. */
  149. static struct pcpu *pcpu_find_address(const struct cpumask *mask, u16 address)
  150. {
  151. int cpu;
  152. for_each_cpu(cpu, mask)
  153. if (pcpu_devices[cpu].address == address)
  154. return pcpu_devices + cpu;
  155. return NULL;
  156. }
  157. static void pcpu_ec_call(struct pcpu *pcpu, int ec_bit)
  158. {
  159. int order;
  160. if (test_and_set_bit(ec_bit, &pcpu->ec_mask))
  161. return;
  162. order = pcpu_running(pcpu) ? SIGP_EXTERNAL_CALL : SIGP_EMERGENCY_SIGNAL;
  163. pcpu->ec_clk = get_tod_clock_fast();
  164. pcpu_sigp_retry(pcpu, order, 0);
  165. }
  166. static int pcpu_alloc_lowcore(struct pcpu *pcpu, int cpu)
  167. {
  168. unsigned long async_stack, nodat_stack, mcck_stack;
  169. struct lowcore *lc;
  170. lc = (struct lowcore *) __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER);
  171. nodat_stack = __get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER);
  172. async_stack = stack_alloc();
  173. mcck_stack = stack_alloc();
  174. if (!lc || !nodat_stack || !async_stack || !mcck_stack)
  175. goto out;
  176. memcpy(lc, &S390_lowcore, 512);
  177. memset((char *) lc + 512, 0, sizeof(*lc) - 512);
  178. lc->async_stack = async_stack + STACK_INIT_OFFSET;
  179. lc->nodat_stack = nodat_stack + STACK_INIT_OFFSET;
  180. lc->mcck_stack = mcck_stack + STACK_INIT_OFFSET;
  181. lc->cpu_nr = cpu;
  182. lc->spinlock_lockval = arch_spin_lockval(cpu);
  183. lc->spinlock_index = 0;
  184. lc->return_lpswe = gen_lpswe(__LC_RETURN_PSW);
  185. lc->return_mcck_lpswe = gen_lpswe(__LC_RETURN_MCCK_PSW);
  186. lc->preempt_count = PREEMPT_DISABLED;
  187. if (nmi_alloc_mcesa(&lc->mcesad))
  188. goto out;
  189. if (abs_lowcore_map(cpu, lc, true))
  190. goto out_mcesa;
  191. lowcore_ptr[cpu] = lc;
  192. pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, __pa(lc));
  193. return 0;
  194. out_mcesa:
  195. nmi_free_mcesa(&lc->mcesad);
  196. out:
  197. stack_free(mcck_stack);
  198. stack_free(async_stack);
  199. free_pages(nodat_stack, THREAD_SIZE_ORDER);
  200. free_pages((unsigned long) lc, LC_ORDER);
  201. return -ENOMEM;
  202. }
  203. static void pcpu_free_lowcore(struct pcpu *pcpu)
  204. {
  205. unsigned long async_stack, nodat_stack, mcck_stack;
  206. struct lowcore *lc;
  207. int cpu;
  208. cpu = pcpu - pcpu_devices;
  209. lc = lowcore_ptr[cpu];
  210. nodat_stack = lc->nodat_stack - STACK_INIT_OFFSET;
  211. async_stack = lc->async_stack - STACK_INIT_OFFSET;
  212. mcck_stack = lc->mcck_stack - STACK_INIT_OFFSET;
  213. pcpu_sigp_retry(pcpu, SIGP_SET_PREFIX, 0);
  214. lowcore_ptr[cpu] = NULL;
  215. abs_lowcore_unmap(cpu);
  216. nmi_free_mcesa(&lc->mcesad);
  217. stack_free(async_stack);
  218. stack_free(mcck_stack);
  219. free_pages(nodat_stack, THREAD_SIZE_ORDER);
  220. free_pages((unsigned long) lc, LC_ORDER);
  221. }
  222. static void pcpu_prepare_secondary(struct pcpu *pcpu, int cpu)
  223. {
  224. struct lowcore *lc = lowcore_ptr[cpu];
  225. cpumask_set_cpu(cpu, &init_mm.context.cpu_attach_mask);
  226. cpumask_set_cpu(cpu, mm_cpumask(&init_mm));
  227. lc->cpu_nr = cpu;
  228. lc->restart_flags = RESTART_FLAG_CTLREGS;
  229. lc->spinlock_lockval = arch_spin_lockval(cpu);
  230. lc->spinlock_index = 0;
  231. lc->percpu_offset = __per_cpu_offset[cpu];
  232. lc->kernel_asce = S390_lowcore.kernel_asce;
  233. lc->user_asce = s390_invalid_asce;
  234. lc->machine_flags = S390_lowcore.machine_flags;
  235. lc->user_timer = lc->system_timer =
  236. lc->steal_timer = lc->avg_steal_timer = 0;
  237. __ctl_store(lc->cregs_save_area, 0, 15);
  238. lc->cregs_save_area[1] = lc->kernel_asce;
  239. lc->cregs_save_area[7] = lc->user_asce;
  240. save_access_regs((unsigned int *) lc->access_regs_save_area);
  241. arch_spin_lock_setup(cpu);
  242. }
  243. static void pcpu_attach_task(struct pcpu *pcpu, struct task_struct *tsk)
  244. {
  245. struct lowcore *lc;
  246. int cpu;
  247. cpu = pcpu - pcpu_devices;
  248. lc = lowcore_ptr[cpu];
  249. lc->kernel_stack = (unsigned long) task_stack_page(tsk)
  250. + THREAD_SIZE - STACK_FRAME_OVERHEAD - sizeof(struct pt_regs);
  251. lc->current_task = (unsigned long) tsk;
  252. lc->lpp = LPP_MAGIC;
  253. lc->current_pid = tsk->pid;
  254. lc->user_timer = tsk->thread.user_timer;
  255. lc->guest_timer = tsk->thread.guest_timer;
  256. lc->system_timer = tsk->thread.system_timer;
  257. lc->hardirq_timer = tsk->thread.hardirq_timer;
  258. lc->softirq_timer = tsk->thread.softirq_timer;
  259. lc->steal_timer = 0;
  260. }
  261. static void pcpu_start_fn(struct pcpu *pcpu, void (*func)(void *), void *data)
  262. {
  263. struct lowcore *lc;
  264. int cpu;
  265. cpu = pcpu - pcpu_devices;
  266. lc = lowcore_ptr[cpu];
  267. lc->restart_stack = lc->kernel_stack;
  268. lc->restart_fn = (unsigned long) func;
  269. lc->restart_data = (unsigned long) data;
  270. lc->restart_source = -1U;
  271. pcpu_sigp_retry(pcpu, SIGP_RESTART, 0);
  272. }
  273. typedef void (pcpu_delegate_fn)(void *);
  274. /*
  275. * Call function via PSW restart on pcpu and stop the current cpu.
  276. */
  277. static void __pcpu_delegate(pcpu_delegate_fn *func, void *data)
  278. {
  279. func(data); /* should not return */
  280. }
  281. static void pcpu_delegate(struct pcpu *pcpu,
  282. pcpu_delegate_fn *func,
  283. void *data, unsigned long stack)
  284. {
  285. struct lowcore *lc, *abs_lc;
  286. unsigned int source_cpu;
  287. unsigned long flags;
  288. lc = lowcore_ptr[pcpu - pcpu_devices];
  289. source_cpu = stap();
  290. __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT);
  291. if (pcpu->address == source_cpu) {
  292. call_on_stack(2, stack, void, __pcpu_delegate,
  293. pcpu_delegate_fn *, func, void *, data);
  294. }
  295. /* Stop target cpu (if func returns this stops the current cpu). */
  296. pcpu_sigp_retry(pcpu, SIGP_STOP, 0);
  297. /* Restart func on the target cpu and stop the current cpu. */
  298. if (lc) {
  299. lc->restart_stack = stack;
  300. lc->restart_fn = (unsigned long)func;
  301. lc->restart_data = (unsigned long)data;
  302. lc->restart_source = source_cpu;
  303. } else {
  304. abs_lc = get_abs_lowcore(&flags);
  305. abs_lc->restart_stack = stack;
  306. abs_lc->restart_fn = (unsigned long)func;
  307. abs_lc->restart_data = (unsigned long)data;
  308. abs_lc->restart_source = source_cpu;
  309. put_abs_lowcore(abs_lc, flags);
  310. }
  311. __bpon();
  312. asm volatile(
  313. "0: sigp 0,%0,%2 # sigp restart to target cpu\n"
  314. " brc 2,0b # busy, try again\n"
  315. "1: sigp 0,%1,%3 # sigp stop to current cpu\n"
  316. " brc 2,1b # busy, try again\n"
  317. : : "d" (pcpu->address), "d" (source_cpu),
  318. "K" (SIGP_RESTART), "K" (SIGP_STOP)
  319. : "0", "1", "cc");
  320. for (;;) ;
  321. }
  322. /*
  323. * Enable additional logical cpus for multi-threading.
  324. */
  325. static int pcpu_set_smt(unsigned int mtid)
  326. {
  327. int cc;
  328. if (smp_cpu_mtid == mtid)
  329. return 0;
  330. cc = __pcpu_sigp(0, SIGP_SET_MULTI_THREADING, mtid, NULL);
  331. if (cc == 0) {
  332. smp_cpu_mtid = mtid;
  333. smp_cpu_mt_shift = 0;
  334. while (smp_cpu_mtid >= (1U << smp_cpu_mt_shift))
  335. smp_cpu_mt_shift++;
  336. pcpu_devices[0].address = stap();
  337. }
  338. return cc;
  339. }
  340. /*
  341. * Call function on an online CPU.
  342. */
  343. void smp_call_online_cpu(void (*func)(void *), void *data)
  344. {
  345. struct pcpu *pcpu;
  346. /* Use the current cpu if it is online. */
  347. pcpu = pcpu_find_address(cpu_online_mask, stap());
  348. if (!pcpu)
  349. /* Use the first online cpu. */
  350. pcpu = pcpu_devices + cpumask_first(cpu_online_mask);
  351. pcpu_delegate(pcpu, func, data, (unsigned long) restart_stack);
  352. }
  353. /*
  354. * Call function on the ipl CPU.
  355. */
  356. void smp_call_ipl_cpu(void (*func)(void *), void *data)
  357. {
  358. struct lowcore *lc = lowcore_ptr[0];
  359. if (pcpu_devices[0].address == stap())
  360. lc = &S390_lowcore;
  361. pcpu_delegate(&pcpu_devices[0], func, data,
  362. lc->nodat_stack);
  363. }
  364. int smp_find_processor_id(u16 address)
  365. {
  366. int cpu;
  367. for_each_present_cpu(cpu)
  368. if (pcpu_devices[cpu].address == address)
  369. return cpu;
  370. return -1;
  371. }
  372. void schedule_mcck_handler(void)
  373. {
  374. pcpu_ec_call(pcpu_devices + smp_processor_id(), ec_mcck_pending);
  375. }
  376. bool notrace arch_vcpu_is_preempted(int cpu)
  377. {
  378. if (test_cpu_flag_of(CIF_ENABLED_WAIT, cpu))
  379. return false;
  380. if (pcpu_running(pcpu_devices + cpu))
  381. return false;
  382. return true;
  383. }
  384. EXPORT_SYMBOL(arch_vcpu_is_preempted);
  385. void notrace smp_yield_cpu(int cpu)
  386. {
  387. if (!MACHINE_HAS_DIAG9C)
  388. return;
  389. diag_stat_inc_norecursion(DIAG_STAT_X09C);
  390. asm volatile("diag %0,0,0x9c"
  391. : : "d" (pcpu_devices[cpu].address));
  392. }
  393. EXPORT_SYMBOL_GPL(smp_yield_cpu);
  394. /*
  395. * Send cpus emergency shutdown signal. This gives the cpus the
  396. * opportunity to complete outstanding interrupts.
  397. */
  398. void notrace smp_emergency_stop(void)
  399. {
  400. static arch_spinlock_t lock = __ARCH_SPIN_LOCK_UNLOCKED;
  401. static cpumask_t cpumask;
  402. u64 end;
  403. int cpu;
  404. arch_spin_lock(&lock);
  405. cpumask_copy(&cpumask, cpu_online_mask);
  406. cpumask_clear_cpu(smp_processor_id(), &cpumask);
  407. end = get_tod_clock() + (1000000UL << 12);
  408. for_each_cpu(cpu, &cpumask) {
  409. struct pcpu *pcpu = pcpu_devices + cpu;
  410. set_bit(ec_stop_cpu, &pcpu->ec_mask);
  411. while (__pcpu_sigp(pcpu->address, SIGP_EMERGENCY_SIGNAL,
  412. 0, NULL) == SIGP_CC_BUSY &&
  413. get_tod_clock() < end)
  414. cpu_relax();
  415. }
  416. while (get_tod_clock() < end) {
  417. for_each_cpu(cpu, &cpumask)
  418. if (pcpu_stopped(pcpu_devices + cpu))
  419. cpumask_clear_cpu(cpu, &cpumask);
  420. if (cpumask_empty(&cpumask))
  421. break;
  422. cpu_relax();
  423. }
  424. arch_spin_unlock(&lock);
  425. }
  426. NOKPROBE_SYMBOL(smp_emergency_stop);
  427. /*
  428. * Stop all cpus but the current one.
  429. */
  430. void smp_send_stop(void)
  431. {
  432. int cpu;
  433. /* Disable all interrupts/machine checks */
  434. __load_psw_mask(PSW_KERNEL_BITS | PSW_MASK_DAT);
  435. trace_hardirqs_off();
  436. debug_set_critical();
  437. if (oops_in_progress)
  438. smp_emergency_stop();
  439. /* stop all processors */
  440. for_each_online_cpu(cpu) {
  441. if (cpu == smp_processor_id())
  442. continue;
  443. pcpu_sigp_retry(pcpu_devices + cpu, SIGP_STOP, 0);
  444. while (!pcpu_stopped(pcpu_devices + cpu))
  445. cpu_relax();
  446. }
  447. }
  448. /*
  449. * This is the main routine where commands issued by other
  450. * cpus are handled.
  451. */
  452. static void smp_handle_ext_call(void)
  453. {
  454. unsigned long bits;
  455. /* handle bit signal external calls */
  456. bits = xchg(&pcpu_devices[smp_processor_id()].ec_mask, 0);
  457. if (test_bit(ec_stop_cpu, &bits))
  458. smp_stop_cpu();
  459. if (test_bit(ec_schedule, &bits))
  460. scheduler_ipi();
  461. if (test_bit(ec_call_function_single, &bits))
  462. generic_smp_call_function_single_interrupt();
  463. if (test_bit(ec_mcck_pending, &bits))
  464. __s390_handle_mcck();
  465. if (test_bit(ec_irq_work, &bits))
  466. irq_work_run();
  467. }
  468. static void do_ext_call_interrupt(struct ext_code ext_code,
  469. unsigned int param32, unsigned long param64)
  470. {
  471. inc_irq_stat(ext_code.code == 0x1202 ? IRQEXT_EXC : IRQEXT_EMS);
  472. smp_handle_ext_call();
  473. }
  474. void arch_send_call_function_ipi_mask(const struct cpumask *mask)
  475. {
  476. int cpu;
  477. for_each_cpu(cpu, mask)
  478. pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single);
  479. }
  480. void arch_send_call_function_single_ipi(int cpu)
  481. {
  482. pcpu_ec_call(pcpu_devices + cpu, ec_call_function_single);
  483. }
  484. /*
  485. * this function sends a 'reschedule' IPI to another CPU.
  486. * it goes straight through and wastes no time serializing
  487. * anything. Worst case is that we lose a reschedule ...
  488. */
  489. void smp_send_reschedule(int cpu)
  490. {
  491. pcpu_ec_call(pcpu_devices + cpu, ec_schedule);
  492. }
  493. #ifdef CONFIG_IRQ_WORK
  494. void arch_irq_work_raise(void)
  495. {
  496. pcpu_ec_call(pcpu_devices + smp_processor_id(), ec_irq_work);
  497. }
  498. #endif
  499. /*
  500. * parameter area for the set/clear control bit callbacks
  501. */
  502. struct ec_creg_mask_parms {
  503. unsigned long orval;
  504. unsigned long andval;
  505. int cr;
  506. };
  507. /*
  508. * callback for setting/clearing control bits
  509. */
  510. static void smp_ctl_bit_callback(void *info)
  511. {
  512. struct ec_creg_mask_parms *pp = info;
  513. unsigned long cregs[16];
  514. __ctl_store(cregs, 0, 15);
  515. cregs[pp->cr] = (cregs[pp->cr] & pp->andval) | pp->orval;
  516. __ctl_load(cregs, 0, 15);
  517. }
  518. static DEFINE_SPINLOCK(ctl_lock);
  519. void smp_ctl_set_clear_bit(int cr, int bit, bool set)
  520. {
  521. struct ec_creg_mask_parms parms = { .cr = cr, };
  522. struct lowcore *abs_lc;
  523. unsigned long flags;
  524. u64 ctlreg;
  525. if (set) {
  526. parms.orval = 1UL << bit;
  527. parms.andval = -1UL;
  528. } else {
  529. parms.orval = 0;
  530. parms.andval = ~(1UL << bit);
  531. }
  532. spin_lock(&ctl_lock);
  533. abs_lc = get_abs_lowcore(&flags);
  534. ctlreg = abs_lc->cregs_save_area[cr];
  535. ctlreg = (ctlreg & parms.andval) | parms.orval;
  536. abs_lc->cregs_save_area[cr] = ctlreg;
  537. put_abs_lowcore(abs_lc, flags);
  538. spin_unlock(&ctl_lock);
  539. on_each_cpu(smp_ctl_bit_callback, &parms, 1);
  540. }
  541. EXPORT_SYMBOL(smp_ctl_set_clear_bit);
  542. #ifdef CONFIG_CRASH_DUMP
  543. int smp_store_status(int cpu)
  544. {
  545. struct lowcore *lc;
  546. struct pcpu *pcpu;
  547. unsigned long pa;
  548. pcpu = pcpu_devices + cpu;
  549. lc = lowcore_ptr[cpu];
  550. pa = __pa(&lc->floating_pt_save_area);
  551. if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_STATUS_AT_ADDRESS,
  552. pa) != SIGP_CC_ORDER_CODE_ACCEPTED)
  553. return -EIO;
  554. if (!MACHINE_HAS_VX && !MACHINE_HAS_GS)
  555. return 0;
  556. pa = lc->mcesad & MCESA_ORIGIN_MASK;
  557. if (MACHINE_HAS_GS)
  558. pa |= lc->mcesad & MCESA_LC_MASK;
  559. if (__pcpu_sigp_relax(pcpu->address, SIGP_STORE_ADDITIONAL_STATUS,
  560. pa) != SIGP_CC_ORDER_CODE_ACCEPTED)
  561. return -EIO;
  562. return 0;
  563. }
  564. /*
  565. * Collect CPU state of the previous, crashed system.
  566. * There are four cases:
  567. * 1) standard zfcp/nvme dump
  568. * condition: OLDMEM_BASE == NULL && is_ipl_type_dump() == true
  569. * The state for all CPUs except the boot CPU needs to be collected
  570. * with sigp stop-and-store-status. The boot CPU state is located in
  571. * the absolute lowcore of the memory stored in the HSA. The zcore code
  572. * will copy the boot CPU state from the HSA.
  573. * 2) stand-alone kdump for SCSI/NVMe (zfcp/nvme dump with swapped memory)
  574. * condition: OLDMEM_BASE != NULL && is_ipl_type_dump() == true
  575. * The state for all CPUs except the boot CPU needs to be collected
  576. * with sigp stop-and-store-status. The firmware or the boot-loader
  577. * stored the registers of the boot CPU in the absolute lowcore in the
  578. * memory of the old system.
  579. * 3) kdump and the old kernel did not store the CPU state,
  580. * or stand-alone kdump for DASD
  581. * condition: OLDMEM_BASE != NULL && !is_kdump_kernel()
  582. * The state for all CPUs except the boot CPU needs to be collected
  583. * with sigp stop-and-store-status. The kexec code or the boot-loader
  584. * stored the registers of the boot CPU in the memory of the old system.
  585. * 4) kdump and the old kernel stored the CPU state
  586. * condition: OLDMEM_BASE != NULL && is_kdump_kernel()
  587. * This case does not exist for s390 anymore, setup_arch explicitly
  588. * deactivates the elfcorehdr= kernel parameter
  589. */
  590. static bool dump_available(void)
  591. {
  592. return oldmem_data.start || is_ipl_type_dump();
  593. }
  594. void __init smp_save_dump_ipl_cpu(void)
  595. {
  596. struct save_area *sa;
  597. void *regs;
  598. if (!dump_available())
  599. return;
  600. sa = save_area_alloc(true);
  601. regs = memblock_alloc(512, 8);
  602. if (!sa || !regs)
  603. panic("could not allocate memory for boot CPU save area\n");
  604. copy_oldmem_kernel(regs, __LC_FPREGS_SAVE_AREA, 512);
  605. save_area_add_regs(sa, regs);
  606. memblock_free(regs, 512);
  607. if (MACHINE_HAS_VX)
  608. save_area_add_vxrs(sa, boot_cpu_vector_save_area);
  609. }
  610. void __init smp_save_dump_secondary_cpus(void)
  611. {
  612. int addr, boot_cpu_addr, max_cpu_addr;
  613. struct save_area *sa;
  614. void *page;
  615. if (!dump_available())
  616. return;
  617. /* Allocate a page as dumping area for the store status sigps */
  618. page = memblock_alloc_low(PAGE_SIZE, PAGE_SIZE);
  619. if (!page)
  620. panic("ERROR: Failed to allocate %lx bytes below %lx\n",
  621. PAGE_SIZE, 1UL << 31);
  622. /* Set multi-threading state to the previous system. */
  623. pcpu_set_smt(sclp.mtid_prev);
  624. boot_cpu_addr = stap();
  625. max_cpu_addr = SCLP_MAX_CORES << sclp.mtid_prev;
  626. for (addr = 0; addr <= max_cpu_addr; addr++) {
  627. if (addr == boot_cpu_addr)
  628. continue;
  629. if (__pcpu_sigp_relax(addr, SIGP_SENSE, 0) ==
  630. SIGP_CC_NOT_OPERATIONAL)
  631. continue;
  632. sa = save_area_alloc(false);
  633. if (!sa)
  634. panic("could not allocate memory for save area\n");
  635. __pcpu_sigp_relax(addr, SIGP_STORE_STATUS_AT_ADDRESS, __pa(page));
  636. save_area_add_regs(sa, page);
  637. if (MACHINE_HAS_VX) {
  638. __pcpu_sigp_relax(addr, SIGP_STORE_ADDITIONAL_STATUS, __pa(page));
  639. save_area_add_vxrs(sa, page);
  640. }
  641. }
  642. memblock_free(page, PAGE_SIZE);
  643. diag_amode31_ops.diag308_reset();
  644. pcpu_set_smt(0);
  645. }
  646. #endif /* CONFIG_CRASH_DUMP */
  647. void smp_cpu_set_polarization(int cpu, int val)
  648. {
  649. pcpu_devices[cpu].polarization = val;
  650. }
  651. int smp_cpu_get_polarization(int cpu)
  652. {
  653. return pcpu_devices[cpu].polarization;
  654. }
  655. int smp_cpu_get_cpu_address(int cpu)
  656. {
  657. return pcpu_devices[cpu].address;
  658. }
  659. static void __ref smp_get_core_info(struct sclp_core_info *info, int early)
  660. {
  661. static int use_sigp_detection;
  662. int address;
  663. if (use_sigp_detection || sclp_get_core_info(info, early)) {
  664. use_sigp_detection = 1;
  665. for (address = 0;
  666. address < (SCLP_MAX_CORES << smp_cpu_mt_shift);
  667. address += (1U << smp_cpu_mt_shift)) {
  668. if (__pcpu_sigp_relax(address, SIGP_SENSE, 0) ==
  669. SIGP_CC_NOT_OPERATIONAL)
  670. continue;
  671. info->core[info->configured].core_id =
  672. address >> smp_cpu_mt_shift;
  673. info->configured++;
  674. }
  675. info->combined = info->configured;
  676. }
  677. }
  678. static int smp_add_present_cpu(int cpu);
  679. static int smp_add_core(struct sclp_core_entry *core, cpumask_t *avail,
  680. bool configured, bool early)
  681. {
  682. struct pcpu *pcpu;
  683. int cpu, nr, i;
  684. u16 address;
  685. nr = 0;
  686. if (sclp.has_core_type && core->type != boot_core_type)
  687. return nr;
  688. cpu = cpumask_first(avail);
  689. address = core->core_id << smp_cpu_mt_shift;
  690. for (i = 0; (i <= smp_cpu_mtid) && (cpu < nr_cpu_ids); i++) {
  691. if (pcpu_find_address(cpu_present_mask, address + i))
  692. continue;
  693. pcpu = pcpu_devices + cpu;
  694. pcpu->address = address + i;
  695. if (configured)
  696. pcpu->state = CPU_STATE_CONFIGURED;
  697. else
  698. pcpu->state = CPU_STATE_STANDBY;
  699. smp_cpu_set_polarization(cpu, POLARIZATION_UNKNOWN);
  700. set_cpu_present(cpu, true);
  701. if (!early && smp_add_present_cpu(cpu) != 0)
  702. set_cpu_present(cpu, false);
  703. else
  704. nr++;
  705. cpumask_clear_cpu(cpu, avail);
  706. cpu = cpumask_next(cpu, avail);
  707. }
  708. return nr;
  709. }
  710. static int __smp_rescan_cpus(struct sclp_core_info *info, bool early)
  711. {
  712. struct sclp_core_entry *core;
  713. static cpumask_t avail;
  714. bool configured;
  715. u16 core_id;
  716. int nr, i;
  717. cpus_read_lock();
  718. mutex_lock(&smp_cpu_state_mutex);
  719. nr = 0;
  720. cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask);
  721. /*
  722. * Add IPL core first (which got logical CPU number 0) to make sure
  723. * that all SMT threads get subsequent logical CPU numbers.
  724. */
  725. if (early) {
  726. core_id = pcpu_devices[0].address >> smp_cpu_mt_shift;
  727. for (i = 0; i < info->configured; i++) {
  728. core = &info->core[i];
  729. if (core->core_id == core_id) {
  730. nr += smp_add_core(core, &avail, true, early);
  731. break;
  732. }
  733. }
  734. }
  735. for (i = 0; i < info->combined; i++) {
  736. configured = i < info->configured;
  737. nr += smp_add_core(&info->core[i], &avail, configured, early);
  738. }
  739. mutex_unlock(&smp_cpu_state_mutex);
  740. cpus_read_unlock();
  741. return nr;
  742. }
  743. void __init smp_detect_cpus(void)
  744. {
  745. unsigned int cpu, mtid, c_cpus, s_cpus;
  746. struct sclp_core_info *info;
  747. u16 address;
  748. /* Get CPU information */
  749. info = memblock_alloc(sizeof(*info), 8);
  750. if (!info)
  751. panic("%s: Failed to allocate %zu bytes align=0x%x\n",
  752. __func__, sizeof(*info), 8);
  753. smp_get_core_info(info, 1);
  754. /* Find boot CPU type */
  755. if (sclp.has_core_type) {
  756. address = stap();
  757. for (cpu = 0; cpu < info->combined; cpu++)
  758. if (info->core[cpu].core_id == address) {
  759. /* The boot cpu dictates the cpu type. */
  760. boot_core_type = info->core[cpu].type;
  761. break;
  762. }
  763. if (cpu >= info->combined)
  764. panic("Could not find boot CPU type");
  765. }
  766. /* Set multi-threading state for the current system */
  767. mtid = boot_core_type ? sclp.mtid : sclp.mtid_cp;
  768. mtid = (mtid < smp_max_threads) ? mtid : smp_max_threads - 1;
  769. pcpu_set_smt(mtid);
  770. /* Print number of CPUs */
  771. c_cpus = s_cpus = 0;
  772. for (cpu = 0; cpu < info->combined; cpu++) {
  773. if (sclp.has_core_type &&
  774. info->core[cpu].type != boot_core_type)
  775. continue;
  776. if (cpu < info->configured)
  777. c_cpus += smp_cpu_mtid + 1;
  778. else
  779. s_cpus += smp_cpu_mtid + 1;
  780. }
  781. pr_info("%d configured CPUs, %d standby CPUs\n", c_cpus, s_cpus);
  782. /* Add CPUs present at boot */
  783. __smp_rescan_cpus(info, true);
  784. memblock_free(info, sizeof(*info));
  785. }
  786. /*
  787. * Activate a secondary processor.
  788. */
  789. static void smp_start_secondary(void *cpuvoid)
  790. {
  791. int cpu = raw_smp_processor_id();
  792. S390_lowcore.last_update_clock = get_tod_clock();
  793. S390_lowcore.restart_stack = (unsigned long)restart_stack;
  794. S390_lowcore.restart_fn = (unsigned long)do_restart;
  795. S390_lowcore.restart_data = 0;
  796. S390_lowcore.restart_source = -1U;
  797. S390_lowcore.restart_flags = 0;
  798. restore_access_regs(S390_lowcore.access_regs_save_area);
  799. cpu_init();
  800. rcu_cpu_starting(cpu);
  801. init_cpu_timer();
  802. vtime_init();
  803. vdso_getcpu_init();
  804. pfault_init();
  805. cpumask_set_cpu(cpu, &cpu_setup_mask);
  806. update_cpu_masks();
  807. notify_cpu_starting(cpu);
  808. if (topology_cpu_dedicated(cpu))
  809. set_cpu_flag(CIF_DEDICATED_CPU);
  810. else
  811. clear_cpu_flag(CIF_DEDICATED_CPU);
  812. set_cpu_online(cpu, true);
  813. inc_irq_stat(CPU_RST);
  814. local_irq_enable();
  815. cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
  816. }
  817. /* Upping and downing of CPUs */
  818. int __cpu_up(unsigned int cpu, struct task_struct *tidle)
  819. {
  820. struct pcpu *pcpu = pcpu_devices + cpu;
  821. int rc;
  822. if (pcpu->state != CPU_STATE_CONFIGURED)
  823. return -EIO;
  824. if (pcpu_sigp_retry(pcpu, SIGP_INITIAL_CPU_RESET, 0) !=
  825. SIGP_CC_ORDER_CODE_ACCEPTED)
  826. return -EIO;
  827. rc = pcpu_alloc_lowcore(pcpu, cpu);
  828. if (rc)
  829. return rc;
  830. pcpu_prepare_secondary(pcpu, cpu);
  831. pcpu_attach_task(pcpu, tidle);
  832. pcpu_start_fn(pcpu, smp_start_secondary, NULL);
  833. /* Wait until cpu puts itself in the online & active maps */
  834. while (!cpu_online(cpu))
  835. cpu_relax();
  836. return 0;
  837. }
  838. static unsigned int setup_possible_cpus __initdata;
  839. static int __init _setup_possible_cpus(char *s)
  840. {
  841. get_option(&s, &setup_possible_cpus);
  842. return 0;
  843. }
  844. early_param("possible_cpus", _setup_possible_cpus);
  845. int __cpu_disable(void)
  846. {
  847. unsigned long cregs[16];
  848. int cpu;
  849. /* Handle possible pending IPIs */
  850. smp_handle_ext_call();
  851. cpu = smp_processor_id();
  852. set_cpu_online(cpu, false);
  853. cpumask_clear_cpu(cpu, &cpu_setup_mask);
  854. update_cpu_masks();
  855. /* Disable pseudo page faults on this cpu. */
  856. pfault_fini();
  857. /* Disable interrupt sources via control register. */
  858. __ctl_store(cregs, 0, 15);
  859. cregs[0] &= ~0x0000ee70UL; /* disable all external interrupts */
  860. cregs[6] &= ~0xff000000UL; /* disable all I/O interrupts */
  861. cregs[14] &= ~0x1f000000UL; /* disable most machine checks */
  862. __ctl_load(cregs, 0, 15);
  863. clear_cpu_flag(CIF_NOHZ_DELAY);
  864. return 0;
  865. }
  866. void __cpu_die(unsigned int cpu)
  867. {
  868. struct pcpu *pcpu;
  869. /* Wait until target cpu is down */
  870. pcpu = pcpu_devices + cpu;
  871. while (!pcpu_stopped(pcpu))
  872. cpu_relax();
  873. pcpu_free_lowcore(pcpu);
  874. cpumask_clear_cpu(cpu, mm_cpumask(&init_mm));
  875. cpumask_clear_cpu(cpu, &init_mm.context.cpu_attach_mask);
  876. }
  877. void __noreturn cpu_die(void)
  878. {
  879. idle_task_exit();
  880. __bpon();
  881. pcpu_sigp_retry(pcpu_devices + smp_processor_id(), SIGP_STOP, 0);
  882. for (;;) ;
  883. }
  884. void __init smp_fill_possible_mask(void)
  885. {
  886. unsigned int possible, sclp_max, cpu;
  887. sclp_max = max(sclp.mtid, sclp.mtid_cp) + 1;
  888. sclp_max = min(smp_max_threads, sclp_max);
  889. sclp_max = (sclp.max_cores * sclp_max) ?: nr_cpu_ids;
  890. possible = setup_possible_cpus ?: nr_cpu_ids;
  891. possible = min(possible, sclp_max);
  892. for (cpu = 0; cpu < possible && cpu < nr_cpu_ids; cpu++)
  893. set_cpu_possible(cpu, true);
  894. }
  895. void __init smp_prepare_cpus(unsigned int max_cpus)
  896. {
  897. /* request the 0x1201 emergency signal external interrupt */
  898. if (register_external_irq(EXT_IRQ_EMERGENCY_SIG, do_ext_call_interrupt))
  899. panic("Couldn't request external interrupt 0x1201");
  900. /* request the 0x1202 external call external interrupt */
  901. if (register_external_irq(EXT_IRQ_EXTERNAL_CALL, do_ext_call_interrupt))
  902. panic("Couldn't request external interrupt 0x1202");
  903. }
  904. void __init smp_prepare_boot_cpu(void)
  905. {
  906. struct pcpu *pcpu = pcpu_devices;
  907. WARN_ON(!cpu_present(0) || !cpu_online(0));
  908. pcpu->state = CPU_STATE_CONFIGURED;
  909. S390_lowcore.percpu_offset = __per_cpu_offset[0];
  910. smp_cpu_set_polarization(0, POLARIZATION_UNKNOWN);
  911. }
  912. void __init smp_setup_processor_id(void)
  913. {
  914. pcpu_devices[0].address = stap();
  915. S390_lowcore.cpu_nr = 0;
  916. S390_lowcore.spinlock_lockval = arch_spin_lockval(0);
  917. S390_lowcore.spinlock_index = 0;
  918. }
  919. /*
  920. * the frequency of the profiling timer can be changed
  921. * by writing a multiplier value into /proc/profile.
  922. *
  923. * usually you want to run this on all CPUs ;)
  924. */
  925. int setup_profiling_timer(unsigned int multiplier)
  926. {
  927. return 0;
  928. }
  929. static ssize_t cpu_configure_show(struct device *dev,
  930. struct device_attribute *attr, char *buf)
  931. {
  932. ssize_t count;
  933. mutex_lock(&smp_cpu_state_mutex);
  934. count = sprintf(buf, "%d\n", pcpu_devices[dev->id].state);
  935. mutex_unlock(&smp_cpu_state_mutex);
  936. return count;
  937. }
  938. static ssize_t cpu_configure_store(struct device *dev,
  939. struct device_attribute *attr,
  940. const char *buf, size_t count)
  941. {
  942. struct pcpu *pcpu;
  943. int cpu, val, rc, i;
  944. char delim;
  945. if (sscanf(buf, "%d %c", &val, &delim) != 1)
  946. return -EINVAL;
  947. if (val != 0 && val != 1)
  948. return -EINVAL;
  949. cpus_read_lock();
  950. mutex_lock(&smp_cpu_state_mutex);
  951. rc = -EBUSY;
  952. /* disallow configuration changes of online cpus and cpu 0 */
  953. cpu = dev->id;
  954. cpu = smp_get_base_cpu(cpu);
  955. if (cpu == 0)
  956. goto out;
  957. for (i = 0; i <= smp_cpu_mtid; i++)
  958. if (cpu_online(cpu + i))
  959. goto out;
  960. pcpu = pcpu_devices + cpu;
  961. rc = 0;
  962. switch (val) {
  963. case 0:
  964. if (pcpu->state != CPU_STATE_CONFIGURED)
  965. break;
  966. rc = sclp_core_deconfigure(pcpu->address >> smp_cpu_mt_shift);
  967. if (rc)
  968. break;
  969. for (i = 0; i <= smp_cpu_mtid; i++) {
  970. if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i))
  971. continue;
  972. pcpu[i].state = CPU_STATE_STANDBY;
  973. smp_cpu_set_polarization(cpu + i,
  974. POLARIZATION_UNKNOWN);
  975. }
  976. topology_expect_change();
  977. break;
  978. case 1:
  979. if (pcpu->state != CPU_STATE_STANDBY)
  980. break;
  981. rc = sclp_core_configure(pcpu->address >> smp_cpu_mt_shift);
  982. if (rc)
  983. break;
  984. for (i = 0; i <= smp_cpu_mtid; i++) {
  985. if (cpu + i >= nr_cpu_ids || !cpu_present(cpu + i))
  986. continue;
  987. pcpu[i].state = CPU_STATE_CONFIGURED;
  988. smp_cpu_set_polarization(cpu + i,
  989. POLARIZATION_UNKNOWN);
  990. }
  991. topology_expect_change();
  992. break;
  993. default:
  994. break;
  995. }
  996. out:
  997. mutex_unlock(&smp_cpu_state_mutex);
  998. cpus_read_unlock();
  999. return rc ? rc : count;
  1000. }
  1001. static DEVICE_ATTR(configure, 0644, cpu_configure_show, cpu_configure_store);
  1002. static ssize_t show_cpu_address(struct device *dev,
  1003. struct device_attribute *attr, char *buf)
  1004. {
  1005. return sprintf(buf, "%d\n", pcpu_devices[dev->id].address);
  1006. }
  1007. static DEVICE_ATTR(address, 0444, show_cpu_address, NULL);
  1008. static struct attribute *cpu_common_attrs[] = {
  1009. &dev_attr_configure.attr,
  1010. &dev_attr_address.attr,
  1011. NULL,
  1012. };
  1013. static struct attribute_group cpu_common_attr_group = {
  1014. .attrs = cpu_common_attrs,
  1015. };
  1016. static struct attribute *cpu_online_attrs[] = {
  1017. &dev_attr_idle_count.attr,
  1018. &dev_attr_idle_time_us.attr,
  1019. NULL,
  1020. };
  1021. static struct attribute_group cpu_online_attr_group = {
  1022. .attrs = cpu_online_attrs,
  1023. };
  1024. static int smp_cpu_online(unsigned int cpu)
  1025. {
  1026. struct device *s = &per_cpu(cpu_device, cpu)->dev;
  1027. return sysfs_create_group(&s->kobj, &cpu_online_attr_group);
  1028. }
  1029. static int smp_cpu_pre_down(unsigned int cpu)
  1030. {
  1031. struct device *s = &per_cpu(cpu_device, cpu)->dev;
  1032. sysfs_remove_group(&s->kobj, &cpu_online_attr_group);
  1033. return 0;
  1034. }
  1035. static int smp_add_present_cpu(int cpu)
  1036. {
  1037. struct device *s;
  1038. struct cpu *c;
  1039. int rc;
  1040. c = kzalloc(sizeof(*c), GFP_KERNEL);
  1041. if (!c)
  1042. return -ENOMEM;
  1043. per_cpu(cpu_device, cpu) = c;
  1044. s = &c->dev;
  1045. c->hotpluggable = 1;
  1046. rc = register_cpu(c, cpu);
  1047. if (rc)
  1048. goto out;
  1049. rc = sysfs_create_group(&s->kobj, &cpu_common_attr_group);
  1050. if (rc)
  1051. goto out_cpu;
  1052. rc = topology_cpu_init(c);
  1053. if (rc)
  1054. goto out_topology;
  1055. return 0;
  1056. out_topology:
  1057. sysfs_remove_group(&s->kobj, &cpu_common_attr_group);
  1058. out_cpu:
  1059. unregister_cpu(c);
  1060. out:
  1061. return rc;
  1062. }
  1063. int __ref smp_rescan_cpus(void)
  1064. {
  1065. struct sclp_core_info *info;
  1066. int nr;
  1067. info = kzalloc(sizeof(*info), GFP_KERNEL);
  1068. if (!info)
  1069. return -ENOMEM;
  1070. smp_get_core_info(info, 0);
  1071. nr = __smp_rescan_cpus(info, false);
  1072. kfree(info);
  1073. if (nr)
  1074. topology_schedule_update();
  1075. return 0;
  1076. }
  1077. static ssize_t __ref rescan_store(struct device *dev,
  1078. struct device_attribute *attr,
  1079. const char *buf,
  1080. size_t count)
  1081. {
  1082. int rc;
  1083. rc = lock_device_hotplug_sysfs();
  1084. if (rc)
  1085. return rc;
  1086. rc = smp_rescan_cpus();
  1087. unlock_device_hotplug();
  1088. return rc ? rc : count;
  1089. }
  1090. static DEVICE_ATTR_WO(rescan);
  1091. static int __init s390_smp_init(void)
  1092. {
  1093. int cpu, rc = 0;
  1094. rc = device_create_file(cpu_subsys.dev_root, &dev_attr_rescan);
  1095. if (rc)
  1096. return rc;
  1097. for_each_present_cpu(cpu) {
  1098. rc = smp_add_present_cpu(cpu);
  1099. if (rc)
  1100. goto out;
  1101. }
  1102. rc = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "s390/smp:online",
  1103. smp_cpu_online, smp_cpu_pre_down);
  1104. rc = rc <= 0 ? rc : 0;
  1105. out:
  1106. return rc;
  1107. }
  1108. subsys_initcall(s390_smp_init);
  1109. static __always_inline void set_new_lowcore(struct lowcore *lc)
  1110. {
  1111. union register_pair dst, src;
  1112. u32 pfx;
  1113. src.even = (unsigned long) &S390_lowcore;
  1114. src.odd = sizeof(S390_lowcore);
  1115. dst.even = (unsigned long) lc;
  1116. dst.odd = sizeof(*lc);
  1117. pfx = __pa(lc);
  1118. asm volatile(
  1119. " mvcl %[dst],%[src]\n"
  1120. " spx %[pfx]\n"
  1121. : [dst] "+&d" (dst.pair), [src] "+&d" (src.pair)
  1122. : [pfx] "Q" (pfx)
  1123. : "memory", "cc");
  1124. }
  1125. int __init smp_reinit_ipl_cpu(void)
  1126. {
  1127. unsigned long async_stack, nodat_stack, mcck_stack;
  1128. struct lowcore *lc, *lc_ipl;
  1129. unsigned long flags, cr0;
  1130. u64 mcesad;
  1131. lc_ipl = lowcore_ptr[0];
  1132. lc = (struct lowcore *) __get_free_pages(GFP_KERNEL | GFP_DMA, LC_ORDER);
  1133. nodat_stack = __get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER);
  1134. async_stack = stack_alloc();
  1135. mcck_stack = stack_alloc();
  1136. if (!lc || !nodat_stack || !async_stack || !mcck_stack || nmi_alloc_mcesa(&mcesad))
  1137. panic("Couldn't allocate memory");
  1138. local_irq_save(flags);
  1139. local_mcck_disable();
  1140. set_new_lowcore(lc);
  1141. S390_lowcore.nodat_stack = nodat_stack + STACK_INIT_OFFSET;
  1142. S390_lowcore.async_stack = async_stack + STACK_INIT_OFFSET;
  1143. S390_lowcore.mcck_stack = mcck_stack + STACK_INIT_OFFSET;
  1144. __ctl_store(cr0, 0, 0);
  1145. __ctl_clear_bit(0, 28); /* disable lowcore protection */
  1146. S390_lowcore.mcesad = mcesad;
  1147. __ctl_load(cr0, 0, 0);
  1148. if (abs_lowcore_map(0, lc, false))
  1149. panic("Couldn't remap absolute lowcore");
  1150. lowcore_ptr[0] = lc;
  1151. local_mcck_enable();
  1152. local_irq_restore(flags);
  1153. free_pages(lc_ipl->async_stack - STACK_INIT_OFFSET, THREAD_SIZE_ORDER);
  1154. memblock_free_late(__pa(lc_ipl->mcck_stack - STACK_INIT_OFFSET), THREAD_SIZE);
  1155. memblock_free_late(__pa(lc_ipl), sizeof(*lc_ipl));
  1156. return 0;
  1157. }