ap.h 13 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Adjunct processor (AP) interfaces
  4. *
  5. * Copyright IBM Corp. 2017
  6. *
  7. * Author(s): Tony Krowiak <[email protected]>
  8. * Martin Schwidefsky <[email protected]>
  9. * Harald Freudenberger <[email protected]>
  10. */
  11. #ifndef _ASM_S390_AP_H_
  12. #define _ASM_S390_AP_H_
  13. #include <linux/io.h>
  14. #include <asm/asm-extable.h>
  15. /**
  16. * The ap_qid_t identifier of an ap queue.
  17. * If the AP facilities test (APFT) facility is available,
  18. * card and queue index are 8 bit values, otherwise
  19. * card index is 6 bit and queue index a 4 bit value.
  20. */
  21. typedef unsigned int ap_qid_t;
  22. #define AP_MKQID(_card, _queue) (((_card) & 0xff) << 8 | ((_queue) & 0xff))
  23. #define AP_QID_CARD(_qid) (((_qid) >> 8) & 0xff)
  24. #define AP_QID_QUEUE(_qid) ((_qid) & 0xff)
  25. /**
  26. * struct ap_queue_status - Holds the AP queue status.
  27. * @queue_empty: Shows if queue is empty
  28. * @replies_waiting: Waiting replies
  29. * @queue_full: Is 1 if the queue is full
  30. * @irq_enabled: Shows if interrupts are enabled for the AP
  31. * @response_code: Holds the 8 bit response code
  32. *
  33. * The ap queue status word is returned by all three AP functions
  34. * (PQAP, NQAP and DQAP). There's a set of flags in the first
  35. * byte, followed by a 1 byte response code.
  36. */
  37. struct ap_queue_status {
  38. unsigned int queue_empty : 1;
  39. unsigned int replies_waiting : 1;
  40. unsigned int queue_full : 1;
  41. unsigned int _pad1 : 4;
  42. unsigned int irq_enabled : 1;
  43. unsigned int response_code : 8;
  44. unsigned int _pad2 : 16;
  45. };
  46. /**
  47. * ap_intructions_available() - Test if AP instructions are available.
  48. *
  49. * Returns true if the AP instructions are installed, otherwise false.
  50. */
  51. static inline bool ap_instructions_available(void)
  52. {
  53. unsigned long reg0 = AP_MKQID(0, 0);
  54. unsigned long reg1 = 0;
  55. asm volatile(
  56. " lgr 0,%[reg0]\n" /* qid into gr0 */
  57. " lghi 1,0\n" /* 0 into gr1 */
  58. " lghi 2,0\n" /* 0 into gr2 */
  59. " .insn rre,0xb2af0000,0,0\n" /* PQAP(TAPQ) */
  60. "0: la %[reg1],1\n" /* 1 into reg1 */
  61. "1:\n"
  62. EX_TABLE(0b, 1b)
  63. : [reg1] "+&d" (reg1)
  64. : [reg0] "d" (reg0)
  65. : "cc", "0", "1", "2");
  66. return reg1 != 0;
  67. }
  68. /**
  69. * ap_tapq(): Test adjunct processor queue.
  70. * @qid: The AP queue number
  71. * @info: Pointer to queue descriptor
  72. *
  73. * Returns AP queue status structure.
  74. */
  75. static inline struct ap_queue_status ap_tapq(ap_qid_t qid, unsigned long *info)
  76. {
  77. struct ap_queue_status reg1;
  78. unsigned long reg2;
  79. asm volatile(
  80. " lgr 0,%[qid]\n" /* qid into gr0 */
  81. " lghi 2,0\n" /* 0 into gr2 */
  82. " .insn rre,0xb2af0000,0,0\n" /* PQAP(TAPQ) */
  83. " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
  84. " lgr %[reg2],2\n" /* gr2 into reg2 */
  85. : [reg1] "=&d" (reg1), [reg2] "=&d" (reg2)
  86. : [qid] "d" (qid)
  87. : "cc", "0", "1", "2");
  88. if (info)
  89. *info = reg2;
  90. return reg1;
  91. }
  92. /**
  93. * ap_test_queue(): Test adjunct processor queue.
  94. * @qid: The AP queue number
  95. * @tbit: Test facilities bit
  96. * @info: Pointer to queue descriptor
  97. *
  98. * Returns AP queue status structure.
  99. */
  100. static inline struct ap_queue_status ap_test_queue(ap_qid_t qid,
  101. int tbit,
  102. unsigned long *info)
  103. {
  104. if (tbit)
  105. qid |= 1UL << 23; /* set T bit*/
  106. return ap_tapq(qid, info);
  107. }
  108. /**
  109. * ap_pqap_rapq(): Reset adjunct processor queue.
  110. * @qid: The AP queue number
  111. *
  112. * Returns AP queue status structure.
  113. */
  114. static inline struct ap_queue_status ap_rapq(ap_qid_t qid)
  115. {
  116. unsigned long reg0 = qid | (1UL << 24); /* fc 1UL is RAPQ */
  117. struct ap_queue_status reg1;
  118. asm volatile(
  119. " lgr 0,%[reg0]\n" /* qid arg into gr0 */
  120. " .insn rre,0xb2af0000,0,0\n" /* PQAP(RAPQ) */
  121. " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
  122. : [reg1] "=&d" (reg1)
  123. : [reg0] "d" (reg0)
  124. : "cc", "0", "1");
  125. return reg1;
  126. }
  127. /**
  128. * ap_pqap_zapq(): Reset and zeroize adjunct processor queue.
  129. * @qid: The AP queue number
  130. *
  131. * Returns AP queue status structure.
  132. */
  133. static inline struct ap_queue_status ap_zapq(ap_qid_t qid)
  134. {
  135. unsigned long reg0 = qid | (2UL << 24); /* fc 2UL is ZAPQ */
  136. struct ap_queue_status reg1;
  137. asm volatile(
  138. " lgr 0,%[reg0]\n" /* qid arg into gr0 */
  139. " .insn rre,0xb2af0000,0,0\n" /* PQAP(ZAPQ) */
  140. " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
  141. : [reg1] "=&d" (reg1)
  142. : [reg0] "d" (reg0)
  143. : "cc", "0", "1");
  144. return reg1;
  145. }
  146. /**
  147. * struct ap_config_info - convenience struct for AP crypto
  148. * config info as returned by the ap_qci() function.
  149. */
  150. struct ap_config_info {
  151. unsigned int apsc : 1; /* S bit */
  152. unsigned int apxa : 1; /* N bit */
  153. unsigned int qact : 1; /* C bit */
  154. unsigned int rc8a : 1; /* R bit */
  155. unsigned char _reserved1 : 4;
  156. unsigned char _reserved2[3];
  157. unsigned char Na; /* max # of APs - 1 */
  158. unsigned char Nd; /* max # of Domains - 1 */
  159. unsigned char _reserved3[10];
  160. unsigned int apm[8]; /* AP ID mask */
  161. unsigned int aqm[8]; /* AP (usage) queue mask */
  162. unsigned int adm[8]; /* AP (control) domain mask */
  163. unsigned char _reserved4[16];
  164. } __aligned(8);
  165. /**
  166. * ap_qci(): Get AP configuration data
  167. *
  168. * Returns 0 on success, or -EOPNOTSUPP.
  169. */
  170. static inline int ap_qci(struct ap_config_info *config)
  171. {
  172. unsigned long reg0 = 4UL << 24; /* fc 4UL is QCI */
  173. unsigned long reg1 = -EOPNOTSUPP;
  174. struct ap_config_info *reg2 = config;
  175. asm volatile(
  176. " lgr 0,%[reg0]\n" /* QCI fc into gr0 */
  177. " lgr 2,%[reg2]\n" /* ptr to config into gr2 */
  178. " .insn rre,0xb2af0000,0,0\n" /* PQAP(QCI) */
  179. "0: la %[reg1],0\n" /* good case, QCI fc available */
  180. "1:\n"
  181. EX_TABLE(0b, 1b)
  182. : [reg1] "+&d" (reg1)
  183. : [reg0] "d" (reg0), [reg2] "d" (reg2)
  184. : "cc", "memory", "0", "2");
  185. return reg1;
  186. }
  187. /*
  188. * struct ap_qirq_ctrl - convenient struct for easy invocation
  189. * of the ap_aqic() function. This struct is passed as GR1
  190. * parameter to the PQAP(AQIC) instruction. For details please
  191. * see the AR documentation.
  192. */
  193. struct ap_qirq_ctrl {
  194. unsigned int _res1 : 8;
  195. unsigned int zone : 8; /* zone info */
  196. unsigned int ir : 1; /* ir flag: enable (1) or disable (0) irq */
  197. unsigned int _res2 : 4;
  198. unsigned int gisc : 3; /* guest isc field */
  199. unsigned int _res3 : 6;
  200. unsigned int gf : 2; /* gisa format */
  201. unsigned int _res4 : 1;
  202. unsigned int gisa : 27; /* gisa origin */
  203. unsigned int _res5 : 1;
  204. unsigned int isc : 3; /* irq sub class */
  205. };
  206. /**
  207. * ap_aqic(): Control interruption for a specific AP.
  208. * @qid: The AP queue number
  209. * @qirqctrl: struct ap_qirq_ctrl (64 bit value)
  210. * @pa_ind: Physical address of the notification indicator byte
  211. *
  212. * Returns AP queue status.
  213. */
  214. static inline struct ap_queue_status ap_aqic(ap_qid_t qid,
  215. struct ap_qirq_ctrl qirqctrl,
  216. phys_addr_t pa_ind)
  217. {
  218. unsigned long reg0 = qid | (3UL << 24); /* fc 3UL is AQIC */
  219. union {
  220. unsigned long value;
  221. struct ap_qirq_ctrl qirqctrl;
  222. struct {
  223. u32 _pad;
  224. struct ap_queue_status status;
  225. };
  226. } reg1;
  227. unsigned long reg2 = pa_ind;
  228. reg1.qirqctrl = qirqctrl;
  229. asm volatile(
  230. " lgr 0,%[reg0]\n" /* qid param into gr0 */
  231. " lgr 1,%[reg1]\n" /* irq ctrl into gr1 */
  232. " lgr 2,%[reg2]\n" /* ni addr into gr2 */
  233. " .insn rre,0xb2af0000,0,0\n" /* PQAP(AQIC) */
  234. " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
  235. : [reg1] "+&d" (reg1)
  236. : [reg0] "d" (reg0), [reg2] "d" (reg2)
  237. : "cc", "memory", "0", "1", "2");
  238. return reg1.status;
  239. }
  240. /*
  241. * union ap_qact_ap_info - used together with the
  242. * ap_aqic() function to provide a convenient way
  243. * to handle the ap info needed by the qact function.
  244. */
  245. union ap_qact_ap_info {
  246. unsigned long val;
  247. struct {
  248. unsigned int : 3;
  249. unsigned int mode : 3;
  250. unsigned int : 26;
  251. unsigned int cat : 8;
  252. unsigned int : 8;
  253. unsigned char ver[2];
  254. };
  255. };
  256. /**
  257. * ap_qact(): Query AP combatibility type.
  258. * @qid: The AP queue number
  259. * @apinfo: On input the info about the AP queue. On output the
  260. * alternate AP queue info provided by the qact function
  261. * in GR2 is stored in.
  262. *
  263. * Returns AP queue status. Check response_code field for failures.
  264. */
  265. static inline struct ap_queue_status ap_qact(ap_qid_t qid, int ifbit,
  266. union ap_qact_ap_info *apinfo)
  267. {
  268. unsigned long reg0 = qid | (5UL << 24) | ((ifbit & 0x01) << 22);
  269. union {
  270. unsigned long value;
  271. struct {
  272. u32 _pad;
  273. struct ap_queue_status status;
  274. };
  275. } reg1;
  276. unsigned long reg2;
  277. reg1.value = apinfo->val;
  278. asm volatile(
  279. " lgr 0,%[reg0]\n" /* qid param into gr0 */
  280. " lgr 1,%[reg1]\n" /* qact in info into gr1 */
  281. " .insn rre,0xb2af0000,0,0\n" /* PQAP(QACT) */
  282. " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
  283. " lgr %[reg2],2\n" /* qact out info into reg2 */
  284. : [reg1] "+&d" (reg1), [reg2] "=&d" (reg2)
  285. : [reg0] "d" (reg0)
  286. : "cc", "0", "1", "2");
  287. apinfo->val = reg2;
  288. return reg1.status;
  289. }
  290. /**
  291. * ap_nqap(): Send message to adjunct processor queue.
  292. * @qid: The AP queue number
  293. * @psmid: The program supplied message identifier
  294. * @msg: The message text
  295. * @length: The message length
  296. *
  297. * Returns AP queue status structure.
  298. * Condition code 1 on NQAP can't happen because the L bit is 1.
  299. * Condition code 2 on NQAP also means the send is incomplete,
  300. * because a segment boundary was reached. The NQAP is repeated.
  301. */
  302. static inline struct ap_queue_status ap_nqap(ap_qid_t qid,
  303. unsigned long long psmid,
  304. void *msg, size_t length)
  305. {
  306. unsigned long reg0 = qid | 0x40000000UL; /* 0x4... is last msg part */
  307. union register_pair nqap_r1, nqap_r2;
  308. struct ap_queue_status reg1;
  309. nqap_r1.even = (unsigned int)(psmid >> 32);
  310. nqap_r1.odd = psmid & 0xffffffff;
  311. nqap_r2.even = (unsigned long)msg;
  312. nqap_r2.odd = (unsigned long)length;
  313. asm volatile (
  314. " lgr 0,%[reg0]\n" /* qid param in gr0 */
  315. "0: .insn rre,0xb2ad0000,%[nqap_r1],%[nqap_r2]\n"
  316. " brc 2,0b\n" /* handle partial completion */
  317. " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
  318. : [reg0] "+&d" (reg0), [reg1] "=&d" (reg1),
  319. [nqap_r2] "+&d" (nqap_r2.pair)
  320. : [nqap_r1] "d" (nqap_r1.pair)
  321. : "cc", "memory", "0", "1");
  322. return reg1;
  323. }
  324. /**
  325. * ap_dqap(): Receive message from adjunct processor queue.
  326. * @qid: The AP queue number
  327. * @psmid: Pointer to program supplied message identifier
  328. * @msg: The message text
  329. * @length: The message length
  330. * @reslength: Resitual length on return
  331. * @resgr0: input: gr0 value (only used if != 0), output: resitual gr0 content
  332. *
  333. * Returns AP queue status structure.
  334. * Condition code 1 on DQAP means the receive has taken place
  335. * but only partially. The response is incomplete, hence the
  336. * DQAP is repeated.
  337. * Condition code 2 on DQAP also means the receive is incomplete,
  338. * this time because a segment boundary was reached. Again, the
  339. * DQAP is repeated.
  340. * Note that gpr2 is used by the DQAP instruction to keep track of
  341. * any 'residual' length, in case the instruction gets interrupted.
  342. * Hence it gets zeroed before the instruction.
  343. * If the message does not fit into the buffer, this function will
  344. * return with a truncated message and the reply in the firmware queue
  345. * is not removed. This is indicated to the caller with an
  346. * ap_queue_status response_code value of all bits on (0xFF) and (if
  347. * the reslength ptr is given) the remaining length is stored in
  348. * *reslength and (if the resgr0 ptr is given) the updated gr0 value
  349. * for further processing of this msg entry is stored in *resgr0. The
  350. * caller needs to detect this situation and should invoke ap_dqap
  351. * with a valid resgr0 ptr and a value in there != 0 to indicate that
  352. * *resgr0 is to be used instead of qid to further process this entry.
  353. */
  354. static inline struct ap_queue_status ap_dqap(ap_qid_t qid,
  355. unsigned long long *psmid,
  356. void *msg, size_t length,
  357. size_t *reslength,
  358. unsigned long *resgr0)
  359. {
  360. unsigned long reg0 = resgr0 && *resgr0 ? *resgr0 : qid | 0x80000000UL;
  361. struct ap_queue_status reg1;
  362. unsigned long reg2;
  363. union register_pair rp1, rp2;
  364. rp1.even = 0UL;
  365. rp1.odd = 0UL;
  366. rp2.even = (unsigned long)msg;
  367. rp2.odd = (unsigned long)length;
  368. asm volatile(
  369. " lgr 0,%[reg0]\n" /* qid param into gr0 */
  370. " lghi 2,0\n" /* 0 into gr2 (res length) */
  371. "0: ltgr %N[rp2],%N[rp2]\n" /* check buf len */
  372. " jz 2f\n" /* go out if buf len is 0 */
  373. "1: .insn rre,0xb2ae0000,%[rp1],%[rp2]\n"
  374. " brc 6,0b\n" /* handle partial complete */
  375. "2: lgr %[reg0],0\n" /* gr0 (qid + info) into reg0 */
  376. " lgr %[reg1],1\n" /* gr1 (status) into reg1 */
  377. " lgr %[reg2],2\n" /* gr2 (res length) into reg2 */
  378. : [reg0] "+&d" (reg0), [reg1] "=&d" (reg1), [reg2] "=&d" (reg2),
  379. [rp1] "+&d" (rp1.pair), [rp2] "+&d" (rp2.pair)
  380. :
  381. : "cc", "memory", "0", "1", "2");
  382. if (reslength)
  383. *reslength = reg2;
  384. if (reg2 != 0 && rp2.odd == 0) {
  385. /*
  386. * Partially complete, status in gr1 is not set.
  387. * Signal the caller that this dqap is only partially received
  388. * with a special status response code 0xFF and *resgr0 updated
  389. */
  390. reg1.response_code = 0xFF;
  391. if (resgr0)
  392. *resgr0 = reg0;
  393. } else {
  394. *psmid = (((unsigned long long)rp1.even) << 32) + rp1.odd;
  395. if (resgr0)
  396. *resgr0 = 0;
  397. }
  398. return reg1;
  399. }
  400. /*
  401. * Interface to tell the AP bus code that a configuration
  402. * change has happened. The bus code should at least do
  403. * an ap bus resource rescan.
  404. */
  405. #if IS_ENABLED(CONFIG_ZCRYPT)
  406. void ap_bus_cfg_chg(void);
  407. #else
  408. static inline void ap_bus_cfg_chg(void){}
  409. #endif
  410. #endif /* _ASM_S390_AP_H_ */