ip22-int.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * ip22-int.c: Routines for generic manipulation of the INT[23] ASIC
  4. * found on INDY and Indigo2 workstations.
  5. *
  6. * Copyright (C) 1996 David S. Miller ([email protected])
  7. * Copyright (C) 1997, 1998 Ralf Baechle ([email protected])
  8. * Copyright (C) 1999 Andrew R. Baker ([email protected])
  9. * - Indigo2 changes
  10. * - Interrupt handling fixes
  11. * Copyright (C) 2001, 2003 Ladislav Michl ([email protected])
  12. */
  13. #include <linux/types.h>
  14. #include <linux/init.h>
  15. #include <linux/kernel_stat.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/ftrace.h>
  18. #include <asm/irq_cpu.h>
  19. #include <asm/sgi/hpc3.h>
  20. #include <asm/sgi/ip22.h>
  21. /* So far nothing hangs here */
  22. #undef USE_LIO3_IRQ
  23. struct sgint_regs *sgint;
  24. static char lc0msk_to_irqnr[256];
  25. static char lc1msk_to_irqnr[256];
  26. static char lc2msk_to_irqnr[256];
  27. static char lc3msk_to_irqnr[256];
  28. extern int ip22_eisa_init(void);
  29. static void enable_local0_irq(struct irq_data *d)
  30. {
  31. /* don't allow mappable interrupt to be enabled from setup_irq,
  32. * we have our own way to do so */
  33. if (d->irq != SGI_MAP_0_IRQ)
  34. sgint->imask0 |= (1 << (d->irq - SGINT_LOCAL0));
  35. }
  36. static void disable_local0_irq(struct irq_data *d)
  37. {
  38. sgint->imask0 &= ~(1 << (d->irq - SGINT_LOCAL0));
  39. }
  40. static struct irq_chip ip22_local0_irq_type = {
  41. .name = "IP22 local 0",
  42. .irq_mask = disable_local0_irq,
  43. .irq_unmask = enable_local0_irq,
  44. };
  45. static void enable_local1_irq(struct irq_data *d)
  46. {
  47. /* don't allow mappable interrupt to be enabled from setup_irq,
  48. * we have our own way to do so */
  49. if (d->irq != SGI_MAP_1_IRQ)
  50. sgint->imask1 |= (1 << (d->irq - SGINT_LOCAL1));
  51. }
  52. static void disable_local1_irq(struct irq_data *d)
  53. {
  54. sgint->imask1 &= ~(1 << (d->irq - SGINT_LOCAL1));
  55. }
  56. static struct irq_chip ip22_local1_irq_type = {
  57. .name = "IP22 local 1",
  58. .irq_mask = disable_local1_irq,
  59. .irq_unmask = enable_local1_irq,
  60. };
  61. static void enable_local2_irq(struct irq_data *d)
  62. {
  63. sgint->imask0 |= (1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
  64. sgint->cmeimask0 |= (1 << (d->irq - SGINT_LOCAL2));
  65. }
  66. static void disable_local2_irq(struct irq_data *d)
  67. {
  68. sgint->cmeimask0 &= ~(1 << (d->irq - SGINT_LOCAL2));
  69. if (!sgint->cmeimask0)
  70. sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
  71. }
  72. static struct irq_chip ip22_local2_irq_type = {
  73. .name = "IP22 local 2",
  74. .irq_mask = disable_local2_irq,
  75. .irq_unmask = enable_local2_irq,
  76. };
  77. static void enable_local3_irq(struct irq_data *d)
  78. {
  79. sgint->imask1 |= (1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
  80. sgint->cmeimask1 |= (1 << (d->irq - SGINT_LOCAL3));
  81. }
  82. static void disable_local3_irq(struct irq_data *d)
  83. {
  84. sgint->cmeimask1 &= ~(1 << (d->irq - SGINT_LOCAL3));
  85. if (!sgint->cmeimask1)
  86. sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
  87. }
  88. static struct irq_chip ip22_local3_irq_type = {
  89. .name = "IP22 local 3",
  90. .irq_mask = disable_local3_irq,
  91. .irq_unmask = enable_local3_irq,
  92. };
  93. static void indy_local0_irqdispatch(void)
  94. {
  95. u8 mask = sgint->istat0 & sgint->imask0;
  96. u8 mask2;
  97. int irq;
  98. if (mask & SGINT_ISTAT0_LIO2) {
  99. mask2 = sgint->vmeistat & sgint->cmeimask0;
  100. irq = lc2msk_to_irqnr[mask2];
  101. } else
  102. irq = lc0msk_to_irqnr[mask];
  103. /*
  104. * workaround for INT2 bug; if irq == 0, INT2 has seen a fifo full
  105. * irq, but failed to latch it into status register
  106. */
  107. if (irq)
  108. do_IRQ(irq);
  109. else
  110. do_IRQ(SGINT_LOCAL0 + 0);
  111. }
  112. static void indy_local1_irqdispatch(void)
  113. {
  114. u8 mask = sgint->istat1 & sgint->imask1;
  115. u8 mask2;
  116. int irq;
  117. if (mask & SGINT_ISTAT1_LIO3) {
  118. mask2 = sgint->vmeistat & sgint->cmeimask1;
  119. irq = lc3msk_to_irqnr[mask2];
  120. } else
  121. irq = lc1msk_to_irqnr[mask];
  122. /* if irq == 0, then the interrupt has already been cleared */
  123. if (irq)
  124. do_IRQ(irq);
  125. }
  126. extern void ip22_be_interrupt(int irq);
  127. static void __irq_entry indy_buserror_irq(void)
  128. {
  129. int irq = SGI_BUSERR_IRQ;
  130. irq_enter();
  131. kstat_incr_irq_this_cpu(irq);
  132. ip22_be_interrupt(irq);
  133. irq_exit();
  134. }
  135. #ifdef USE_LIO3_IRQ
  136. #define SGI_INTERRUPTS SGINT_END
  137. #else
  138. #define SGI_INTERRUPTS SGINT_LOCAL3
  139. #endif
  140. extern void indy_8254timer_irq(void);
  141. /*
  142. * IRQs on the INDY look basically (barring software IRQs which we don't use
  143. * at all) like:
  144. *
  145. * MIPS IRQ Source
  146. * -------- ------
  147. * 0 Software (ignored)
  148. * 1 Software (ignored)
  149. * 2 Local IRQ level zero
  150. * 3 Local IRQ level one
  151. * 4 8254 Timer zero
  152. * 5 8254 Timer one
  153. * 6 Bus Error
  154. * 7 R4k timer (what we use)
  155. *
  156. * We handle the IRQ according to _our_ priority which is:
  157. *
  158. * Highest ---- R4k Timer
  159. * Local IRQ zero
  160. * Local IRQ one
  161. * Bus Error
  162. * 8254 Timer zero
  163. * Lowest ---- 8254 Timer one
  164. *
  165. * then we just return, if multiple IRQs are pending then we will just take
  166. * another exception, big deal.
  167. */
  168. asmlinkage void plat_irq_dispatch(void)
  169. {
  170. unsigned int pending = read_c0_status() & read_c0_cause();
  171. /*
  172. * First we check for r4k counter/timer IRQ.
  173. */
  174. if (pending & CAUSEF_IP7)
  175. do_IRQ(SGI_TIMER_IRQ);
  176. else if (pending & CAUSEF_IP2)
  177. indy_local0_irqdispatch();
  178. else if (pending & CAUSEF_IP3)
  179. indy_local1_irqdispatch();
  180. else if (pending & CAUSEF_IP6)
  181. indy_buserror_irq();
  182. else if (pending & (CAUSEF_IP4 | CAUSEF_IP5))
  183. indy_8254timer_irq();
  184. }
  185. void __init arch_init_irq(void)
  186. {
  187. int i;
  188. /* Init local mask --> irq tables. */
  189. for (i = 0; i < 256; i++) {
  190. if (i & 0x80) {
  191. lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 7;
  192. lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 7;
  193. lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 7;
  194. lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 7;
  195. } else if (i & 0x40) {
  196. lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 6;
  197. lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 6;
  198. lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 6;
  199. lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 6;
  200. } else if (i & 0x20) {
  201. lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 5;
  202. lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 5;
  203. lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 5;
  204. lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 5;
  205. } else if (i & 0x10) {
  206. lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 4;
  207. lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 4;
  208. lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 4;
  209. lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 4;
  210. } else if (i & 0x08) {
  211. lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 3;
  212. lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 3;
  213. lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 3;
  214. lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 3;
  215. } else if (i & 0x04) {
  216. lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 2;
  217. lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 2;
  218. lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 2;
  219. lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 2;
  220. } else if (i & 0x02) {
  221. lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 1;
  222. lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 1;
  223. lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 1;
  224. lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 1;
  225. } else if (i & 0x01) {
  226. lc0msk_to_irqnr[i] = SGINT_LOCAL0 + 0;
  227. lc1msk_to_irqnr[i] = SGINT_LOCAL1 + 0;
  228. lc2msk_to_irqnr[i] = SGINT_LOCAL2 + 0;
  229. lc3msk_to_irqnr[i] = SGINT_LOCAL3 + 0;
  230. } else {
  231. lc0msk_to_irqnr[i] = 0;
  232. lc1msk_to_irqnr[i] = 0;
  233. lc2msk_to_irqnr[i] = 0;
  234. lc3msk_to_irqnr[i] = 0;
  235. }
  236. }
  237. /* Mask out all interrupts. */
  238. sgint->imask0 = 0;
  239. sgint->imask1 = 0;
  240. sgint->cmeimask0 = 0;
  241. sgint->cmeimask1 = 0;
  242. /* init CPU irqs */
  243. mips_cpu_irq_init();
  244. for (i = SGINT_LOCAL0; i < SGI_INTERRUPTS; i++) {
  245. struct irq_chip *handler;
  246. if (i < SGINT_LOCAL1)
  247. handler = &ip22_local0_irq_type;
  248. else if (i < SGINT_LOCAL2)
  249. handler = &ip22_local1_irq_type;
  250. else if (i < SGINT_LOCAL3)
  251. handler = &ip22_local2_irq_type;
  252. else
  253. handler = &ip22_local3_irq_type;
  254. irq_set_chip_and_handler(i, handler, handle_level_irq);
  255. }
  256. /* vector handler. this register the IRQ as non-sharable */
  257. if (request_irq(SGI_LOCAL_0_IRQ, no_action, IRQF_NO_THREAD,
  258. "local0 cascade", NULL))
  259. pr_err("Failed to register local0 cascade interrupt\n");
  260. if (request_irq(SGI_LOCAL_1_IRQ, no_action, IRQF_NO_THREAD,
  261. "local1 cascade", NULL))
  262. pr_err("Failed to register local1 cascade interrupt\n");
  263. if (request_irq(SGI_BUSERR_IRQ, no_action, IRQF_NO_THREAD,
  264. "Bus Error", NULL))
  265. pr_err("Failed to register Bus Error interrupt\n");
  266. /* cascade in cascade. i love Indy ;-) */
  267. if (request_irq(SGI_MAP_0_IRQ, no_action, IRQF_NO_THREAD,
  268. "mapable0 cascade", NULL))
  269. pr_err("Failed to register mapable0 cascade interrupt\n");
  270. #ifdef USE_LIO3_IRQ
  271. if (request_irq(SGI_MAP_1_IRQ, no_action, IRQF_NO_THREAD,
  272. "mapable1 cascade", NULL))
  273. pr_err("Failed to register mapable1 cascade interrupt\n");
  274. #endif
  275. #ifdef CONFIG_EISA
  276. if (ip22_is_fullhouse()) /* Only Indigo-2 has EISA stuff */
  277. ip22_eisa_init();
  278. #endif
  279. }