devices.c 6.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * RouterBoard 500 Platform devices
  4. *
  5. * Copyright (C) 2006 Felix Fietkau <[email protected]>
  6. * Copyright (C) 2007 Florian Fainelli <[email protected]>
  7. */
  8. #include <linux/kernel.h>
  9. #include <linux/export.h>
  10. #include <linux/init.h>
  11. #include <linux/ctype.h>
  12. #include <linux/string.h>
  13. #include <linux/platform_device.h>
  14. #include <linux/mtd/platnand.h>
  15. #include <linux/mtd/mtd.h>
  16. #include <linux/gpio.h>
  17. #include <linux/gpio/machine.h>
  18. #include <linux/gpio_keys.h>
  19. #include <linux/input.h>
  20. #include <linux/serial_8250.h>
  21. #include <asm/bootinfo.h>
  22. #include <asm/mach-rc32434/rc32434.h>
  23. #include <asm/mach-rc32434/dma.h>
  24. #include <asm/mach-rc32434/dma_v.h>
  25. #include <asm/mach-rc32434/eth.h>
  26. #include <asm/mach-rc32434/rb.h>
  27. #include <asm/mach-rc32434/integ.h>
  28. #include <asm/mach-rc32434/gpio.h>
  29. #include <asm/mach-rc32434/irq.h>
  30. #define ETH0_RX_DMA_ADDR (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET)
  31. #define ETH0_TX_DMA_ADDR (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET)
  32. extern unsigned int idt_cpu_freq;
  33. static struct mpmc_device dev3;
  34. void set_latch_u5(unsigned char or_mask, unsigned char nand_mask)
  35. {
  36. unsigned long flags;
  37. spin_lock_irqsave(&dev3.lock, flags);
  38. dev3.state = (dev3.state | or_mask) & ~nand_mask;
  39. writeb(dev3.state, dev3.base);
  40. spin_unlock_irqrestore(&dev3.lock, flags);
  41. }
  42. EXPORT_SYMBOL(set_latch_u5);
  43. unsigned char get_latch_u5(void)
  44. {
  45. return dev3.state;
  46. }
  47. EXPORT_SYMBOL(get_latch_u5);
  48. static struct resource korina_dev0_res[] = {
  49. {
  50. .name = "emac",
  51. .start = ETH0_BASE_ADDR,
  52. .end = ETH0_BASE_ADDR + sizeof(struct eth_regs),
  53. .flags = IORESOURCE_MEM,
  54. }, {
  55. .name = "rx",
  56. .start = ETH0_DMA_RX_IRQ,
  57. .end = ETH0_DMA_RX_IRQ,
  58. .flags = IORESOURCE_IRQ
  59. }, {
  60. .name = "tx",
  61. .start = ETH0_DMA_TX_IRQ,
  62. .end = ETH0_DMA_TX_IRQ,
  63. .flags = IORESOURCE_IRQ
  64. }, {
  65. .name = "dma_rx",
  66. .start = ETH0_RX_DMA_ADDR,
  67. .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
  68. .flags = IORESOURCE_MEM,
  69. }, {
  70. .name = "dma_tx",
  71. .start = ETH0_TX_DMA_ADDR,
  72. .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
  73. .flags = IORESOURCE_MEM,
  74. }
  75. };
  76. static struct korina_device korina_dev0_data = {
  77. .name = "korina0",
  78. .mac = {0xde, 0xca, 0xff, 0xc0, 0xff, 0xee}
  79. };
  80. static struct platform_device korina_dev0 = {
  81. .id = -1,
  82. .name = "korina",
  83. .resource = korina_dev0_res,
  84. .num_resources = ARRAY_SIZE(korina_dev0_res),
  85. .dev = {
  86. .platform_data = &korina_dev0_data.mac,
  87. }
  88. };
  89. static struct resource cf_slot0_res[] = {
  90. {
  91. .name = "cf_membase",
  92. .flags = IORESOURCE_MEM
  93. }, {
  94. .name = "cf_irq",
  95. .start = (8 + 4 * 32 + CF_GPIO_NUM), /* 149 */
  96. .end = (8 + 4 * 32 + CF_GPIO_NUM),
  97. .flags = IORESOURCE_IRQ
  98. }
  99. };
  100. static struct gpiod_lookup_table cf_slot0_gpio_table = {
  101. .dev_id = "pata-rb532-cf",
  102. .table = {
  103. GPIO_LOOKUP("gpio0", CF_GPIO_NUM,
  104. NULL, GPIO_ACTIVE_HIGH),
  105. { },
  106. },
  107. };
  108. static struct platform_device cf_slot0 = {
  109. .id = -1,
  110. .name = "pata-rb532-cf",
  111. .resource = cf_slot0_res,
  112. .num_resources = ARRAY_SIZE(cf_slot0_res),
  113. };
  114. /* Resources and device for NAND */
  115. static int rb532_dev_ready(struct nand_chip *chip)
  116. {
  117. return gpio_get_value(GPIO_RDY);
  118. }
  119. static void rb532_cmd_ctrl(struct nand_chip *chip, int cmd, unsigned int ctrl)
  120. {
  121. unsigned char orbits, nandbits;
  122. if (ctrl & NAND_CTRL_CHANGE) {
  123. orbits = (ctrl & NAND_CLE) << 1;
  124. orbits |= (ctrl & NAND_ALE) >> 1;
  125. nandbits = (~ctrl & NAND_CLE) << 1;
  126. nandbits |= (~ctrl & NAND_ALE) >> 1;
  127. set_latch_u5(orbits, nandbits);
  128. }
  129. if (cmd != NAND_CMD_NONE)
  130. writeb(cmd, chip->legacy.IO_ADDR_W);
  131. }
  132. static struct resource nand_slot0_res[] = {
  133. [0] = {
  134. .name = "nand_membase",
  135. .flags = IORESOURCE_MEM
  136. }
  137. };
  138. static struct platform_nand_data rb532_nand_data = {
  139. .ctrl.dev_ready = rb532_dev_ready,
  140. .ctrl.cmd_ctrl = rb532_cmd_ctrl,
  141. };
  142. static struct platform_device nand_slot0 = {
  143. .name = "gen_nand",
  144. .id = -1,
  145. .resource = nand_slot0_res,
  146. .num_resources = ARRAY_SIZE(nand_slot0_res),
  147. .dev.platform_data = &rb532_nand_data,
  148. };
  149. static struct mtd_partition rb532_partition_info[] = {
  150. {
  151. .name = "Routerboard NAND boot",
  152. .offset = 0,
  153. .size = 4 * 1024 * 1024,
  154. }, {
  155. .name = "rootfs",
  156. .offset = MTDPART_OFS_NXTBLK,
  157. .size = MTDPART_SIZ_FULL,
  158. }
  159. };
  160. static struct platform_device rb532_led = {
  161. .name = "rb532-led",
  162. .id = -1,
  163. };
  164. static struct platform_device rb532_button = {
  165. .name = "rb532-button",
  166. .id = -1,
  167. };
  168. static struct resource rb532_wdt_res[] = {
  169. {
  170. .name = "rb532_wdt_res",
  171. .start = INTEG0_BASE_ADDR,
  172. .end = INTEG0_BASE_ADDR + sizeof(struct integ),
  173. .flags = IORESOURCE_MEM,
  174. }
  175. };
  176. static struct platform_device rb532_wdt = {
  177. .name = "rc32434_wdt",
  178. .id = -1,
  179. .resource = rb532_wdt_res,
  180. .num_resources = ARRAY_SIZE(rb532_wdt_res),
  181. };
  182. static struct plat_serial8250_port rb532_uart_res[] = {
  183. {
  184. .type = PORT_16550A,
  185. .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
  186. .irq = UART0_IRQ,
  187. .regshift = 2,
  188. .iotype = UPIO_MEM,
  189. .flags = UPF_BOOT_AUTOCONF,
  190. },
  191. {
  192. .flags = 0,
  193. }
  194. };
  195. static struct platform_device rb532_uart = {
  196. .name = "serial8250",
  197. .id = PLAT8250_DEV_PLATFORM,
  198. .dev.platform_data = &rb532_uart_res,
  199. };
  200. static struct platform_device *rb532_devs[] = {
  201. &korina_dev0,
  202. &nand_slot0,
  203. &cf_slot0,
  204. &rb532_led,
  205. &rb532_button,
  206. &rb532_uart,
  207. &rb532_wdt
  208. };
  209. /* NAND definitions */
  210. #define NAND_CHIP_DELAY 25
  211. static void __init rb532_nand_setup(void)
  212. {
  213. switch (mips_machtype) {
  214. case MACH_MIKROTIK_RB532A:
  215. set_latch_u5(LO_FOFF | LO_CEX,
  216. LO_ULED | LO_ALE | LO_CLE | LO_WPX);
  217. break;
  218. default:
  219. set_latch_u5(LO_WPX | LO_FOFF | LO_CEX,
  220. LO_ULED | LO_ALE | LO_CLE);
  221. break;
  222. }
  223. /* Setup NAND specific settings */
  224. rb532_nand_data.chip.nr_chips = 1;
  225. rb532_nand_data.chip.nr_partitions = ARRAY_SIZE(rb532_partition_info);
  226. rb532_nand_data.chip.partitions = rb532_partition_info;
  227. rb532_nand_data.chip.chip_delay = NAND_CHIP_DELAY;
  228. }
  229. static int __init plat_setup_devices(void)
  230. {
  231. /* Look for the CF card reader */
  232. if (!readl(IDT434_REG_BASE + DEV1MASK))
  233. rb532_devs[2] = NULL; /* disable cf_slot0 at index 2 */
  234. else {
  235. cf_slot0_res[0].start =
  236. readl(IDT434_REG_BASE + DEV1BASE);
  237. cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
  238. }
  239. /* Read the NAND resources from the device controller */
  240. nand_slot0_res[0].start = readl(IDT434_REG_BASE + DEV2BASE);
  241. nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
  242. /* Read and map device controller 3 */
  243. dev3.base = ioremap(readl(IDT434_REG_BASE + DEV3BASE), 1);
  244. if (!dev3.base) {
  245. printk(KERN_ERR "rb532: cannot remap device controller 3\n");
  246. return -ENXIO;
  247. }
  248. /* Initialise the NAND device */
  249. rb532_nand_setup();
  250. /* set the uart clock to the current cpu frequency */
  251. rb532_uart_res[0].uartclk = idt_cpu_freq;
  252. gpiod_add_lookup_table(&cf_slot0_gpio_table);
  253. return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs));
  254. }
  255. #ifdef CONFIG_NET
  256. static int __init setup_kmac(char *s)
  257. {
  258. printk(KERN_INFO "korina mac = %s\n", s);
  259. if (!mac_pton(s, korina_dev0_data.mac))
  260. printk(KERN_ERR "Invalid mac\n");
  261. return 1;
  262. }
  263. __setup("kmac=", setup_kmac);
  264. #endif /* CONFIG_NET */
  265. arch_initcall(plat_setup_devices);