rt3883.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. *
  4. * Parts of this file are based on Ralink's 2.6.21 BSP
  5. *
  6. * Copyright (C) 2008 Imre Kaloz <[email protected]>
  7. * Copyright (C) 2008-2011 Gabor Juhos <[email protected]>
  8. * Copyright (C) 2013 John Crispin <[email protected]>
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/init.h>
  12. #include <asm/mipsregs.h>
  13. #include <asm/mach-ralink/ralink_regs.h>
  14. #include <asm/mach-ralink/rt3883.h>
  15. #include "common.h"
  16. void __init ralink_clk_init(void)
  17. {
  18. unsigned long cpu_rate, sys_rate;
  19. u32 syscfg0;
  20. u32 clksel;
  21. u32 ddr2;
  22. syscfg0 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG0);
  23. clksel = ((syscfg0 >> RT3883_SYSCFG0_CPUCLK_SHIFT) &
  24. RT3883_SYSCFG0_CPUCLK_MASK);
  25. ddr2 = syscfg0 & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
  26. switch (clksel) {
  27. case RT3883_SYSCFG0_CPUCLK_250:
  28. cpu_rate = 250000000;
  29. sys_rate = (ddr2) ? 125000000 : 83000000;
  30. break;
  31. case RT3883_SYSCFG0_CPUCLK_384:
  32. cpu_rate = 384000000;
  33. sys_rate = (ddr2) ? 128000000 : 96000000;
  34. break;
  35. case RT3883_SYSCFG0_CPUCLK_480:
  36. cpu_rate = 480000000;
  37. sys_rate = (ddr2) ? 160000000 : 120000000;
  38. break;
  39. case RT3883_SYSCFG0_CPUCLK_500:
  40. cpu_rate = 500000000;
  41. sys_rate = (ddr2) ? 166000000 : 125000000;
  42. break;
  43. }
  44. ralink_clk_add("cpu", cpu_rate);
  45. ralink_clk_add("10000100.timer", sys_rate);
  46. ralink_clk_add("10000120.watchdog", sys_rate);
  47. ralink_clk_add("10000500.uart", 40000000);
  48. ralink_clk_add("10000900.i2c", 40000000);
  49. ralink_clk_add("10000a00.i2s", 40000000);
  50. ralink_clk_add("10000b00.spi", sys_rate);
  51. ralink_clk_add("10000b40.spi", sys_rate);
  52. ralink_clk_add("10000c00.uartlite", 40000000);
  53. ralink_clk_add("10100000.ethernet", sys_rate);
  54. ralink_clk_add("10180000.wmac", 40000000);
  55. }
  56. void __init ralink_of_remap(void)
  57. {
  58. rt_sysc_membase = plat_of_remap_node("ralink,rt3883-sysc");
  59. rt_memc_membase = plat_of_remap_node("ralink,rt3883-memc");
  60. if (!rt_sysc_membase || !rt_memc_membase)
  61. panic("Failed to remap core resources");
  62. }
  63. void __init prom_soc_init(struct ralink_soc_info *soc_info)
  64. {
  65. void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT3883_SYSC_BASE);
  66. const char *name;
  67. u32 n0;
  68. u32 n1;
  69. u32 id;
  70. n0 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID0_3);
  71. n1 = __raw_readl(sysc + RT3883_SYSC_REG_CHIPID4_7);
  72. id = __raw_readl(sysc + RT3883_SYSC_REG_REVID);
  73. if (n0 == RT3883_CHIP_NAME0 && n1 == RT3883_CHIP_NAME1) {
  74. soc_info->compatible = "ralink,rt3883-soc";
  75. name = "RT3883";
  76. } else {
  77. panic("rt3883: unknown SoC, n0:%08x n1:%08x", n0, n1);
  78. }
  79. snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
  80. "Ralink %s ver:%u eco:%u",
  81. name,
  82. (id >> RT3883_REVID_VER_ID_SHIFT) & RT3883_REVID_VER_ID_MASK,
  83. (id & RT3883_REVID_ECO_ID_MASK));
  84. soc_info->mem_base = RT3883_SDRAM_BASE;
  85. soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
  86. soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
  87. ralink_soc = RT3883_SOC;
  88. }