rt305x.c 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. *
  4. * Parts of this file are based on Ralink's 2.6.21 BSP
  5. *
  6. * Copyright (C) 2008-2011 Gabor Juhos <[email protected]>
  7. * Copyright (C) 2008 Imre Kaloz <[email protected]>
  8. * Copyright (C) 2013 John Crispin <[email protected]>
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/init.h>
  12. #include <linux/bug.h>
  13. #include <asm/io.h>
  14. #include <asm/mipsregs.h>
  15. #include <asm/mach-ralink/ralink_regs.h>
  16. #include <asm/mach-ralink/rt305x.h>
  17. #include "common.h"
  18. static unsigned long rt5350_get_mem_size(void)
  19. {
  20. void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
  21. unsigned long ret;
  22. u32 t;
  23. t = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG);
  24. t = (t >> RT5350_SYSCFG0_DRAM_SIZE_SHIFT) &
  25. RT5350_SYSCFG0_DRAM_SIZE_MASK;
  26. switch (t) {
  27. case RT5350_SYSCFG0_DRAM_SIZE_2M:
  28. ret = 2;
  29. break;
  30. case RT5350_SYSCFG0_DRAM_SIZE_8M:
  31. ret = 8;
  32. break;
  33. case RT5350_SYSCFG0_DRAM_SIZE_16M:
  34. ret = 16;
  35. break;
  36. case RT5350_SYSCFG0_DRAM_SIZE_32M:
  37. ret = 32;
  38. break;
  39. case RT5350_SYSCFG0_DRAM_SIZE_64M:
  40. ret = 64;
  41. break;
  42. default:
  43. panic("rt5350: invalid DRAM size: %u", t);
  44. break;
  45. }
  46. return ret;
  47. }
  48. void __init ralink_clk_init(void)
  49. {
  50. unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
  51. unsigned long wmac_rate = 40000000;
  52. u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
  53. if (soc_is_rt305x() || soc_is_rt3350()) {
  54. t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
  55. RT305X_SYSCFG_CPUCLK_MASK;
  56. switch (t) {
  57. case RT305X_SYSCFG_CPUCLK_LOW:
  58. cpu_rate = 320000000;
  59. break;
  60. case RT305X_SYSCFG_CPUCLK_HIGH:
  61. cpu_rate = 384000000;
  62. break;
  63. }
  64. sys_rate = uart_rate = wdt_rate = cpu_rate / 3;
  65. } else if (soc_is_rt3352()) {
  66. t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) &
  67. RT3352_SYSCFG0_CPUCLK_MASK;
  68. switch (t) {
  69. case RT3352_SYSCFG0_CPUCLK_LOW:
  70. cpu_rate = 384000000;
  71. break;
  72. case RT3352_SYSCFG0_CPUCLK_HIGH:
  73. cpu_rate = 400000000;
  74. break;
  75. }
  76. sys_rate = wdt_rate = cpu_rate / 3;
  77. uart_rate = 40000000;
  78. } else if (soc_is_rt5350()) {
  79. t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) &
  80. RT5350_SYSCFG0_CPUCLK_MASK;
  81. switch (t) {
  82. case RT5350_SYSCFG0_CPUCLK_360:
  83. cpu_rate = 360000000;
  84. sys_rate = cpu_rate / 3;
  85. break;
  86. case RT5350_SYSCFG0_CPUCLK_320:
  87. cpu_rate = 320000000;
  88. sys_rate = cpu_rate / 4;
  89. break;
  90. case RT5350_SYSCFG0_CPUCLK_300:
  91. cpu_rate = 300000000;
  92. sys_rate = cpu_rate / 3;
  93. break;
  94. default:
  95. BUG();
  96. }
  97. uart_rate = 40000000;
  98. wdt_rate = sys_rate;
  99. } else {
  100. BUG();
  101. }
  102. if (soc_is_rt3352() || soc_is_rt5350()) {
  103. u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
  104. if (!(val & RT3352_CLKCFG0_XTAL_SEL))
  105. wmac_rate = 20000000;
  106. }
  107. ralink_clk_add("cpu", cpu_rate);
  108. ralink_clk_add("sys", sys_rate);
  109. ralink_clk_add("10000900.i2c", uart_rate);
  110. ralink_clk_add("10000a00.i2s", uart_rate);
  111. ralink_clk_add("10000b00.spi", sys_rate);
  112. ralink_clk_add("10000b40.spi", sys_rate);
  113. ralink_clk_add("10000100.timer", wdt_rate);
  114. ralink_clk_add("10000120.watchdog", wdt_rate);
  115. ralink_clk_add("10000500.uart", uart_rate);
  116. ralink_clk_add("10000c00.uartlite", uart_rate);
  117. ralink_clk_add("10100000.ethernet", sys_rate);
  118. ralink_clk_add("10180000.wmac", wmac_rate);
  119. }
  120. void __init ralink_of_remap(void)
  121. {
  122. rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc");
  123. rt_memc_membase = plat_of_remap_node("ralink,rt3050-memc");
  124. if (!rt_sysc_membase || !rt_memc_membase)
  125. panic("Failed to remap core resources");
  126. }
  127. void __init prom_soc_init(struct ralink_soc_info *soc_info)
  128. {
  129. void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
  130. unsigned char *name;
  131. u32 n0;
  132. u32 n1;
  133. u32 id;
  134. n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
  135. n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
  136. if (n0 == RT3052_CHIP_NAME0 && n1 == RT3052_CHIP_NAME1) {
  137. unsigned long icache_sets;
  138. icache_sets = (read_c0_config1() >> 22) & 7;
  139. if (icache_sets == 1) {
  140. ralink_soc = RT305X_SOC_RT3050;
  141. name = "RT3050";
  142. soc_info->compatible = "ralink,rt3050-soc";
  143. } else {
  144. ralink_soc = RT305X_SOC_RT3052;
  145. name = "RT3052";
  146. soc_info->compatible = "ralink,rt3052-soc";
  147. }
  148. } else if (n0 == RT3350_CHIP_NAME0 && n1 == RT3350_CHIP_NAME1) {
  149. ralink_soc = RT305X_SOC_RT3350;
  150. name = "RT3350";
  151. soc_info->compatible = "ralink,rt3350-soc";
  152. } else if (n0 == RT3352_CHIP_NAME0 && n1 == RT3352_CHIP_NAME1) {
  153. ralink_soc = RT305X_SOC_RT3352;
  154. name = "RT3352";
  155. soc_info->compatible = "ralink,rt3352-soc";
  156. } else if (n0 == RT5350_CHIP_NAME0 && n1 == RT5350_CHIP_NAME1) {
  157. ralink_soc = RT305X_SOC_RT5350;
  158. name = "RT5350";
  159. soc_info->compatible = "ralink,rt5350-soc";
  160. } else {
  161. panic("rt305x: unknown SoC, n0:%08x n1:%08x", n0, n1);
  162. }
  163. id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
  164. snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
  165. "Ralink %s id:%u rev:%u",
  166. name,
  167. (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
  168. (id & CHIP_ID_REV_MASK));
  169. soc_info->mem_base = RT305X_SDRAM_BASE;
  170. if (soc_is_rt5350()) {
  171. soc_info->mem_size = rt5350_get_mem_size();
  172. } else if (soc_is_rt305x() || soc_is_rt3350()) {
  173. soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
  174. soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
  175. } else if (soc_is_rt3352()) {
  176. soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
  177. soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
  178. }
  179. }