rt288x.c 2.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. *
  4. * Parts of this file are based on Ralink's 2.6.21 BSP
  5. *
  6. * Copyright (C) 2008-2011 Gabor Juhos <[email protected]>
  7. * Copyright (C) 2008 Imre Kaloz <[email protected]>
  8. * Copyright (C) 2013 John Crispin <[email protected]>
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/init.h>
  12. #include <asm/mipsregs.h>
  13. #include <asm/mach-ralink/ralink_regs.h>
  14. #include <asm/mach-ralink/rt288x.h>
  15. #include "common.h"
  16. void __init ralink_clk_init(void)
  17. {
  18. unsigned long cpu_rate, wmac_rate = 40000000;
  19. u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
  20. t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
  21. switch (t) {
  22. case SYSTEM_CONFIG_CPUCLK_250:
  23. cpu_rate = 250000000;
  24. break;
  25. case SYSTEM_CONFIG_CPUCLK_266:
  26. cpu_rate = 266666667;
  27. break;
  28. case SYSTEM_CONFIG_CPUCLK_280:
  29. cpu_rate = 280000000;
  30. break;
  31. case SYSTEM_CONFIG_CPUCLK_300:
  32. cpu_rate = 300000000;
  33. break;
  34. }
  35. ralink_clk_add("cpu", cpu_rate);
  36. ralink_clk_add("300100.timer", cpu_rate / 2);
  37. ralink_clk_add("300120.watchdog", cpu_rate / 2);
  38. ralink_clk_add("300500.uart", cpu_rate / 2);
  39. ralink_clk_add("300900.i2c", cpu_rate / 2);
  40. ralink_clk_add("300c00.uartlite", cpu_rate / 2);
  41. ralink_clk_add("400000.ethernet", cpu_rate / 2);
  42. ralink_clk_add("480000.wmac", wmac_rate);
  43. }
  44. void __init ralink_of_remap(void)
  45. {
  46. rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");
  47. rt_memc_membase = plat_of_remap_node("ralink,rt2880-memc");
  48. if (!rt_sysc_membase || !rt_memc_membase)
  49. panic("Failed to remap core resources");
  50. }
  51. void __init prom_soc_init(struct ralink_soc_info *soc_info)
  52. {
  53. void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE);
  54. const char *name;
  55. u32 n0;
  56. u32 n1;
  57. u32 id;
  58. n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
  59. n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
  60. id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
  61. if (n0 == RT2880_CHIP_NAME0 && n1 == RT2880_CHIP_NAME1) {
  62. soc_info->compatible = "ralink,r2880-soc";
  63. name = "RT2880";
  64. } else {
  65. panic("rt288x: unknown SoC, n0:%08x n1:%08x", n0, n1);
  66. }
  67. snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
  68. "Ralink %s id:%u rev:%u",
  69. name,
  70. (id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
  71. (id & CHIP_ID_REV_MASK));
  72. soc_info->mem_base = RT2880_SDRAM_BASE;
  73. soc_info->mem_size_min = RT2880_MEM_SIZE_MIN;
  74. soc_info->mem_size_max = RT2880_MEM_SIZE_MAX;
  75. ralink_soc = RT2880_SOC;
  76. }