mt7621.c 5.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. *
  4. * Copyright (C) 2015 Nikolay Martynov <[email protected]>
  5. * Copyright (C) 2015 John Crispin <[email protected]>
  6. */
  7. #include <linux/kernel.h>
  8. #include <linux/init.h>
  9. #include <linux/slab.h>
  10. #include <linux/sys_soc.h>
  11. #include <linux/memblock.h>
  12. #include <linux/pci.h>
  13. #include <linux/bug.h>
  14. #include <asm/bootinfo.h>
  15. #include <asm/mipsregs.h>
  16. #include <asm/smp-ops.h>
  17. #include <asm/mips-cps.h>
  18. #include <asm/mach-ralink/ralink_regs.h>
  19. #include <asm/mach-ralink/mt7621.h>
  20. #include "common.h"
  21. #define MT7621_MEM_TEST_PATTERN 0xaa5555aa
  22. static u32 detect_magic __initdata;
  23. static struct ralink_soc_info *soc_info_ptr;
  24. int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
  25. {
  26. struct resource_entry *entry;
  27. resource_size_t mask;
  28. entry = resource_list_first_type(&bridge->windows, IORESOURCE_MEM);
  29. if (!entry) {
  30. pr_err("Cannot get memory resource\n");
  31. return -EINVAL;
  32. }
  33. if (mips_cps_numiocu(0)) {
  34. /*
  35. * Hardware doesn't accept mask values with 1s after
  36. * 0s (e.g. 0xffef), so warn if that's happen
  37. */
  38. mask = ~(entry->res->end - entry->res->start) & CM_GCR_REGn_MASK_ADDRMASK;
  39. WARN_ON(mask && BIT(ffz(~mask)) - 1 != ~mask);
  40. write_gcr_reg1_base(entry->res->start);
  41. write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
  42. pr_info("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
  43. (unsigned long long)read_gcr_reg1_base(),
  44. (unsigned long long)read_gcr_reg1_mask());
  45. }
  46. return 0;
  47. }
  48. phys_addr_t mips_cpc_default_phys_base(void)
  49. {
  50. panic("Cannot detect cpc address");
  51. }
  52. static bool __init mt7621_addr_wraparound_test(phys_addr_t size)
  53. {
  54. void *dm = (void *)KSEG1ADDR(&detect_magic);
  55. if (CPHYSADDR(dm + size) >= MT7621_LOWMEM_MAX_SIZE)
  56. return true;
  57. __raw_writel(MT7621_MEM_TEST_PATTERN, dm);
  58. if (__raw_readl(dm) != __raw_readl(dm + size))
  59. return false;
  60. __raw_writel(~MT7621_MEM_TEST_PATTERN, dm);
  61. return __raw_readl(dm) == __raw_readl(dm + size);
  62. }
  63. static void __init mt7621_memory_detect(void)
  64. {
  65. phys_addr_t size;
  66. for (size = 32 * SZ_1M; size <= 256 * SZ_1M; size <<= 1) {
  67. if (mt7621_addr_wraparound_test(size)) {
  68. memblock_add(MT7621_LOWMEM_BASE, size);
  69. return;
  70. }
  71. }
  72. memblock_add(MT7621_LOWMEM_BASE, MT7621_LOWMEM_MAX_SIZE);
  73. memblock_add(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE);
  74. }
  75. void __init ralink_of_remap(void)
  76. {
  77. rt_sysc_membase = plat_of_remap_node("mediatek,mt7621-sysc");
  78. rt_memc_membase = plat_of_remap_node("mediatek,mt7621-memc");
  79. if (!rt_sysc_membase || !rt_memc_membase)
  80. panic("Failed to remap core resources");
  81. }
  82. static unsigned int __init mt7621_get_soc_name0(void)
  83. {
  84. return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME0);
  85. }
  86. static unsigned int __init mt7621_get_soc_name1(void)
  87. {
  88. return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME1);
  89. }
  90. static bool __init mt7621_soc_valid(void)
  91. {
  92. if (mt7621_get_soc_name0() == MT7621_CHIP_NAME0 &&
  93. mt7621_get_soc_name1() == MT7621_CHIP_NAME1)
  94. return true;
  95. else
  96. return false;
  97. }
  98. static const char __init *mt7621_get_soc_id(void)
  99. {
  100. if (mt7621_soc_valid())
  101. return "MT7621";
  102. else
  103. return "invalid";
  104. }
  105. static unsigned int __init mt7621_get_soc_rev(void)
  106. {
  107. return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_REV);
  108. }
  109. static unsigned int __init mt7621_get_soc_ver(void)
  110. {
  111. return (mt7621_get_soc_rev() >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK;
  112. }
  113. static unsigned int __init mt7621_get_soc_eco(void)
  114. {
  115. return (mt7621_get_soc_rev() & CHIP_REV_ECO_MASK);
  116. }
  117. static const char __init *mt7621_get_soc_revision(void)
  118. {
  119. if (mt7621_get_soc_rev() == 1 && mt7621_get_soc_eco() == 1)
  120. return "E2";
  121. else
  122. return "E1";
  123. }
  124. static int __init mt7621_soc_dev_init(void)
  125. {
  126. struct soc_device *soc_dev;
  127. struct soc_device_attribute *soc_dev_attr;
  128. soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
  129. if (!soc_dev_attr)
  130. return -ENOMEM;
  131. soc_dev_attr->soc_id = "mt7621";
  132. soc_dev_attr->family = "Ralink";
  133. soc_dev_attr->revision = mt7621_get_soc_revision();
  134. soc_dev_attr->data = soc_info_ptr;
  135. soc_dev = soc_device_register(soc_dev_attr);
  136. if (IS_ERR(soc_dev)) {
  137. kfree(soc_dev_attr);
  138. return PTR_ERR(soc_dev);
  139. }
  140. return 0;
  141. }
  142. device_initcall(mt7621_soc_dev_init);
  143. void __init prom_soc_init(struct ralink_soc_info *soc_info)
  144. {
  145. /* Early detection of CMP support */
  146. mips_cm_probe();
  147. mips_cpc_probe();
  148. if (mips_cps_numiocu(0)) {
  149. /*
  150. * mips_cm_probe() wipes out bootloader
  151. * config for CM regions and we have to configure them
  152. * again. This SoC cannot talk to pamlbus devices
  153. * witout proper iocu region set up.
  154. *
  155. * FIXME: it would be better to do this with values
  156. * from DT, but we need this very early because
  157. * without this we cannot talk to pretty much anything
  158. * including serial.
  159. */
  160. write_gcr_reg0_base(MT7621_PALMBUS_BASE);
  161. write_gcr_reg0_mask(~MT7621_PALMBUS_SIZE |
  162. CM_GCR_REGn_MASK_CMTGT_IOCU0);
  163. __sync();
  164. }
  165. if (mt7621_soc_valid())
  166. soc_info->compatible = "mediatek,mt7621-soc";
  167. else
  168. panic("mt7621: unknown SoC, n0:%08x n1:%08x\n",
  169. mt7621_get_soc_name0(),
  170. mt7621_get_soc_name1());
  171. ralink_soc = MT762X_SOC_MT7621AT;
  172. snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
  173. "MediaTek %s ver:%u eco:%u",
  174. mt7621_get_soc_id(),
  175. mt7621_get_soc_ver(),
  176. mt7621_get_soc_eco());
  177. soc_info->mem_detect = mt7621_memory_detect;
  178. soc_info_ptr = soc_info;
  179. if (!register_cps_smp_ops())
  180. return;
  181. if (!register_cmp_smp_ops())
  182. return;
  183. if (!register_vsmp_smp_ops())
  184. return;
  185. }