mt7620.c 9.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. *
  4. * Parts of this file are based on Ralink's 2.6.21 BSP
  5. *
  6. * Copyright (C) 2008-2011 Gabor Juhos <[email protected]>
  7. * Copyright (C) 2008 Imre Kaloz <[email protected]>
  8. * Copyright (C) 2013 John Crispin <[email protected]>
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/init.h>
  12. #include <linux/bug.h>
  13. #include <asm/mipsregs.h>
  14. #include <asm/mach-ralink/ralink_regs.h>
  15. #include <asm/mach-ralink/mt7620.h>
  16. #include "common.h"
  17. /* analog */
  18. #define PMU0_CFG 0x88
  19. #define PMU_SW_SET BIT(28)
  20. #define A_DCDC_EN BIT(24)
  21. #define A_SSC_PERI BIT(19)
  22. #define A_SSC_GEN BIT(18)
  23. #define A_SSC_M 0x3
  24. #define A_SSC_S 16
  25. #define A_DLY_M 0x7
  26. #define A_DLY_S 8
  27. #define A_VTUNE_M 0xff
  28. /* digital */
  29. #define PMU1_CFG 0x8C
  30. #define DIG_SW_SEL BIT(25)
  31. /* clock scaling */
  32. #define CLKCFG_FDIV_MASK 0x1f00
  33. #define CLKCFG_FDIV_USB_VAL 0x0300
  34. #define CLKCFG_FFRAC_MASK 0x001f
  35. #define CLKCFG_FFRAC_USB_VAL 0x0003
  36. /* EFUSE bits */
  37. #define EFUSE_MT7688 0x100000
  38. /* DRAM type bit */
  39. #define DRAM_TYPE_MT7628_MASK 0x1
  40. /* does the board have sdram or ddram */
  41. static int dram_type;
  42. static __init u32
  43. mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
  44. {
  45. u64 t;
  46. t = ref_rate;
  47. t *= mul;
  48. do_div(t, div);
  49. return t;
  50. }
  51. #define MHZ(x) ((x) * 1000 * 1000)
  52. static __init unsigned long
  53. mt7620_get_xtal_rate(void)
  54. {
  55. u32 reg;
  56. reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
  57. if (reg & SYSCFG0_XTAL_FREQ_SEL)
  58. return MHZ(40);
  59. return MHZ(20);
  60. }
  61. static __init unsigned long
  62. mt7620_get_periph_rate(unsigned long xtal_rate)
  63. {
  64. u32 reg;
  65. reg = rt_sysc_r32(SYSC_REG_CLKCFG0);
  66. if (reg & CLKCFG0_PERI_CLK_SEL)
  67. return xtal_rate;
  68. return MHZ(40);
  69. }
  70. static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 };
  71. static __init unsigned long
  72. mt7620_get_cpu_pll_rate(unsigned long xtal_rate)
  73. {
  74. u32 reg;
  75. u32 mul;
  76. u32 div;
  77. reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
  78. if (reg & CPLL_CFG0_BYPASS_REF_CLK)
  79. return xtal_rate;
  80. if ((reg & CPLL_CFG0_SW_CFG) == 0)
  81. return MHZ(600);
  82. mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
  83. CPLL_CFG0_PLL_MULT_RATIO_MASK;
  84. mul += 24;
  85. if (reg & CPLL_CFG0_LC_CURFCK)
  86. mul *= 2;
  87. div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
  88. CPLL_CFG0_PLL_DIV_RATIO_MASK;
  89. WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider));
  90. return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]);
  91. }
  92. static __init unsigned long
  93. mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate)
  94. {
  95. u32 reg;
  96. reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
  97. if (reg & CPLL_CFG1_CPU_AUX1)
  98. return xtal_rate;
  99. if (reg & CPLL_CFG1_CPU_AUX0)
  100. return MHZ(480);
  101. return cpu_pll_rate;
  102. }
  103. static __init unsigned long
  104. mt7620_get_cpu_rate(unsigned long pll_rate)
  105. {
  106. u32 reg;
  107. u32 mul;
  108. u32 div;
  109. reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
  110. mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
  111. div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
  112. CPU_SYS_CLKCFG_CPU_FDIV_MASK;
  113. return mt7620_calc_rate(pll_rate, mul, div);
  114. }
  115. static const u32 mt7620_ocp_dividers[16] __initconst = {
  116. [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
  117. [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
  118. [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
  119. [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
  120. [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
  121. };
  122. static __init unsigned long
  123. mt7620_get_dram_rate(unsigned long pll_rate)
  124. {
  125. if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
  126. return pll_rate / 4;
  127. return pll_rate / 3;
  128. }
  129. static __init unsigned long
  130. mt7620_get_sys_rate(unsigned long cpu_rate)
  131. {
  132. u32 reg;
  133. u32 ocp_ratio;
  134. u32 div;
  135. reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
  136. ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
  137. CPU_SYS_CLKCFG_OCP_RATIO_MASK;
  138. if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers)))
  139. return cpu_rate;
  140. div = mt7620_ocp_dividers[ocp_ratio];
  141. if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
  142. return cpu_rate;
  143. return cpu_rate / div;
  144. }
  145. void __init ralink_clk_init(void)
  146. {
  147. unsigned long xtal_rate;
  148. unsigned long cpu_pll_rate;
  149. unsigned long pll_rate;
  150. unsigned long cpu_rate;
  151. unsigned long sys_rate;
  152. unsigned long dram_rate;
  153. unsigned long periph_rate;
  154. unsigned long pcmi2s_rate;
  155. xtal_rate = mt7620_get_xtal_rate();
  156. #define RFMT(label) label ":%lu.%03luMHz "
  157. #define RINT(x) ((x) / 1000000)
  158. #define RFRAC(x) (((x) / 1000) % 1000)
  159. if (is_mt76x8()) {
  160. if (xtal_rate == MHZ(40))
  161. cpu_rate = MHZ(580);
  162. else
  163. cpu_rate = MHZ(575);
  164. dram_rate = sys_rate = cpu_rate / 3;
  165. periph_rate = MHZ(40);
  166. pcmi2s_rate = MHZ(480);
  167. ralink_clk_add("10000d00.uartlite", periph_rate);
  168. ralink_clk_add("10000e00.uartlite", periph_rate);
  169. } else {
  170. cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
  171. pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
  172. cpu_rate = mt7620_get_cpu_rate(pll_rate);
  173. dram_rate = mt7620_get_dram_rate(pll_rate);
  174. sys_rate = mt7620_get_sys_rate(cpu_rate);
  175. periph_rate = mt7620_get_periph_rate(xtal_rate);
  176. pcmi2s_rate = periph_rate;
  177. pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
  178. RINT(xtal_rate), RFRAC(xtal_rate),
  179. RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
  180. RINT(pll_rate), RFRAC(pll_rate));
  181. ralink_clk_add("10000500.uart", periph_rate);
  182. }
  183. pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
  184. RINT(cpu_rate), RFRAC(cpu_rate),
  185. RINT(dram_rate), RFRAC(dram_rate),
  186. RINT(sys_rate), RFRAC(sys_rate),
  187. RINT(periph_rate), RFRAC(periph_rate));
  188. #undef RFRAC
  189. #undef RINT
  190. #undef RFMT
  191. ralink_clk_add("cpu", cpu_rate);
  192. ralink_clk_add("10000100.timer", periph_rate);
  193. ralink_clk_add("10000120.watchdog", periph_rate);
  194. ralink_clk_add("10000900.i2c", periph_rate);
  195. ralink_clk_add("10000a00.i2s", pcmi2s_rate);
  196. ralink_clk_add("10000b00.spi", sys_rate);
  197. ralink_clk_add("10000b40.spi", sys_rate);
  198. ralink_clk_add("10000c00.uartlite", periph_rate);
  199. ralink_clk_add("10000d00.uart1", periph_rate);
  200. ralink_clk_add("10000e00.uart2", periph_rate);
  201. ralink_clk_add("10180000.wmac", xtal_rate);
  202. if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
  203. /*
  204. * When the CPU goes into sleep mode, the BUS clock will be
  205. * too low for USB to function properly. Adjust the busses
  206. * fractional divider to fix this
  207. */
  208. u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
  209. val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
  210. val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
  211. rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
  212. }
  213. }
  214. void __init ralink_of_remap(void)
  215. {
  216. rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
  217. rt_memc_membase = plat_of_remap_node("ralink,mt7620a-memc");
  218. if (!rt_sysc_membase || !rt_memc_membase)
  219. panic("Failed to remap core resources");
  220. }
  221. static __init void
  222. mt7620_dram_init(struct ralink_soc_info *soc_info)
  223. {
  224. switch (dram_type) {
  225. case SYSCFG0_DRAM_TYPE_SDRAM:
  226. pr_info("Board has SDRAM\n");
  227. soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
  228. soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
  229. break;
  230. case SYSCFG0_DRAM_TYPE_DDR1:
  231. pr_info("Board has DDR1\n");
  232. soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
  233. soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
  234. break;
  235. case SYSCFG0_DRAM_TYPE_DDR2:
  236. pr_info("Board has DDR2\n");
  237. soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
  238. soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
  239. break;
  240. default:
  241. BUG();
  242. }
  243. }
  244. static __init void
  245. mt7628_dram_init(struct ralink_soc_info *soc_info)
  246. {
  247. switch (dram_type) {
  248. case SYSCFG0_DRAM_TYPE_DDR1_MT7628:
  249. pr_info("Board has DDR1\n");
  250. soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
  251. soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
  252. break;
  253. case SYSCFG0_DRAM_TYPE_DDR2_MT7628:
  254. pr_info("Board has DDR2\n");
  255. soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
  256. soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
  257. break;
  258. default:
  259. BUG();
  260. }
  261. }
  262. void __init prom_soc_init(struct ralink_soc_info *soc_info)
  263. {
  264. void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7620_SYSC_BASE);
  265. unsigned char *name = NULL;
  266. u32 n0;
  267. u32 n1;
  268. u32 rev;
  269. u32 cfg0;
  270. u32 pmu0;
  271. u32 pmu1;
  272. u32 bga;
  273. n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
  274. n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
  275. rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
  276. bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK;
  277. if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) {
  278. if (bga) {
  279. ralink_soc = MT762X_SOC_MT7620A;
  280. name = "MT7620A";
  281. soc_info->compatible = "ralink,mt7620a-soc";
  282. } else {
  283. ralink_soc = MT762X_SOC_MT7620N;
  284. name = "MT7620N";
  285. soc_info->compatible = "ralink,mt7620n-soc";
  286. }
  287. } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
  288. u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG);
  289. if (efuse & EFUSE_MT7688) {
  290. ralink_soc = MT762X_SOC_MT7688;
  291. name = "MT7688";
  292. } else {
  293. ralink_soc = MT762X_SOC_MT7628AN;
  294. name = "MT7628AN";
  295. }
  296. soc_info->compatible = "ralink,mt7628an-soc";
  297. } else {
  298. panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
  299. }
  300. snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
  301. "MediaTek %s ver:%u eco:%u",
  302. name,
  303. (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
  304. (rev & CHIP_REV_ECO_MASK));
  305. cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
  306. if (is_mt76x8()) {
  307. dram_type = cfg0 & DRAM_TYPE_MT7628_MASK;
  308. } else {
  309. dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) &
  310. SYSCFG0_DRAM_TYPE_MASK;
  311. if (dram_type == SYSCFG0_DRAM_TYPE_UNKNOWN)
  312. dram_type = SYSCFG0_DRAM_TYPE_SDRAM;
  313. }
  314. soc_info->mem_base = MT7620_DRAM_BASE;
  315. if (is_mt76x8())
  316. mt7628_dram_init(soc_info);
  317. else
  318. mt7620_dram_init(soc_info);
  319. pmu0 = __raw_readl(sysc + PMU0_CFG);
  320. pmu1 = __raw_readl(sysc + PMU1_CFG);
  321. pr_info("Analog PMU set to %s control\n",
  322. (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
  323. pr_info("Digital PMU set to %s control\n",
  324. (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
  325. }