pci-sb1250.c 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2001,2002,2003 Broadcom Corporation
  4. * Copyright (C) 2004 by Ralf Baechle ([email protected])
  5. */
  6. /*
  7. * BCM1250-specific PCI support
  8. *
  9. * This module provides the glue between Linux's PCI subsystem
  10. * and the hardware. We basically provide glue for accessing
  11. * configuration space, and set up the translation for I/O
  12. * space accesses.
  13. *
  14. * To access configuration space, we use ioremap. In the 32-bit
  15. * kernel, this consumes either 4 or 8 page table pages, and 16MB of
  16. * kernel mapped memory. Hopefully neither of these should be a huge
  17. * problem.
  18. */
  19. #include <linux/types.h>
  20. #include <linux/pci.h>
  21. #include <linux/kernel.h>
  22. #include <linux/init.h>
  23. #include <linux/mm.h>
  24. #include <linux/console.h>
  25. #include <linux/tty.h>
  26. #include <linux/vt.h>
  27. #include <asm/io.h>
  28. #include <asm/sibyte/sb1250_defs.h>
  29. #include <asm/sibyte/sb1250_regs.h>
  30. #include <asm/sibyte/sb1250_scd.h>
  31. #include <asm/sibyte/board.h>
  32. /*
  33. * Macros for calculating offsets into config space given a device
  34. * structure or dev/fun/reg
  35. */
  36. #define CFGOFFSET(bus, devfn, where) (((bus)<<16) + ((devfn)<<8) + (where))
  37. #define CFGADDR(bus, devfn, where) CFGOFFSET((bus)->number, (devfn), where)
  38. static void *cfg_space;
  39. #define PCI_BUS_ENABLED 1
  40. #define LDT_BUS_ENABLED 2
  41. #define PCI_DEVICE_MODE 4
  42. static int sb1250_bus_status;
  43. #define PCI_BRIDGE_DEVICE 0
  44. #define LDT_BRIDGE_DEVICE 1
  45. #ifdef CONFIG_SIBYTE_HAS_LDT
  46. /*
  47. * HT's level-sensitive interrupts require EOI, which is generated
  48. * through a 4MB memory-mapped region
  49. */
  50. unsigned long ldt_eoi_space;
  51. #endif
  52. /*
  53. * Read/write 32-bit values in config space.
  54. */
  55. static inline u32 READCFG32(u32 addr)
  56. {
  57. return *(u32 *) (cfg_space + (addr & ~3));
  58. }
  59. static inline void WRITECFG32(u32 addr, u32 data)
  60. {
  61. *(u32 *) (cfg_space + (addr & ~3)) = data;
  62. }
  63. int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  64. {
  65. return dev->irq;
  66. }
  67. /* Do platform specific device initialization at pci_enable_device() time */
  68. int pcibios_plat_dev_init(struct pci_dev *dev)
  69. {
  70. return 0;
  71. }
  72. /*
  73. * Some checks before doing config cycles:
  74. * In PCI Device Mode, hide everything on bus 0 except the LDT host
  75. * bridge. Otherwise, access is controlled by bridge MasterEn bits.
  76. */
  77. static int sb1250_pci_can_access(struct pci_bus *bus, int devfn)
  78. {
  79. u32 devno;
  80. if (!(sb1250_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE)))
  81. return 0;
  82. if (bus->number == 0) {
  83. devno = PCI_SLOT(devfn);
  84. if (devno == LDT_BRIDGE_DEVICE)
  85. return (sb1250_bus_status & LDT_BUS_ENABLED) != 0;
  86. else if (sb1250_bus_status & PCI_DEVICE_MODE)
  87. return 0;
  88. else
  89. return 1;
  90. } else
  91. return 1;
  92. }
  93. /*
  94. * Read/write access functions for various sizes of values
  95. * in config space. Return all 1's for disallowed accesses
  96. * for a kludgy but adequate simulation of master aborts.
  97. */
  98. static int sb1250_pcibios_read(struct pci_bus *bus, unsigned int devfn,
  99. int where, int size, u32 * val)
  100. {
  101. u32 data = 0;
  102. if ((size == 2) && (where & 1))
  103. return PCIBIOS_BAD_REGISTER_NUMBER;
  104. else if ((size == 4) && (where & 3))
  105. return PCIBIOS_BAD_REGISTER_NUMBER;
  106. if (sb1250_pci_can_access(bus, devfn))
  107. data = READCFG32(CFGADDR(bus, devfn, where));
  108. else
  109. data = 0xFFFFFFFF;
  110. if (size == 1)
  111. *val = (data >> ((where & 3) << 3)) & 0xff;
  112. else if (size == 2)
  113. *val = (data >> ((where & 3) << 3)) & 0xffff;
  114. else
  115. *val = data;
  116. return PCIBIOS_SUCCESSFUL;
  117. }
  118. static int sb1250_pcibios_write(struct pci_bus *bus, unsigned int devfn,
  119. int where, int size, u32 val)
  120. {
  121. u32 cfgaddr = CFGADDR(bus, devfn, where);
  122. u32 data = 0;
  123. if ((size == 2) && (where & 1))
  124. return PCIBIOS_BAD_REGISTER_NUMBER;
  125. else if ((size == 4) && (where & 3))
  126. return PCIBIOS_BAD_REGISTER_NUMBER;
  127. if (!sb1250_pci_can_access(bus, devfn))
  128. return PCIBIOS_BAD_REGISTER_NUMBER;
  129. data = READCFG32(cfgaddr);
  130. if (size == 1)
  131. data = (data & ~(0xff << ((where & 3) << 3))) |
  132. (val << ((where & 3) << 3));
  133. else if (size == 2)
  134. data = (data & ~(0xffff << ((where & 3) << 3))) |
  135. (val << ((where & 3) << 3));
  136. else
  137. data = val;
  138. WRITECFG32(cfgaddr, data);
  139. return PCIBIOS_SUCCESSFUL;
  140. }
  141. struct pci_ops sb1250_pci_ops = {
  142. .read = sb1250_pcibios_read,
  143. .write = sb1250_pcibios_write,
  144. };
  145. static struct resource sb1250_mem_resource = {
  146. .name = "SB1250 PCI MEM",
  147. .start = 0x40000000UL,
  148. .end = 0x5fffffffUL,
  149. .flags = IORESOURCE_MEM,
  150. };
  151. static struct resource sb1250_io_resource = {
  152. .name = "SB1250 PCI I/O",
  153. .start = 0x00000000UL,
  154. .end = 0x01ffffffUL,
  155. .flags = IORESOURCE_IO,
  156. };
  157. struct pci_controller sb1250_controller = {
  158. .pci_ops = &sb1250_pci_ops,
  159. .mem_resource = &sb1250_mem_resource,
  160. .io_resource = &sb1250_io_resource,
  161. };
  162. static int __init sb1250_pcibios_init(void)
  163. {
  164. void __iomem *io_map_base;
  165. uint32_t cmdreg;
  166. uint64_t reg;
  167. /* CFE will assign PCI resources */
  168. pci_set_flags(PCI_PROBE_ONLY);
  169. /* Avoid ISA compat ranges. */
  170. PCIBIOS_MIN_IO = 0x00008000UL;
  171. PCIBIOS_MIN_MEM = 0x01000000UL;
  172. /* Set I/O resource limits. */
  173. ioport_resource.end = 0x01ffffffUL; /* 32MB accessible by sb1250 */
  174. iomem_resource.end = 0xffffffffUL; /* no HT support yet */
  175. cfg_space =
  176. ioremap(A_PHYS_LDTPCI_CFG_MATCH_BITS, 16 * 1024 * 1024);
  177. /*
  178. * See if the PCI bus has been configured by the firmware.
  179. */
  180. reg = __raw_readq(IOADDR(A_SCD_SYSTEM_CFG));
  181. if (!(reg & M_SYS_PCI_HOST)) {
  182. sb1250_bus_status |= PCI_DEVICE_MODE;
  183. } else {
  184. cmdreg =
  185. READCFG32(CFGOFFSET
  186. (0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0),
  187. PCI_COMMAND));
  188. if (!(cmdreg & PCI_COMMAND_MASTER)) {
  189. printk
  190. ("PCI: Skipping PCI probe. Bus is not initialized.\n");
  191. iounmap(cfg_space);
  192. return 0;
  193. }
  194. sb1250_bus_status |= PCI_BUS_ENABLED;
  195. }
  196. /*
  197. * Establish mappings in KSEG2 (kernel virtual) to PCI I/O
  198. * space. Use "match bytes" policy to make everything look
  199. * little-endian. So, you need to also set
  200. * CONFIG_SWAP_IO_SPACE, but this is the combination that
  201. * works correctly with most of Linux's drivers.
  202. * XXX ehs: Should this happen in PCI Device mode?
  203. */
  204. io_map_base = ioremap(A_PHYS_LDTPCI_IO_MATCH_BYTES, 1024 * 1024);
  205. sb1250_controller.io_map_base = (unsigned long)io_map_base;
  206. set_io_port_base((unsigned long)io_map_base);
  207. #ifdef CONFIG_SIBYTE_HAS_LDT
  208. /*
  209. * Also check the LDT bridge's enable, just in case we didn't
  210. * initialize that one.
  211. */
  212. cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(LDT_BRIDGE_DEVICE, 0),
  213. PCI_COMMAND));
  214. if (cmdreg & PCI_COMMAND_MASTER) {
  215. sb1250_bus_status |= LDT_BUS_ENABLED;
  216. /*
  217. * Need bits 23:16 to convey vector number. Note that
  218. * this consumes 4MB of kernel-mapped memory
  219. * (Kseg2/Kseg3) for 32-bit kernel.
  220. */
  221. ldt_eoi_space = (unsigned long)
  222. ioremap(A_PHYS_LDT_SPECIAL_MATCH_BYTES,
  223. 4 * 1024 * 1024);
  224. }
  225. #endif
  226. register_pci_controller(&sb1250_controller);
  227. #ifdef CONFIG_VGA_CONSOLE
  228. console_lock();
  229. do_take_over_console(&vga_con, 0, MAX_NR_CONSOLES - 1, 1);
  230. console_unlock();
  231. #endif
  232. return 0;
  233. }
  234. arch_initcall(sb1250_pcibios_init);