pci-rt3883.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Ralink RT3662/RT3883 SoC PCI support
  4. *
  5. * Copyright (C) 2011-2013 Gabor Juhos <[email protected]>
  6. *
  7. * Parts of this file are based on Ralink's 2.6.21 BSP
  8. */
  9. #include <linux/types.h>
  10. #include <linux/pci.h>
  11. #include <linux/io.h>
  12. #include <linux/init.h>
  13. #include <linux/delay.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/irqdomain.h>
  16. #include <linux/of.h>
  17. #include <linux/of_irq.h>
  18. #include <linux/of_pci.h>
  19. #include <linux/platform_device.h>
  20. #include <asm/mach-ralink/rt3883.h>
  21. #include <asm/mach-ralink/ralink_regs.h>
  22. #define RT3883_MEMORY_BASE 0x00000000
  23. #define RT3883_MEMORY_SIZE 0x02000000
  24. #define RT3883_PCI_REG_PCICFG 0x00
  25. #define RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf
  26. #define RT3883_PCICFG_P2P_BR_DEVNUM_S 16
  27. #define RT3883_PCICFG_PCIRST BIT(1)
  28. #define RT3883_PCI_REG_PCIRAW 0x04
  29. #define RT3883_PCI_REG_PCIINT 0x08
  30. #define RT3883_PCI_REG_PCIENA 0x0c
  31. #define RT3883_PCI_REG_CFGADDR 0x20
  32. #define RT3883_PCI_REG_CFGDATA 0x24
  33. #define RT3883_PCI_REG_MEMBASE 0x28
  34. #define RT3883_PCI_REG_IOBASE 0x2c
  35. #define RT3883_PCI_REG_ARBCTL 0x80
  36. #define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000)
  37. #define RT3883_PCI_REG_BAR0SETUP(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10)
  38. #define RT3883_PCI_REG_IMBASEBAR0(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18)
  39. #define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30)
  40. #define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34)
  41. #define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38)
  42. #define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50)
  43. #define RT3883_PCI_MODE_NONE 0
  44. #define RT3883_PCI_MODE_PCI BIT(0)
  45. #define RT3883_PCI_MODE_PCIE BIT(1)
  46. #define RT3883_PCI_MODE_BOTH (RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE)
  47. #define RT3883_PCI_IRQ_COUNT 32
  48. #define RT3883_P2P_BR_DEVNUM 1
  49. struct rt3883_pci_controller {
  50. void __iomem *base;
  51. struct device_node *intc_of_node;
  52. struct irq_domain *irq_domain;
  53. struct pci_controller pci_controller;
  54. struct resource io_res;
  55. struct resource mem_res;
  56. bool pcie_ready;
  57. };
  58. static inline struct rt3883_pci_controller *
  59. pci_bus_to_rt3883_controller(struct pci_bus *bus)
  60. {
  61. struct pci_controller *hose;
  62. hose = (struct pci_controller *) bus->sysdata;
  63. return container_of(hose, struct rt3883_pci_controller, pci_controller);
  64. }
  65. static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc,
  66. unsigned reg)
  67. {
  68. return ioread32(rpc->base + reg);
  69. }
  70. static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc,
  71. u32 val, unsigned reg)
  72. {
  73. iowrite32(val, rpc->base + reg);
  74. }
  75. static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
  76. unsigned int func, unsigned int where)
  77. {
  78. return (bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
  79. 0x80000000;
  80. }
  81. static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc,
  82. unsigned bus, unsigned slot,
  83. unsigned func, unsigned reg)
  84. {
  85. u32 address;
  86. address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
  87. rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
  88. return rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
  89. }
  90. static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc,
  91. unsigned bus, unsigned slot,
  92. unsigned func, unsigned reg, u32 val)
  93. {
  94. u32 address;
  95. address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
  96. rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
  97. rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA);
  98. }
  99. static void rt3883_pci_irq_handler(struct irq_desc *desc)
  100. {
  101. struct rt3883_pci_controller *rpc;
  102. u32 pending;
  103. rpc = irq_desc_get_handler_data(desc);
  104. pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) &
  105. rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
  106. if (!pending) {
  107. spurious_interrupt();
  108. return;
  109. }
  110. while (pending) {
  111. unsigned bit = __ffs(pending);
  112. generic_handle_domain_irq(rpc->irq_domain, bit);
  113. pending &= ~BIT(bit);
  114. }
  115. }
  116. static void rt3883_pci_irq_unmask(struct irq_data *d)
  117. {
  118. struct rt3883_pci_controller *rpc;
  119. u32 t;
  120. rpc = irq_data_get_irq_chip_data(d);
  121. t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
  122. rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
  123. /* flush write */
  124. rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
  125. }
  126. static void rt3883_pci_irq_mask(struct irq_data *d)
  127. {
  128. struct rt3883_pci_controller *rpc;
  129. u32 t;
  130. rpc = irq_data_get_irq_chip_data(d);
  131. t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
  132. rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
  133. /* flush write */
  134. rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
  135. }
  136. static struct irq_chip rt3883_pci_irq_chip = {
  137. .name = "RT3883 PCI",
  138. .irq_mask = rt3883_pci_irq_mask,
  139. .irq_unmask = rt3883_pci_irq_unmask,
  140. .irq_mask_ack = rt3883_pci_irq_mask,
  141. };
  142. static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq,
  143. irq_hw_number_t hw)
  144. {
  145. irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq);
  146. irq_set_chip_data(irq, d->host_data);
  147. return 0;
  148. }
  149. static const struct irq_domain_ops rt3883_pci_irq_domain_ops = {
  150. .map = rt3883_pci_irq_map,
  151. .xlate = irq_domain_xlate_onecell,
  152. };
  153. static int rt3883_pci_irq_init(struct device *dev,
  154. struct rt3883_pci_controller *rpc)
  155. {
  156. int irq;
  157. irq = irq_of_parse_and_map(rpc->intc_of_node, 0);
  158. if (irq == 0) {
  159. dev_err(dev, "%pOF has no IRQ", rpc->intc_of_node);
  160. return -EINVAL;
  161. }
  162. /* disable all interrupts */
  163. rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA);
  164. rpc->irq_domain =
  165. irq_domain_add_linear(rpc->intc_of_node, RT3883_PCI_IRQ_COUNT,
  166. &rt3883_pci_irq_domain_ops,
  167. rpc);
  168. if (!rpc->irq_domain) {
  169. dev_err(dev, "unable to add IRQ domain\n");
  170. return -ENODEV;
  171. }
  172. irq_set_chained_handler_and_data(irq, rt3883_pci_irq_handler, rpc);
  173. return 0;
  174. }
  175. static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
  176. int where, int size, u32 *val)
  177. {
  178. struct rt3883_pci_controller *rpc;
  179. u32 address;
  180. u32 data;
  181. rpc = pci_bus_to_rt3883_controller(bus);
  182. if (!rpc->pcie_ready && bus->number == 1)
  183. return PCIBIOS_DEVICE_NOT_FOUND;
  184. address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
  185. PCI_FUNC(devfn), where);
  186. rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
  187. data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
  188. switch (size) {
  189. case 1:
  190. *val = (data >> ((where & 3) << 3)) & 0xff;
  191. break;
  192. case 2:
  193. *val = (data >> ((where & 3) << 3)) & 0xffff;
  194. break;
  195. case 4:
  196. *val = data;
  197. break;
  198. }
  199. return PCIBIOS_SUCCESSFUL;
  200. }
  201. static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
  202. int where, int size, u32 val)
  203. {
  204. struct rt3883_pci_controller *rpc;
  205. u32 address;
  206. u32 data;
  207. rpc = pci_bus_to_rt3883_controller(bus);
  208. if (!rpc->pcie_ready && bus->number == 1)
  209. return PCIBIOS_DEVICE_NOT_FOUND;
  210. address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
  211. PCI_FUNC(devfn), where);
  212. rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
  213. data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
  214. switch (size) {
  215. case 1:
  216. data = (data & ~(0xff << ((where & 3) << 3))) |
  217. (val << ((where & 3) << 3));
  218. break;
  219. case 2:
  220. data = (data & ~(0xffff << ((where & 3) << 3))) |
  221. (val << ((where & 3) << 3));
  222. break;
  223. case 4:
  224. data = val;
  225. break;
  226. }
  227. rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA);
  228. return PCIBIOS_SUCCESSFUL;
  229. }
  230. static struct pci_ops rt3883_pci_ops = {
  231. .read = rt3883_pci_config_read,
  232. .write = rt3883_pci_config_write,
  233. };
  234. static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode)
  235. {
  236. u32 syscfg1;
  237. u32 rstctrl;
  238. u32 clkcfg1;
  239. u32 t;
  240. rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
  241. syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
  242. clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
  243. if (mode & RT3883_PCI_MODE_PCIE) {
  244. rstctrl |= RT3883_RSTCTRL_PCIE;
  245. rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
  246. /* setup PCI PAD drive mode */
  247. syscfg1 &= ~(0x30);
  248. syscfg1 |= (2 << 4);
  249. rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
  250. t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
  251. t &= ~BIT(31);
  252. rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
  253. t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
  254. t &= 0x80ffffff;
  255. rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
  256. t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
  257. t |= 0xa << 24;
  258. rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
  259. t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
  260. t |= BIT(31);
  261. rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
  262. msleep(50);
  263. rstctrl &= ~RT3883_RSTCTRL_PCIE;
  264. rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
  265. }
  266. syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE);
  267. clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN);
  268. if (mode & RT3883_PCI_MODE_PCI) {
  269. clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
  270. rstctrl &= ~RT3883_RSTCTRL_PCI;
  271. }
  272. if (mode & RT3883_PCI_MODE_PCIE) {
  273. clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
  274. rstctrl &= ~RT3883_RSTCTRL_PCIE;
  275. }
  276. rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
  277. rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
  278. rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
  279. msleep(500);
  280. /*
  281. * setup the device number of the P2P bridge
  282. * and de-assert the reset line
  283. */
  284. t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S);
  285. rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG);
  286. /* flush write */
  287. rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG);
  288. msleep(500);
  289. if (mode & RT3883_PCI_MODE_PCIE) {
  290. msleep(500);
  291. t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1));
  292. rpc->pcie_ready = t & BIT(0);
  293. if (!rpc->pcie_ready) {
  294. /* reset the PCIe block */
  295. t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
  296. t |= RT3883_RSTCTRL_PCIE;
  297. rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
  298. t &= ~RT3883_RSTCTRL_PCIE;
  299. rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
  300. /* turn off PCIe clock */
  301. t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
  302. t &= ~RT3883_CLKCFG1_PCIE_CLK_EN;
  303. rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1);
  304. t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
  305. t &= ~0xf000c080;
  306. rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
  307. }
  308. }
  309. /* enable PCI arbiter */
  310. rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL);
  311. }
  312. static int rt3883_pci_probe(struct platform_device *pdev)
  313. {
  314. struct rt3883_pci_controller *rpc;
  315. struct device *dev = &pdev->dev;
  316. struct device_node *np = dev->of_node;
  317. struct resource *res;
  318. struct device_node *child;
  319. u32 val;
  320. int err;
  321. int mode;
  322. rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL);
  323. if (!rpc)
  324. return -ENOMEM;
  325. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  326. rpc->base = devm_ioremap_resource(dev, res);
  327. if (IS_ERR(rpc->base))
  328. return PTR_ERR(rpc->base);
  329. /* find the interrupt controller child node */
  330. for_each_child_of_node(np, child) {
  331. if (of_get_property(child, "interrupt-controller", NULL)) {
  332. rpc->intc_of_node = child;
  333. break;
  334. }
  335. }
  336. if (!rpc->intc_of_node) {
  337. dev_err(dev, "%pOF has no %s child node",
  338. np, "interrupt controller");
  339. return -EINVAL;
  340. }
  341. /* find the PCI host bridge child node */
  342. for_each_child_of_node(np, child) {
  343. if (of_node_is_type(child, "pci")) {
  344. rpc->pci_controller.of_node = child;
  345. break;
  346. }
  347. }
  348. if (!rpc->pci_controller.of_node) {
  349. dev_err(dev, "%pOF has no %s child node",
  350. np, "PCI host bridge");
  351. err = -EINVAL;
  352. goto err_put_intc_node;
  353. }
  354. mode = RT3883_PCI_MODE_NONE;
  355. for_each_available_child_of_node(rpc->pci_controller.of_node, child) {
  356. int devfn;
  357. if (!of_node_is_type(child, "pci"))
  358. continue;
  359. devfn = of_pci_get_devfn(child);
  360. if (devfn < 0)
  361. continue;
  362. switch (PCI_SLOT(devfn)) {
  363. case 1:
  364. mode |= RT3883_PCI_MODE_PCIE;
  365. break;
  366. case 17:
  367. case 18:
  368. mode |= RT3883_PCI_MODE_PCI;
  369. break;
  370. }
  371. }
  372. if (mode == RT3883_PCI_MODE_NONE) {
  373. dev_err(dev, "unable to determine PCI mode\n");
  374. err = -EINVAL;
  375. goto err_put_hb_node;
  376. }
  377. dev_info(dev, "mode:%s%s\n",
  378. (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "",
  379. (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : "");
  380. rt3883_pci_preinit(rpc, mode);
  381. rpc->pci_controller.pci_ops = &rt3883_pci_ops;
  382. rpc->pci_controller.io_resource = &rpc->io_res;
  383. rpc->pci_controller.mem_resource = &rpc->mem_res;
  384. /* Load PCI I/O and memory resources from DT */
  385. pci_load_of_ranges(&rpc->pci_controller,
  386. rpc->pci_controller.of_node);
  387. rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE);
  388. rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE);
  389. ioport_resource.start = rpc->io_res.start;
  390. ioport_resource.end = rpc->io_res.end;
  391. /* PCI */
  392. rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0));
  393. rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0));
  394. rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0));
  395. rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0));
  396. rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0));
  397. /* PCIe */
  398. rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1));
  399. rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1));
  400. rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1));
  401. rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1));
  402. rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1));
  403. err = rt3883_pci_irq_init(dev, rpc);
  404. if (err)
  405. goto err_put_hb_node;
  406. /* PCIe */
  407. val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND);
  408. val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
  409. rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val);
  410. /* PCI */
  411. val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND);
  412. val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
  413. rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val);
  414. if (mode == RT3883_PCI_MODE_PCIE) {
  415. rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0));
  416. rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1));
  417. rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
  418. PCI_BASE_ADDRESS_0,
  419. RT3883_MEMORY_BASE);
  420. /* flush write */
  421. rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
  422. PCI_BASE_ADDRESS_0);
  423. } else {
  424. rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
  425. PCI_IO_BASE, 0x00000101);
  426. }
  427. register_pci_controller(&rpc->pci_controller);
  428. return 0;
  429. err_put_hb_node:
  430. of_node_put(rpc->pci_controller.of_node);
  431. err_put_intc_node:
  432. of_node_put(rpc->intc_of_node);
  433. return err;
  434. }
  435. int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  436. {
  437. return of_irq_parse_and_map_pci(dev, slot, pin);
  438. }
  439. int pcibios_plat_dev_init(struct pci_dev *dev)
  440. {
  441. return 0;
  442. }
  443. static const struct of_device_id rt3883_pci_ids[] = {
  444. { .compatible = "ralink,rt3883-pci" },
  445. {},
  446. };
  447. static struct platform_driver rt3883_pci_driver = {
  448. .probe = rt3883_pci_probe,
  449. .driver = {
  450. .name = "rt3883-pci",
  451. .of_match_table = of_match_ptr(rt3883_pci_ids),
  452. },
  453. };
  454. static int __init rt3883_pci_init(void)
  455. {
  456. return platform_driver_register(&rt3883_pci_driver);
  457. }
  458. postcore_initcall(rt3883_pci_init);