pci-rt2880.c 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Ralink RT288x SoC PCI register definitions
  4. *
  5. * Copyright (C) 2009 John Crispin <[email protected]>
  6. * Copyright (C) 2009 Gabor Juhos <[email protected]>
  7. *
  8. * Parts of this file are based on Ralink's 2.6.21 BSP
  9. */
  10. #include <linux/delay.h>
  11. #include <linux/types.h>
  12. #include <linux/pci.h>
  13. #include <linux/io.h>
  14. #include <linux/init.h>
  15. #include <linux/of_platform.h>
  16. #include <linux/of_irq.h>
  17. #include <linux/of_pci.h>
  18. #include <asm/mach-ralink/rt288x.h>
  19. #define RT2880_PCI_BASE 0x00440000
  20. #define RT288X_CPU_IRQ_PCI 4
  21. #define RT2880_PCI_MEM_BASE 0x20000000
  22. #define RT2880_PCI_MEM_SIZE 0x10000000
  23. #define RT2880_PCI_IO_BASE 0x00460000
  24. #define RT2880_PCI_IO_SIZE 0x00010000
  25. #define RT2880_PCI_REG_PCICFG_ADDR 0x00
  26. #define RT2880_PCI_REG_PCIMSK_ADDR 0x0c
  27. #define RT2880_PCI_REG_BAR0SETUP_ADDR 0x10
  28. #define RT2880_PCI_REG_IMBASEBAR0_ADDR 0x18
  29. #define RT2880_PCI_REG_CONFIG_ADDR 0x20
  30. #define RT2880_PCI_REG_CONFIG_DATA 0x24
  31. #define RT2880_PCI_REG_MEMBASE 0x28
  32. #define RT2880_PCI_REG_IOBASE 0x2c
  33. #define RT2880_PCI_REG_ID 0x30
  34. #define RT2880_PCI_REG_CLASS 0x34
  35. #define RT2880_PCI_REG_SUBID 0x38
  36. #define RT2880_PCI_REG_ARBCTL 0x80
  37. static void __iomem *rt2880_pci_base;
  38. static u32 rt2880_pci_reg_read(u32 reg)
  39. {
  40. return readl(rt2880_pci_base + reg);
  41. }
  42. static void rt2880_pci_reg_write(u32 val, u32 reg)
  43. {
  44. writel(val, rt2880_pci_base + reg);
  45. }
  46. static inline u32 rt2880_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
  47. unsigned int func, unsigned int where)
  48. {
  49. return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
  50. 0x80000000);
  51. }
  52. static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn,
  53. int where, int size, u32 *val)
  54. {
  55. u32 address;
  56. u32 data;
  57. address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
  58. PCI_FUNC(devfn), where);
  59. rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
  60. data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
  61. switch (size) {
  62. case 1:
  63. *val = (data >> ((where & 3) << 3)) & 0xff;
  64. break;
  65. case 2:
  66. *val = (data >> ((where & 3) << 3)) & 0xffff;
  67. break;
  68. case 4:
  69. *val = data;
  70. break;
  71. }
  72. return PCIBIOS_SUCCESSFUL;
  73. }
  74. static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn,
  75. int where, int size, u32 val)
  76. {
  77. u32 address;
  78. u32 data;
  79. address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
  80. PCI_FUNC(devfn), where);
  81. rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
  82. data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
  83. switch (size) {
  84. case 1:
  85. data = (data & ~(0xff << ((where & 3) << 3))) |
  86. (val << ((where & 3) << 3));
  87. break;
  88. case 2:
  89. data = (data & ~(0xffff << ((where & 3) << 3))) |
  90. (val << ((where & 3) << 3));
  91. break;
  92. case 4:
  93. data = val;
  94. break;
  95. }
  96. rt2880_pci_reg_write(data, RT2880_PCI_REG_CONFIG_DATA);
  97. return PCIBIOS_SUCCESSFUL;
  98. }
  99. static struct pci_ops rt2880_pci_ops = {
  100. .read = rt2880_pci_config_read,
  101. .write = rt2880_pci_config_write,
  102. };
  103. static struct resource rt2880_pci_mem_resource = {
  104. .name = "PCI MEM space",
  105. .start = RT2880_PCI_MEM_BASE,
  106. .end = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1,
  107. .flags = IORESOURCE_MEM,
  108. };
  109. static struct resource rt2880_pci_io_resource = {
  110. .name = "PCI IO space",
  111. .start = RT2880_PCI_IO_BASE,
  112. .end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1,
  113. .flags = IORESOURCE_IO,
  114. };
  115. static struct pci_controller rt2880_pci_controller = {
  116. .pci_ops = &rt2880_pci_ops,
  117. .mem_resource = &rt2880_pci_mem_resource,
  118. .io_resource = &rt2880_pci_io_resource,
  119. };
  120. static inline u32 rt2880_pci_read_u32(unsigned long reg)
  121. {
  122. u32 address;
  123. u32 ret;
  124. address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
  125. rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
  126. ret = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
  127. return ret;
  128. }
  129. static inline void rt2880_pci_write_u32(unsigned long reg, u32 val)
  130. {
  131. u32 address;
  132. address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
  133. rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
  134. rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA);
  135. }
  136. int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  137. {
  138. int irq = -1;
  139. if (dev->bus->number != 0)
  140. return irq;
  141. switch (PCI_SLOT(dev->devfn)) {
  142. case 0x00:
  143. break;
  144. case 0x11:
  145. irq = RT288X_CPU_IRQ_PCI;
  146. break;
  147. default:
  148. pr_err("%s:%s[%d] trying to alloc unknown pci irq\n",
  149. __FILE__, __func__, __LINE__);
  150. BUG();
  151. break;
  152. }
  153. return irq;
  154. }
  155. static int rt288x_pci_probe(struct platform_device *pdev)
  156. {
  157. void __iomem *io_map_base;
  158. rt2880_pci_base = ioremap(RT2880_PCI_BASE, PAGE_SIZE);
  159. io_map_base = ioremap(RT2880_PCI_IO_BASE, RT2880_PCI_IO_SIZE);
  160. rt2880_pci_controller.io_map_base = (unsigned long) io_map_base;
  161. set_io_port_base((unsigned long) io_map_base);
  162. ioport_resource.start = RT2880_PCI_IO_BASE;
  163. ioport_resource.end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1;
  164. rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR);
  165. udelay(1);
  166. rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);
  167. rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);
  168. rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE);
  169. rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE);
  170. rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR);
  171. rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID);
  172. rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);
  173. rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID);
  174. rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR);
  175. rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
  176. (void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
  177. rt2880_pci_controller.of_node = pdev->dev.of_node;
  178. register_pci_controller(&rt2880_pci_controller);
  179. return 0;
  180. }
  181. int pcibios_plat_dev_init(struct pci_dev *dev)
  182. {
  183. static bool slot0_init;
  184. /*
  185. * Nobody seems to initialize slot 0, but this platform requires it, so
  186. * do it once when some other slot is being enabled. The PCI subsystem
  187. * should configure other slots properly, so no need to do anything
  188. * special for those.
  189. */
  190. if (!slot0_init && dev->bus->number == 0) {
  191. u16 cmd;
  192. u32 bar0;
  193. slot0_init = true;
  194. pci_bus_write_config_dword(dev->bus, 0, PCI_BASE_ADDRESS_0,
  195. 0x08000000);
  196. pci_bus_read_config_dword(dev->bus, 0, PCI_BASE_ADDRESS_0,
  197. &bar0);
  198. pci_bus_read_config_word(dev->bus, 0, PCI_COMMAND, &cmd);
  199. cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
  200. pci_bus_write_config_word(dev->bus, 0, PCI_COMMAND, cmd);
  201. }
  202. return 0;
  203. }
  204. static const struct of_device_id rt288x_pci_match[] = {
  205. { .compatible = "ralink,rt288x-pci" },
  206. {},
  207. };
  208. static struct platform_driver rt288x_pci_driver = {
  209. .probe = rt288x_pci_probe,
  210. .driver = {
  211. .name = "rt288x-pci",
  212. .of_match_table = rt288x_pci_match,
  213. },
  214. };
  215. int __init pcibios_init(void)
  216. {
  217. int ret = platform_driver_register(&rt288x_pci_driver);
  218. if (ret)
  219. pr_info("rt288x-pci: Error registering platform driver!");
  220. return ret;
  221. }
  222. arch_initcall(pcibios_init);