pci-mt7620.c 9.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Ralink MT7620A SoC PCI support
  4. *
  5. * Copyright (C) 2007-2013 Bruce Chang (Mediatek)
  6. * Copyright (C) 2013-2016 John Crispin <[email protected]>
  7. */
  8. #include <linux/types.h>
  9. #include <linux/pci.h>
  10. #include <linux/io.h>
  11. #include <linux/init.h>
  12. #include <linux/delay.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/of.h>
  15. #include <linux/of_irq.h>
  16. #include <linux/of_pci.h>
  17. #include <linux/reset.h>
  18. #include <linux/platform_device.h>
  19. #include <asm/mach-ralink/ralink_regs.h>
  20. #include <asm/mach-ralink/mt7620.h>
  21. #define RALINK_PCI_IO_MAP_BASE 0x10160000
  22. #define RALINK_PCI_MEMORY_BASE 0x0
  23. #define RALINK_INT_PCIE0 4
  24. #define RALINK_CLKCFG1 0x30
  25. #define RALINK_GPIOMODE 0x60
  26. #define PPLL_CFG1 0x9c
  27. #define PPLL_LD BIT(23)
  28. #define PPLL_DRV 0xa0
  29. #define PDRV_SW_SET BIT(31)
  30. #define LC_CKDRVPD BIT(19)
  31. #define LC_CKDRVOHZ BIT(18)
  32. #define LC_CKDRVHZ BIT(17)
  33. #define LC_CKTEST BIT(16)
  34. /* PCI Bridge registers */
  35. #define RALINK_PCI_PCICFG_ADDR 0x00
  36. #define PCIRST BIT(1)
  37. #define RALINK_PCI_PCIENA 0x0C
  38. #define PCIINT2 BIT(20)
  39. #define RALINK_PCI_CONFIG_ADDR 0x20
  40. #define RALINK_PCI_CONFIG_DATA_VIRT_REG 0x24
  41. #define RALINK_PCI_MEMBASE 0x28
  42. #define RALINK_PCI_IOBASE 0x2C
  43. /* PCI RC registers */
  44. #define RALINK_PCI0_BAR0SETUP_ADDR 0x10
  45. #define RALINK_PCI0_IMBASEBAR0_ADDR 0x18
  46. #define RALINK_PCI0_ID 0x30
  47. #define RALINK_PCI0_CLASS 0x34
  48. #define RALINK_PCI0_SUBID 0x38
  49. #define RALINK_PCI0_STATUS 0x50
  50. #define PCIE_LINK_UP_ST BIT(0)
  51. #define PCIEPHY0_CFG 0x90
  52. #define RALINK_PCIEPHY_P0_CTL_OFFSET 0x7498
  53. #define RALINK_PCIE0_CLK_EN BIT(26)
  54. #define BUSY 0x80000000
  55. #define WAITRETRY_MAX 10
  56. #define WRITE_MODE (1UL << 23)
  57. #define DATA_SHIFT 0
  58. #define ADDR_SHIFT 8
  59. static void __iomem *bridge_base;
  60. static void __iomem *pcie_base;
  61. static struct reset_control *rstpcie0;
  62. static inline void bridge_w32(u32 val, unsigned reg)
  63. {
  64. iowrite32(val, bridge_base + reg);
  65. }
  66. static inline u32 bridge_r32(unsigned reg)
  67. {
  68. return ioread32(bridge_base + reg);
  69. }
  70. static inline void pcie_w32(u32 val, unsigned reg)
  71. {
  72. iowrite32(val, pcie_base + reg);
  73. }
  74. static inline u32 pcie_r32(unsigned reg)
  75. {
  76. return ioread32(pcie_base + reg);
  77. }
  78. static inline void pcie_m32(u32 clr, u32 set, unsigned reg)
  79. {
  80. u32 val = pcie_r32(reg);
  81. val &= ~clr;
  82. val |= set;
  83. pcie_w32(val, reg);
  84. }
  85. static int wait_pciephy_busy(void)
  86. {
  87. unsigned long reg_value = 0x0, retry = 0;
  88. while (1) {
  89. reg_value = pcie_r32(PCIEPHY0_CFG);
  90. if (reg_value & BUSY)
  91. mdelay(100);
  92. else
  93. break;
  94. if (retry++ > WAITRETRY_MAX) {
  95. pr_warn("PCIE-PHY retry failed.\n");
  96. return -1;
  97. }
  98. }
  99. return 0;
  100. }
  101. static void pcie_phy(unsigned long addr, unsigned long val)
  102. {
  103. wait_pciephy_busy();
  104. pcie_w32(WRITE_MODE | (val << DATA_SHIFT) | (addr << ADDR_SHIFT),
  105. PCIEPHY0_CFG);
  106. mdelay(1);
  107. wait_pciephy_busy();
  108. }
  109. static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
  110. int size, u32 *val)
  111. {
  112. unsigned int slot = PCI_SLOT(devfn);
  113. u8 func = PCI_FUNC(devfn);
  114. u32 address;
  115. u32 data;
  116. u32 num = 0;
  117. if (bus)
  118. num = bus->number;
  119. address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) |
  120. (func << 8) | (where & 0xfc) | 0x80000000;
  121. bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
  122. data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
  123. switch (size) {
  124. case 1:
  125. *val = (data >> ((where & 3) << 3)) & 0xff;
  126. break;
  127. case 2:
  128. *val = (data >> ((where & 3) << 3)) & 0xffff;
  129. break;
  130. case 4:
  131. *val = data;
  132. break;
  133. }
  134. return PCIBIOS_SUCCESSFUL;
  135. }
  136. static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
  137. int size, u32 val)
  138. {
  139. unsigned int slot = PCI_SLOT(devfn);
  140. u8 func = PCI_FUNC(devfn);
  141. u32 address;
  142. u32 data;
  143. u32 num = 0;
  144. if (bus)
  145. num = bus->number;
  146. address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) |
  147. (func << 8) | (where & 0xfc) | 0x80000000;
  148. bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
  149. data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
  150. switch (size) {
  151. case 1:
  152. data = (data & ~(0xff << ((where & 3) << 3))) |
  153. (val << ((where & 3) << 3));
  154. break;
  155. case 2:
  156. data = (data & ~(0xffff << ((where & 3) << 3))) |
  157. (val << ((where & 3) << 3));
  158. break;
  159. case 4:
  160. data = val;
  161. break;
  162. }
  163. bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRT_REG);
  164. return PCIBIOS_SUCCESSFUL;
  165. }
  166. struct pci_ops mt7620_pci_ops = {
  167. .read = pci_config_read,
  168. .write = pci_config_write,
  169. };
  170. static struct resource mt7620_res_pci_mem1;
  171. static struct resource mt7620_res_pci_io1;
  172. struct pci_controller mt7620_controller = {
  173. .pci_ops = &mt7620_pci_ops,
  174. .mem_resource = &mt7620_res_pci_mem1,
  175. .mem_offset = 0x00000000UL,
  176. .io_resource = &mt7620_res_pci_io1,
  177. .io_offset = 0x00000000UL,
  178. .io_map_base = 0xa0000000,
  179. };
  180. static int mt7620_pci_hw_init(struct platform_device *pdev)
  181. {
  182. /* bypass PCIe DLL */
  183. pcie_phy(0x0, 0x80);
  184. pcie_phy(0x1, 0x04);
  185. /* Elastic buffer control */
  186. pcie_phy(0x68, 0xB4);
  187. /* put core into reset */
  188. pcie_m32(0, PCIRST, RALINK_PCI_PCICFG_ADDR);
  189. reset_control_assert(rstpcie0);
  190. /* disable power and all clocks */
  191. rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
  192. rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
  193. /* bring core out of reset */
  194. reset_control_deassert(rstpcie0);
  195. rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
  196. mdelay(100);
  197. if (!(rt_sysc_r32(PPLL_CFG1) & PPLL_LD)) {
  198. dev_err(&pdev->dev, "pcie PLL not locked, aborting init\n");
  199. reset_control_assert(rstpcie0);
  200. rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
  201. return -1;
  202. }
  203. /* power up the bus */
  204. rt_sysc_m32(LC_CKDRVHZ | LC_CKDRVOHZ, LC_CKDRVPD | PDRV_SW_SET,
  205. PPLL_DRV);
  206. return 0;
  207. }
  208. static int mt7628_pci_hw_init(struct platform_device *pdev)
  209. {
  210. u32 val = 0;
  211. /* bring the core out of reset */
  212. rt_sysc_m32(BIT(16), 0, RALINK_GPIOMODE);
  213. reset_control_deassert(rstpcie0);
  214. /* enable the pci clk */
  215. rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
  216. mdelay(100);
  217. /* voodoo from the SDK driver */
  218. pcie_m32(~0xff, 0x5, RALINK_PCIEPHY_P0_CTL_OFFSET);
  219. pci_config_read(NULL, 0, 0x70c, 4, &val);
  220. val &= ~(0xff) << 8;
  221. val |= 0x50 << 8;
  222. pci_config_write(NULL, 0, 0x70c, 4, val);
  223. pci_config_read(NULL, 0, 0x70c, 4, &val);
  224. dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val);
  225. return 0;
  226. }
  227. static int mt7620_pci_probe(struct platform_device *pdev)
  228. {
  229. struct resource *bridge_res = platform_get_resource(pdev,
  230. IORESOURCE_MEM, 0);
  231. struct resource *pcie_res = platform_get_resource(pdev,
  232. IORESOURCE_MEM, 1);
  233. u32 val = 0;
  234. rstpcie0 = devm_reset_control_get_exclusive(&pdev->dev, "pcie0");
  235. if (IS_ERR(rstpcie0))
  236. return PTR_ERR(rstpcie0);
  237. bridge_base = devm_ioremap_resource(&pdev->dev, bridge_res);
  238. if (IS_ERR(bridge_base))
  239. return PTR_ERR(bridge_base);
  240. pcie_base = devm_ioremap_resource(&pdev->dev, pcie_res);
  241. if (IS_ERR(pcie_base))
  242. return PTR_ERR(pcie_base);
  243. iomem_resource.start = 0;
  244. iomem_resource.end = ~0;
  245. ioport_resource.start = 0;
  246. ioport_resource.end = ~0;
  247. /* bring up the pci core */
  248. switch (ralink_soc) {
  249. case MT762X_SOC_MT7620A:
  250. if (mt7620_pci_hw_init(pdev))
  251. return -1;
  252. break;
  253. case MT762X_SOC_MT7628AN:
  254. case MT762X_SOC_MT7688:
  255. if (mt7628_pci_hw_init(pdev))
  256. return -1;
  257. break;
  258. default:
  259. dev_err(&pdev->dev, "pcie is not supported on this hardware\n");
  260. return -1;
  261. }
  262. mdelay(50);
  263. /* enable write access */
  264. pcie_m32(PCIRST, 0, RALINK_PCI_PCICFG_ADDR);
  265. mdelay(100);
  266. /* check if there is a card present */
  267. if ((pcie_r32(RALINK_PCI0_STATUS) & PCIE_LINK_UP_ST) == 0) {
  268. reset_control_assert(rstpcie0);
  269. rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
  270. if (ralink_soc == MT762X_SOC_MT7620A)
  271. rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
  272. dev_err(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
  273. return -1;
  274. }
  275. /* setup ranges */
  276. bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);
  277. bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
  278. pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
  279. pcie_w32(RALINK_PCI_MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR);
  280. pcie_w32(0x06040001, RALINK_PCI0_CLASS);
  281. /* enable interrupts */
  282. pcie_m32(0, PCIINT2, RALINK_PCI_PCIENA);
  283. /* voodoo from the SDK driver */
  284. pci_config_read(NULL, 0, 4, 4, &val);
  285. pci_config_write(NULL, 0, 4, 4, val | 0x7);
  286. pci_load_of_ranges(&mt7620_controller, pdev->dev.of_node);
  287. register_pci_controller(&mt7620_controller);
  288. return 0;
  289. }
  290. int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  291. {
  292. u16 cmd;
  293. u32 val;
  294. int irq = 0;
  295. if ((dev->bus->number == 0) && (slot == 0)) {
  296. pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
  297. pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4,
  298. RALINK_PCI_MEMORY_BASE);
  299. pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
  300. } else if ((dev->bus->number == 1) && (slot == 0x0)) {
  301. irq = RALINK_INT_PCIE0;
  302. } else {
  303. dev_err(&dev->dev, "no irq found - bus=0x%x, slot = 0x%x\n",
  304. dev->bus->number, slot);
  305. return 0;
  306. }
  307. dev_err(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n",
  308. dev->bus->number, slot, irq);
  309. /* configure the cache line size to 0x14 */
  310. pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);
  311. /* configure latency timer to 0xff */
  312. pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xff);
  313. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  314. /* setup the slot */
  315. cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
  316. pci_write_config_word(dev, PCI_COMMAND, cmd);
  317. pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
  318. return irq;
  319. }
  320. int pcibios_plat_dev_init(struct pci_dev *dev)
  321. {
  322. return 0;
  323. }
  324. static const struct of_device_id mt7620_pci_ids[] = {
  325. { .compatible = "mediatek,mt7620-pci" },
  326. {},
  327. };
  328. static struct platform_driver mt7620_pci_driver = {
  329. .probe = mt7620_pci_probe,
  330. .driver = {
  331. .name = "mt7620-pci",
  332. .of_match_table = of_match_ptr(mt7620_pci_ids),
  333. },
  334. };
  335. static int __init mt7620_pci_init(void)
  336. {
  337. return platform_driver_register(&mt7620_pci_driver);
  338. }
  339. arch_initcall(mt7620_pci_init);