pci-legacy.c 7.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. *
  4. * Copyright (C) 2003, 04, 11 Ralf Baechle ([email protected])
  5. * Copyright (C) 2011 Wind River Systems,
  6. * written by Ralf Baechle ([email protected])
  7. */
  8. #include <linux/bug.h>
  9. #include <linux/kernel.h>
  10. #include <linux/mm.h>
  11. #include <linux/memblock.h>
  12. #include <linux/export.h>
  13. #include <linux/init.h>
  14. #include <linux/types.h>
  15. #include <linux/pci.h>
  16. #include <linux/of_address.h>
  17. #include <asm/cpu-info.h>
  18. /*
  19. * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
  20. * assignments.
  21. */
  22. /*
  23. * The PCI controller list.
  24. */
  25. static LIST_HEAD(controllers);
  26. static int pci_initialized;
  27. /*
  28. * We need to avoid collisions with `mirrored' VGA ports
  29. * and other strange ISA hardware, so we always want the
  30. * addresses to be allocated in the 0x000-0x0ff region
  31. * modulo 0x400.
  32. *
  33. * Why? Because some silly external IO cards only decode
  34. * the low 10 bits of the IO address. The 0x00-0xff region
  35. * is reserved for motherboard devices that decode all 16
  36. * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
  37. * but we want to try to avoid allocating at 0x2900-0x2bff
  38. * which might have be mirrored at 0x0100-0x03ff..
  39. */
  40. resource_size_t
  41. pcibios_align_resource(void *data, const struct resource *res,
  42. resource_size_t size, resource_size_t align)
  43. {
  44. struct pci_dev *dev = data;
  45. struct pci_controller *hose = dev->sysdata;
  46. resource_size_t start = res->start;
  47. if (res->flags & IORESOURCE_IO) {
  48. /* Make sure we start at our min on all hoses */
  49. if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
  50. start = PCIBIOS_MIN_IO + hose->io_resource->start;
  51. /*
  52. * Put everything into 0x00-0xff region modulo 0x400
  53. */
  54. if (start & 0x300)
  55. start = (start + 0x3ff) & ~0x3ff;
  56. } else if (res->flags & IORESOURCE_MEM) {
  57. /* Make sure we start at our min on all hoses */
  58. if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
  59. start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
  60. }
  61. return start;
  62. }
  63. static void pcibios_scanbus(struct pci_controller *hose)
  64. {
  65. static int next_busno;
  66. static int need_domain_info;
  67. LIST_HEAD(resources);
  68. struct pci_bus *bus;
  69. struct pci_host_bridge *bridge;
  70. int ret;
  71. bridge = pci_alloc_host_bridge(0);
  72. if (!bridge)
  73. return;
  74. if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
  75. next_busno = (*hose->get_busno)();
  76. pci_add_resource_offset(&resources,
  77. hose->mem_resource, hose->mem_offset);
  78. pci_add_resource_offset(&resources,
  79. hose->io_resource, hose->io_offset);
  80. list_splice_init(&resources, &bridge->windows);
  81. bridge->dev.parent = NULL;
  82. bridge->sysdata = hose;
  83. bridge->busnr = next_busno;
  84. bridge->ops = hose->pci_ops;
  85. bridge->swizzle_irq = pci_common_swizzle;
  86. bridge->map_irq = pcibios_map_irq;
  87. ret = pci_scan_root_bus_bridge(bridge);
  88. if (ret) {
  89. pci_free_host_bridge(bridge);
  90. return;
  91. }
  92. hose->bus = bus = bridge->bus;
  93. need_domain_info = need_domain_info || pci_domain_nr(bus);
  94. set_pci_need_domain_info(hose, need_domain_info);
  95. next_busno = bus->busn_res.end + 1;
  96. /* Don't allow 8-bit bus number overflow inside the hose -
  97. reserve some space for bridges. */
  98. if (next_busno > 224) {
  99. next_busno = 0;
  100. need_domain_info = 1;
  101. }
  102. /*
  103. * We insert PCI resources into the iomem_resource and
  104. * ioport_resource trees in either pci_bus_claim_resources()
  105. * or pci_bus_assign_resources().
  106. */
  107. if (pci_has_flag(PCI_PROBE_ONLY)) {
  108. pci_bus_claim_resources(bus);
  109. } else {
  110. struct pci_bus *child;
  111. pci_bus_size_bridges(bus);
  112. pci_bus_assign_resources(bus);
  113. list_for_each_entry(child, &bus->children, node)
  114. pcie_bus_configure_settings(child);
  115. }
  116. pci_bus_add_devices(bus);
  117. }
  118. #ifdef CONFIG_OF
  119. void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node)
  120. {
  121. struct of_pci_range range;
  122. struct of_pci_range_parser parser;
  123. hose->of_node = node;
  124. if (of_pci_range_parser_init(&parser, node))
  125. return;
  126. for_each_of_pci_range(&parser, &range) {
  127. struct resource *res = NULL;
  128. switch (range.flags & IORESOURCE_TYPE_BITS) {
  129. case IORESOURCE_IO:
  130. hose->io_map_base =
  131. (unsigned long)ioremap(range.cpu_addr,
  132. range.size);
  133. res = hose->io_resource;
  134. break;
  135. case IORESOURCE_MEM:
  136. res = hose->mem_resource;
  137. break;
  138. }
  139. if (res != NULL) {
  140. res->name = node->full_name;
  141. res->flags = range.flags;
  142. res->start = range.cpu_addr;
  143. res->end = range.cpu_addr + range.size - 1;
  144. res->parent = res->child = res->sibling = NULL;
  145. }
  146. }
  147. }
  148. struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
  149. {
  150. struct pci_controller *hose = bus->sysdata;
  151. return of_node_get(hose->of_node);
  152. }
  153. #endif
  154. static DEFINE_MUTEX(pci_scan_mutex);
  155. void register_pci_controller(struct pci_controller *hose)
  156. {
  157. struct resource *parent;
  158. parent = hose->mem_resource->parent;
  159. if (!parent)
  160. parent = &iomem_resource;
  161. if (request_resource(parent, hose->mem_resource) < 0)
  162. goto out;
  163. parent = hose->io_resource->parent;
  164. if (!parent)
  165. parent = &ioport_resource;
  166. if (request_resource(parent, hose->io_resource) < 0) {
  167. release_resource(hose->mem_resource);
  168. goto out;
  169. }
  170. INIT_LIST_HEAD(&hose->list);
  171. list_add_tail(&hose->list, &controllers);
  172. /*
  173. * Do not panic here but later - this might happen before console init.
  174. */
  175. if (!hose->io_map_base) {
  176. printk(KERN_WARNING
  177. "registering PCI controller with io_map_base unset\n");
  178. }
  179. /*
  180. * Scan the bus if it is register after the PCI subsystem
  181. * initialization.
  182. */
  183. if (pci_initialized) {
  184. mutex_lock(&pci_scan_mutex);
  185. pcibios_scanbus(hose);
  186. mutex_unlock(&pci_scan_mutex);
  187. }
  188. return;
  189. out:
  190. printk(KERN_WARNING
  191. "Skipping PCI bus scan due to resource conflict\n");
  192. }
  193. static int __init pcibios_init(void)
  194. {
  195. struct pci_controller *hose;
  196. /* Scan all of the recorded PCI controllers. */
  197. list_for_each_entry(hose, &controllers, list)
  198. pcibios_scanbus(hose);
  199. pci_initialized = 1;
  200. return 0;
  201. }
  202. subsys_initcall(pcibios_init);
  203. static int pcibios_enable_resources(struct pci_dev *dev, int mask)
  204. {
  205. u16 cmd, old_cmd;
  206. int idx;
  207. struct resource *r;
  208. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  209. old_cmd = cmd;
  210. for (idx = 0; idx < PCI_NUM_RESOURCES; idx++) {
  211. /* Only set up the requested stuff */
  212. if (!(mask & (1<<idx)))
  213. continue;
  214. r = &dev->resource[idx];
  215. if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
  216. continue;
  217. if ((idx == PCI_ROM_RESOURCE) &&
  218. (!(r->flags & IORESOURCE_ROM_ENABLE)))
  219. continue;
  220. if (!r->start && r->end) {
  221. pci_err(dev,
  222. "can't enable device: resource collisions\n");
  223. return -EINVAL;
  224. }
  225. if (r->flags & IORESOURCE_IO)
  226. cmd |= PCI_COMMAND_IO;
  227. if (r->flags & IORESOURCE_MEM)
  228. cmd |= PCI_COMMAND_MEMORY;
  229. }
  230. if (cmd != old_cmd) {
  231. pci_info(dev, "enabling device (%04x -> %04x)\n", old_cmd, cmd);
  232. pci_write_config_word(dev, PCI_COMMAND, cmd);
  233. }
  234. return 0;
  235. }
  236. int pcibios_enable_device(struct pci_dev *dev, int mask)
  237. {
  238. int err = pcibios_enable_resources(dev, mask);
  239. if (err < 0)
  240. return err;
  241. return pcibios_plat_dev_init(dev);
  242. }
  243. void pcibios_fixup_bus(struct pci_bus *bus)
  244. {
  245. struct pci_dev *dev = bus->self;
  246. if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
  247. (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
  248. pci_read_bridge_bases(bus);
  249. }
  250. }
  251. char * (*pcibios_plat_setup)(char *str) __initdata;
  252. char *__init pcibios_setup(char *str)
  253. {
  254. if (pcibios_plat_setup)
  255. return pcibios_plat_setup(str);
  256. return str;
  257. }