pci-lantiq.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. *
  4. * Copyright (C) 2010 John Crispin <[email protected]>
  5. */
  6. #include <linux/types.h>
  7. #include <linux/pci.h>
  8. #include <linux/kernel.h>
  9. #include <linux/init.h>
  10. #include <linux/delay.h>
  11. #include <linux/gpio/consumer.h>
  12. #include <linux/mm.h>
  13. #include <linux/vmalloc.h>
  14. #include <linux/clk.h>
  15. #include <linux/of_platform.h>
  16. #include <linux/of_irq.h>
  17. #include <linux/of_pci.h>
  18. #include <asm/addrspace.h>
  19. #include <lantiq_soc.h>
  20. #include <lantiq_irq.h>
  21. #include "pci-lantiq.h"
  22. #define PCI_CR_FCI_ADDR_MAP0 0x00C0
  23. #define PCI_CR_FCI_ADDR_MAP1 0x00C4
  24. #define PCI_CR_FCI_ADDR_MAP2 0x00C8
  25. #define PCI_CR_FCI_ADDR_MAP3 0x00CC
  26. #define PCI_CR_FCI_ADDR_MAP4 0x00D0
  27. #define PCI_CR_FCI_ADDR_MAP5 0x00D4
  28. #define PCI_CR_FCI_ADDR_MAP6 0x00D8
  29. #define PCI_CR_FCI_ADDR_MAP7 0x00DC
  30. #define PCI_CR_CLK_CTRL 0x0000
  31. #define PCI_CR_PCI_MOD 0x0030
  32. #define PCI_CR_PC_ARB 0x0080
  33. #define PCI_CR_FCI_ADDR_MAP11hg 0x00E4
  34. #define PCI_CR_BAR11MASK 0x0044
  35. #define PCI_CR_BAR12MASK 0x0048
  36. #define PCI_CR_BAR13MASK 0x004C
  37. #define PCI_CS_BASE_ADDR1 0x0010
  38. #define PCI_CR_PCI_ADDR_MAP11 0x0064
  39. #define PCI_CR_FCI_BURST_LENGTH 0x00E8
  40. #define PCI_CR_PCI_EOI 0x002C
  41. #define PCI_CS_STS_CMD 0x0004
  42. #define PCI_MASTER0_REQ_MASK_2BITS 8
  43. #define PCI_MASTER1_REQ_MASK_2BITS 10
  44. #define PCI_MASTER2_REQ_MASK_2BITS 12
  45. #define INTERNAL_ARB_ENABLE_BIT 0
  46. #define LTQ_CGU_IFCCR 0x0018
  47. #define LTQ_CGU_PCICR 0x0034
  48. #define ltq_pci_w32(x, y) ltq_w32((x), ltq_pci_membase + (y))
  49. #define ltq_pci_r32(x) ltq_r32(ltq_pci_membase + (x))
  50. #define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y))
  51. #define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x))
  52. __iomem void *ltq_pci_mapped_cfg;
  53. static __iomem void *ltq_pci_membase;
  54. static struct gpio_desc *reset_gpio;
  55. static struct clk *clk_pci, *clk_external;
  56. static struct resource pci_io_resource;
  57. static struct resource pci_mem_resource;
  58. static struct pci_ops pci_ops = {
  59. .read = ltq_pci_read_config_dword,
  60. .write = ltq_pci_write_config_dword
  61. };
  62. static struct pci_controller pci_controller = {
  63. .pci_ops = &pci_ops,
  64. .mem_resource = &pci_mem_resource,
  65. .mem_offset = 0x00000000UL,
  66. .io_resource = &pci_io_resource,
  67. .io_offset = 0x00000000UL,
  68. };
  69. static inline u32 ltq_calc_bar11mask(void)
  70. {
  71. u32 mem, bar11mask;
  72. /* BAR11MASK value depends on available memory on system. */
  73. mem = get_num_physpages() * PAGE_SIZE;
  74. bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8;
  75. return bar11mask;
  76. }
  77. static int ltq_pci_startup(struct platform_device *pdev)
  78. {
  79. struct device_node *node = pdev->dev.of_node;
  80. const __be32 *req_mask, *bus_clk;
  81. u32 temp_buffer;
  82. int error;
  83. /* get our clocks */
  84. clk_pci = clk_get(&pdev->dev, NULL);
  85. if (IS_ERR(clk_pci)) {
  86. dev_err(&pdev->dev, "failed to get pci clock\n");
  87. return PTR_ERR(clk_pci);
  88. }
  89. clk_external = clk_get(&pdev->dev, "external");
  90. if (IS_ERR(clk_external)) {
  91. clk_put(clk_pci);
  92. dev_err(&pdev->dev, "failed to get external pci clock\n");
  93. return PTR_ERR(clk_external);
  94. }
  95. /* read the bus speed that we want */
  96. bus_clk = of_get_property(node, "lantiq,bus-clock", NULL);
  97. if (bus_clk)
  98. clk_set_rate(clk_pci, *bus_clk);
  99. /* and enable the clocks */
  100. clk_enable(clk_pci);
  101. if (of_find_property(node, "lantiq,external-clock", NULL))
  102. clk_enable(clk_external);
  103. else
  104. clk_disable(clk_external);
  105. /* setup reset gpio used by pci */
  106. reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset",
  107. GPIOD_OUT_LOW);
  108. error = PTR_ERR_OR_ZERO(reset_gpio);
  109. if (error) {
  110. dev_err(&pdev->dev, "failed to request gpio: %d\n", error);
  111. return error;
  112. }
  113. gpiod_set_consumer_name(reset_gpio, "pci_reset");
  114. /* enable auto-switching between PCI and EBU */
  115. ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
  116. /* busy, i.e. configuration is not done, PCI access has to be retried */
  117. ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
  118. wmb();
  119. /* BUS Master/IO/MEM access */
  120. ltq_pci_cfg_w32(ltq_pci_cfg_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
  121. /* enable external 2 PCI masters */
  122. temp_buffer = ltq_pci_r32(PCI_CR_PC_ARB);
  123. /* setup the request mask */
  124. req_mask = of_get_property(node, "req-mask", NULL);
  125. if (req_mask)
  126. temp_buffer &= ~((*req_mask & 0xf) << 16);
  127. else
  128. temp_buffer &= ~0xf0000;
  129. /* enable internal arbiter */
  130. temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
  131. /* enable internal PCI master reqest */
  132. temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
  133. /* enable EBU request */
  134. temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
  135. /* enable all external masters request */
  136. temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
  137. ltq_pci_w32(temp_buffer, PCI_CR_PC_ARB);
  138. wmb();
  139. /* setup BAR memory regions */
  140. ltq_pci_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0);
  141. ltq_pci_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1);
  142. ltq_pci_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2);
  143. ltq_pci_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
  144. ltq_pci_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4);
  145. ltq_pci_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5);
  146. ltq_pci_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
  147. ltq_pci_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
  148. ltq_pci_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
  149. ltq_pci_w32(ltq_calc_bar11mask(), PCI_CR_BAR11MASK);
  150. ltq_pci_w32(0, PCI_CR_PCI_ADDR_MAP11);
  151. ltq_pci_w32(0, PCI_CS_BASE_ADDR1);
  152. /* both TX and RX endian swap are enabled */
  153. ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
  154. wmb();
  155. ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR12MASK) | 0x80000000,
  156. PCI_CR_BAR12MASK);
  157. ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR13MASK) | 0x80000000,
  158. PCI_CR_BAR13MASK);
  159. /*use 8 dw burst length */
  160. ltq_pci_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
  161. ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
  162. wmb();
  163. /* setup irq line */
  164. ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_CON) | 0xc, LTQ_EBU_PCC_CON);
  165. ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN);
  166. /* toggle reset pin */
  167. if (reset_gpio) {
  168. gpiod_set_value_cansleep(reset_gpio, 1);
  169. wmb();
  170. mdelay(1);
  171. gpiod_set_value_cansleep(reset_gpio, 0);
  172. }
  173. return 0;
  174. }
  175. static int ltq_pci_probe(struct platform_device *pdev)
  176. {
  177. struct resource *res_cfg, *res_bridge;
  178. pci_clear_flags(PCI_PROBE_ONLY);
  179. res_bridge = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  180. ltq_pci_membase = devm_ioremap_resource(&pdev->dev, res_bridge);
  181. if (IS_ERR(ltq_pci_membase))
  182. return PTR_ERR(ltq_pci_membase);
  183. res_cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  184. ltq_pci_mapped_cfg = devm_ioremap_resource(&pdev->dev, res_cfg);
  185. if (IS_ERR(ltq_pci_mapped_cfg))
  186. return PTR_ERR(ltq_pci_mapped_cfg);
  187. ltq_pci_startup(pdev);
  188. pci_load_of_ranges(&pci_controller, pdev->dev.of_node);
  189. register_pci_controller(&pci_controller);
  190. return 0;
  191. }
  192. static const struct of_device_id ltq_pci_match[] = {
  193. { .compatible = "lantiq,pci-xway" },
  194. {},
  195. };
  196. static struct platform_driver ltq_pci_driver = {
  197. .probe = ltq_pci_probe,
  198. .driver = {
  199. .name = "pci-xway",
  200. .of_match_table = ltq_pci_match,
  201. },
  202. };
  203. int __init pcibios_init(void)
  204. {
  205. int ret = platform_driver_register(&ltq_pci_driver);
  206. if (ret)
  207. pr_info("pci-xway: Error registering platform driver!");
  208. return ret;
  209. }
  210. arch_initcall(pcibios_init);