pci-ar71xx.c 9.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Atheros AR71xx PCI host controller driver
  4. *
  5. * Copyright (C) 2008-2011 Gabor Juhos <[email protected]>
  6. * Copyright (C) 2008 Imre Kaloz <[email protected]>
  7. *
  8. * Parts of this file are based on Atheros' 2.6.15 BSP
  9. */
  10. #include <linux/resource.h>
  11. #include <linux/types.h>
  12. #include <linux/delay.h>
  13. #include <linux/bitops.h>
  14. #include <linux/pci.h>
  15. #include <linux/pci_regs.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/init.h>
  18. #include <linux/platform_device.h>
  19. #include <asm/mach-ath79/ar71xx_regs.h>
  20. #include <asm/mach-ath79/ath79.h>
  21. #define AR71XX_PCI_REG_CRP_AD_CBE 0x00
  22. #define AR71XX_PCI_REG_CRP_WRDATA 0x04
  23. #define AR71XX_PCI_REG_CRP_RDDATA 0x08
  24. #define AR71XX_PCI_REG_CFG_AD 0x0c
  25. #define AR71XX_PCI_REG_CFG_CBE 0x10
  26. #define AR71XX_PCI_REG_CFG_WRDATA 0x14
  27. #define AR71XX_PCI_REG_CFG_RDDATA 0x18
  28. #define AR71XX_PCI_REG_PCI_ERR 0x1c
  29. #define AR71XX_PCI_REG_PCI_ERR_ADDR 0x20
  30. #define AR71XX_PCI_REG_AHB_ERR 0x24
  31. #define AR71XX_PCI_REG_AHB_ERR_ADDR 0x28
  32. #define AR71XX_PCI_CRP_CMD_WRITE 0x00010000
  33. #define AR71XX_PCI_CRP_CMD_READ 0x00000000
  34. #define AR71XX_PCI_CFG_CMD_READ 0x0000000a
  35. #define AR71XX_PCI_CFG_CMD_WRITE 0x0000000b
  36. #define AR71XX_PCI_INT_CORE BIT(4)
  37. #define AR71XX_PCI_INT_DEV2 BIT(2)
  38. #define AR71XX_PCI_INT_DEV1 BIT(1)
  39. #define AR71XX_PCI_INT_DEV0 BIT(0)
  40. #define AR71XX_PCI_IRQ_COUNT 5
  41. struct ar71xx_pci_controller {
  42. void __iomem *cfg_base;
  43. int irq;
  44. int irq_base;
  45. struct pci_controller pci_ctrl;
  46. struct resource io_res;
  47. struct resource mem_res;
  48. };
  49. /* Byte lane enable bits */
  50. static const u8 ar71xx_pci_ble_table[4][4] = {
  51. {0x0, 0xf, 0xf, 0xf},
  52. {0xe, 0xd, 0xb, 0x7},
  53. {0xc, 0xf, 0x3, 0xf},
  54. {0xf, 0xf, 0xf, 0xf},
  55. };
  56. static const u32 ar71xx_pci_read_mask[8] = {
  57. 0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0
  58. };
  59. static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
  60. {
  61. u32 t;
  62. t = ar71xx_pci_ble_table[size & 3][where & 3];
  63. BUG_ON(t == 0xf);
  64. t <<= (local) ? 20 : 4;
  65. return t;
  66. }
  67. static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn,
  68. int where)
  69. {
  70. u32 ret;
  71. if (!bus->number) {
  72. /* type 0 */
  73. ret = (1 << PCI_SLOT(devfn)) | (PCI_FUNC(devfn) << 8) |
  74. (where & ~3);
  75. } else {
  76. /* type 1 */
  77. ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11) |
  78. (PCI_FUNC(devfn) << 8) | (where & ~3) | 1;
  79. }
  80. return ret;
  81. }
  82. static inline struct ar71xx_pci_controller *
  83. pci_bus_to_ar71xx_controller(struct pci_bus *bus)
  84. {
  85. struct pci_controller *hose;
  86. hose = (struct pci_controller *) bus->sysdata;
  87. return container_of(hose, struct ar71xx_pci_controller, pci_ctrl);
  88. }
  89. static int ar71xx_pci_check_error(struct ar71xx_pci_controller *apc, int quiet)
  90. {
  91. void __iomem *base = apc->cfg_base;
  92. u32 pci_err;
  93. u32 ahb_err;
  94. pci_err = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR) & 3;
  95. if (pci_err) {
  96. if (!quiet) {
  97. u32 addr;
  98. addr = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR_ADDR);
  99. pr_crit("ar71xx: %s bus error %d at addr 0x%x\n",
  100. "PCI", pci_err, addr);
  101. }
  102. /* clear PCI error status */
  103. __raw_writel(pci_err, base + AR71XX_PCI_REG_PCI_ERR);
  104. }
  105. ahb_err = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR) & 1;
  106. if (ahb_err) {
  107. if (!quiet) {
  108. u32 addr;
  109. addr = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR_ADDR);
  110. pr_crit("ar71xx: %s bus error %d at addr 0x%x\n",
  111. "AHB", ahb_err, addr);
  112. }
  113. /* clear AHB error status */
  114. __raw_writel(ahb_err, base + AR71XX_PCI_REG_AHB_ERR);
  115. }
  116. return !!(ahb_err | pci_err);
  117. }
  118. static inline void ar71xx_pci_local_write(struct ar71xx_pci_controller *apc,
  119. int where, int size, u32 value)
  120. {
  121. void __iomem *base = apc->cfg_base;
  122. u32 ad_cbe;
  123. value = value << (8 * (where & 3));
  124. ad_cbe = AR71XX_PCI_CRP_CMD_WRITE | (where & ~3);
  125. ad_cbe |= ar71xx_pci_get_ble(where, size, 1);
  126. __raw_writel(ad_cbe, base + AR71XX_PCI_REG_CRP_AD_CBE);
  127. __raw_writel(value, base + AR71XX_PCI_REG_CRP_WRDATA);
  128. }
  129. static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
  130. unsigned int devfn,
  131. int where, int size, u32 cmd)
  132. {
  133. struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
  134. void __iomem *base = apc->cfg_base;
  135. u32 addr;
  136. addr = ar71xx_pci_bus_addr(bus, devfn, where);
  137. __raw_writel(addr, base + AR71XX_PCI_REG_CFG_AD);
  138. __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0),
  139. base + AR71XX_PCI_REG_CFG_CBE);
  140. return ar71xx_pci_check_error(apc, 1);
  141. }
  142. static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
  143. int where, int size, u32 *value)
  144. {
  145. struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
  146. void __iomem *base = apc->cfg_base;
  147. u32 data;
  148. int err;
  149. int ret;
  150. ret = PCIBIOS_SUCCESSFUL;
  151. data = ~0;
  152. err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
  153. AR71XX_PCI_CFG_CMD_READ);
  154. if (err)
  155. ret = PCIBIOS_DEVICE_NOT_FOUND;
  156. else
  157. data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA);
  158. *value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7];
  159. return ret;
  160. }
  161. static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
  162. int where, int size, u32 value)
  163. {
  164. struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
  165. void __iomem *base = apc->cfg_base;
  166. int err;
  167. int ret;
  168. value = value << (8 * (where & 3));
  169. ret = PCIBIOS_SUCCESSFUL;
  170. err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
  171. AR71XX_PCI_CFG_CMD_WRITE);
  172. if (err)
  173. ret = PCIBIOS_DEVICE_NOT_FOUND;
  174. else
  175. __raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA);
  176. return ret;
  177. }
  178. static struct pci_ops ar71xx_pci_ops = {
  179. .read = ar71xx_pci_read_config,
  180. .write = ar71xx_pci_write_config,
  181. };
  182. static void ar71xx_pci_irq_handler(struct irq_desc *desc)
  183. {
  184. struct ar71xx_pci_controller *apc;
  185. void __iomem *base = ath79_reset_base;
  186. u32 pending;
  187. apc = irq_desc_get_handler_data(desc);
  188. pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
  189. __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
  190. if (pending & AR71XX_PCI_INT_DEV0)
  191. generic_handle_irq(apc->irq_base + 0);
  192. else if (pending & AR71XX_PCI_INT_DEV1)
  193. generic_handle_irq(apc->irq_base + 1);
  194. else if (pending & AR71XX_PCI_INT_DEV2)
  195. generic_handle_irq(apc->irq_base + 2);
  196. else if (pending & AR71XX_PCI_INT_CORE)
  197. generic_handle_irq(apc->irq_base + 4);
  198. else
  199. spurious_interrupt();
  200. }
  201. static void ar71xx_pci_irq_unmask(struct irq_data *d)
  202. {
  203. struct ar71xx_pci_controller *apc;
  204. unsigned int irq;
  205. void __iomem *base = ath79_reset_base;
  206. u32 t;
  207. apc = irq_data_get_irq_chip_data(d);
  208. irq = d->irq - apc->irq_base;
  209. t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
  210. __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
  211. /* flush write */
  212. __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
  213. }
  214. static void ar71xx_pci_irq_mask(struct irq_data *d)
  215. {
  216. struct ar71xx_pci_controller *apc;
  217. unsigned int irq;
  218. void __iomem *base = ath79_reset_base;
  219. u32 t;
  220. apc = irq_data_get_irq_chip_data(d);
  221. irq = d->irq - apc->irq_base;
  222. t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
  223. __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
  224. /* flush write */
  225. __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
  226. }
  227. static struct irq_chip ar71xx_pci_irq_chip = {
  228. .name = "AR71XX PCI",
  229. .irq_mask = ar71xx_pci_irq_mask,
  230. .irq_unmask = ar71xx_pci_irq_unmask,
  231. .irq_mask_ack = ar71xx_pci_irq_mask,
  232. };
  233. static void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
  234. {
  235. void __iomem *base = ath79_reset_base;
  236. int i;
  237. __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
  238. __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
  239. BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT);
  240. apc->irq_base = ATH79_PCI_IRQ_BASE;
  241. for (i = apc->irq_base;
  242. i < apc->irq_base + AR71XX_PCI_IRQ_COUNT; i++) {
  243. irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
  244. handle_level_irq);
  245. irq_set_chip_data(i, apc);
  246. }
  247. irq_set_chained_handler_and_data(apc->irq, ar71xx_pci_irq_handler,
  248. apc);
  249. }
  250. static void ar71xx_pci_reset(void)
  251. {
  252. ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
  253. mdelay(100);
  254. ath79_device_reset_clear(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
  255. mdelay(100);
  256. ath79_ddr_set_pci_windows();
  257. mdelay(100);
  258. }
  259. static int ar71xx_pci_probe(struct platform_device *pdev)
  260. {
  261. struct ar71xx_pci_controller *apc;
  262. struct resource *res;
  263. u32 t;
  264. apc = devm_kzalloc(&pdev->dev, sizeof(struct ar71xx_pci_controller),
  265. GFP_KERNEL);
  266. if (!apc)
  267. return -ENOMEM;
  268. apc->cfg_base = devm_platform_ioremap_resource_byname(pdev,
  269. "cfg_base");
  270. if (IS_ERR(apc->cfg_base))
  271. return PTR_ERR(apc->cfg_base);
  272. apc->irq = platform_get_irq(pdev, 0);
  273. if (apc->irq < 0)
  274. return -EINVAL;
  275. res = platform_get_resource_byname(pdev, IORESOURCE_IO, "io_base");
  276. if (!res)
  277. return -EINVAL;
  278. apc->io_res.parent = res;
  279. apc->io_res.name = "PCI IO space";
  280. apc->io_res.start = res->start;
  281. apc->io_res.end = res->end;
  282. apc->io_res.flags = IORESOURCE_IO;
  283. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem_base");
  284. if (!res)
  285. return -EINVAL;
  286. apc->mem_res.parent = res;
  287. apc->mem_res.name = "PCI memory space";
  288. apc->mem_res.start = res->start;
  289. apc->mem_res.end = res->end;
  290. apc->mem_res.flags = IORESOURCE_MEM;
  291. ar71xx_pci_reset();
  292. /* setup COMMAND register */
  293. t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
  294. | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
  295. ar71xx_pci_local_write(apc, PCI_COMMAND, 4, t);
  296. /* clear bus errors */
  297. ar71xx_pci_check_error(apc, 1);
  298. ar71xx_pci_irq_init(apc);
  299. apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
  300. apc->pci_ctrl.mem_resource = &apc->mem_res;
  301. apc->pci_ctrl.io_resource = &apc->io_res;
  302. register_pci_controller(&apc->pci_ctrl);
  303. return 0;
  304. }
  305. static struct platform_driver ar71xx_pci_driver = {
  306. .probe = ar71xx_pci_probe,
  307. .driver = {
  308. .name = "ar71xx-pci",
  309. },
  310. };
  311. static int __init ar71xx_pci_init(void)
  312. {
  313. return platform_driver_register(&ar71xx_pci_driver);
  314. }
  315. postcore_initcall(ar71xx_pci_init);