pci-ar2315.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. */
  4. /*
  5. * Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA
  6. * and interrupt. PCI interface supports MMIO access method, but does not
  7. * seem to support I/O ports.
  8. *
  9. * Read/write operation in the region 0x80000000-0xBFFFFFFF causes
  10. * a memory read/write command on the PCI bus. 30 LSBs of address on
  11. * the bus are taken from memory read/write request and 2 MSBs are
  12. * determined by PCI unit configuration.
  13. *
  14. * To work with the configuration space instead of memory is necessary set
  15. * the CFG_SEL bit in the PCI_MISC_CONFIG register.
  16. *
  17. * Devices on the bus can perform DMA requests via chip BAR1. PCI host
  18. * controller BARs are programmend as if an external device is programmed.
  19. * Which means that during configuration, IDSEL pin of the chip should be
  20. * asserted.
  21. *
  22. * We know (and support) only one board that uses the PCI interface -
  23. * Fonera 2.0g (FON2202). It has a USB EHCI controller connected to the
  24. * AR2315 PCI bus. IDSEL pin of USB controller is connected to AD[13] line
  25. * and IDSEL pin of AR2315 is connected to AD[16] line.
  26. */
  27. #include <linux/types.h>
  28. #include <linux/pci.h>
  29. #include <linux/platform_device.h>
  30. #include <linux/kernel.h>
  31. #include <linux/init.h>
  32. #include <linux/dma-direct.h>
  33. #include <linux/mm.h>
  34. #include <linux/delay.h>
  35. #include <linux/bitops.h>
  36. #include <linux/irq.h>
  37. #include <linux/irqdomain.h>
  38. #include <linux/io.h>
  39. #include <asm/paccess.h>
  40. /*
  41. * PCI Bus Interface Registers
  42. */
  43. #define AR2315_PCI_1MS_REG 0x0008
  44. #define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
  45. #define AR2315_PCI_MISC_CONFIG 0x000c
  46. #define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
  47. #define AR2315_PCIMISC_CFG_SEL 0x00000002 /* Mem or Config cycles */
  48. #define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
  49. #define AR2315_PCIMISC_RST_MODE 0x00000030
  50. #define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
  51. #define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
  52. #define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
  53. #define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
  54. #define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
  55. #define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
  56. #define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
  57. #define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
  58. * disable */
  59. #define AR2315_PCI_OUT_TSTAMP 0x0010
  60. #define AR2315_PCI_UNCACHE_CFG 0x0014
  61. #define AR2315_PCI_IN_EN 0x0100
  62. #define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
  63. #define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
  64. #define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
  65. #define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
  66. #define AR2315_PCI_IN_DIS 0x0104
  67. #define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
  68. #define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
  69. #define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
  70. #define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
  71. #define AR2315_PCI_IN_PTR 0x0200
  72. #define AR2315_PCI_OUT_EN 0x0400
  73. #define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
  74. #define AR2315_PCI_OUT_DIS 0x0404
  75. #define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
  76. #define AR2315_PCI_OUT_PTR 0x0408
  77. /* PCI interrupt status (write one to clear) */
  78. #define AR2315_PCI_ISR 0x0500
  79. #define AR2315_PCI_INT_TX 0x00000001 /* Desc In Completed */
  80. #define AR2315_PCI_INT_TXOK 0x00000002 /* Desc In OK */
  81. #define AR2315_PCI_INT_TXERR 0x00000004 /* Desc In ERR */
  82. #define AR2315_PCI_INT_TXEOL 0x00000008 /* Desc In End-of-List */
  83. #define AR2315_PCI_INT_RX 0x00000010 /* Desc Out Completed */
  84. #define AR2315_PCI_INT_RXOK 0x00000020 /* Desc Out OK */
  85. #define AR2315_PCI_INT_RXERR 0x00000040 /* Desc Out ERR */
  86. #define AR2315_PCI_INT_RXEOL 0x00000080 /* Desc Out EOL */
  87. #define AR2315_PCI_INT_TXOOD 0x00000200 /* Desc In Out-of-Desc */
  88. #define AR2315_PCI_INT_DESCMASK 0x0000FFFF /* Desc Mask */
  89. #define AR2315_PCI_INT_EXT 0x02000000 /* Extern PCI INTA */
  90. #define AR2315_PCI_INT_ABORT 0x04000000 /* PCI bus abort event */
  91. /* PCI interrupt mask */
  92. #define AR2315_PCI_IMR 0x0504
  93. /* Global PCI interrupt enable */
  94. #define AR2315_PCI_IER 0x0508
  95. #define AR2315_PCI_IER_DISABLE 0x00 /* disable pci interrupts */
  96. #define AR2315_PCI_IER_ENABLE 0x01 /* enable pci interrupts */
  97. #define AR2315_PCI_HOST_IN_EN 0x0800
  98. #define AR2315_PCI_HOST_IN_DIS 0x0804
  99. #define AR2315_PCI_HOST_IN_PTR 0x0810
  100. #define AR2315_PCI_HOST_OUT_EN 0x0900
  101. #define AR2315_PCI_HOST_OUT_DIS 0x0904
  102. #define AR2315_PCI_HOST_OUT_PTR 0x0908
  103. /*
  104. * PCI interrupts, which share IP5
  105. * Keep ordered according to AR2315_PCI_INT_XXX bits
  106. */
  107. #define AR2315_PCI_IRQ_EXT 25
  108. #define AR2315_PCI_IRQ_ABORT 26
  109. #define AR2315_PCI_IRQ_COUNT 27
  110. /* Arbitrary size of memory region to access the configuration space */
  111. #define AR2315_PCI_CFG_SIZE 0x00100000
  112. #define AR2315_PCI_HOST_SLOT 3
  113. #define AR2315_PCI_HOST_DEVID ((0xff18 << 16) | PCI_VENDOR_ID_ATHEROS)
  114. /*
  115. * We need some arbitrary non-zero value to be programmed to the BAR1 register
  116. * of PCI host controller to enable DMA. The same value should be used as the
  117. * offset to calculate the physical address of DMA buffer for PCI devices.
  118. */
  119. #define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
  120. /* ??? access BAR */
  121. #define AR2315_PCI_HOST_MBAR0 0x10000000
  122. /* RAM access BAR */
  123. #define AR2315_PCI_HOST_MBAR1 AR2315_PCI_HOST_SDRAM_BASEADDR
  124. /* ??? access BAR */
  125. #define AR2315_PCI_HOST_MBAR2 0x30000000
  126. struct ar2315_pci_ctrl {
  127. void __iomem *cfg_mem;
  128. void __iomem *mmr_mem;
  129. unsigned irq;
  130. unsigned irq_ext;
  131. struct irq_domain *domain;
  132. struct pci_controller pci_ctrl;
  133. struct resource mem_res;
  134. struct resource io_res;
  135. };
  136. static inline dma_addr_t ar2315_dev_offset(struct device *dev)
  137. {
  138. if (dev && dev_is_pci(dev))
  139. return AR2315_PCI_HOST_SDRAM_BASEADDR;
  140. return 0;
  141. }
  142. dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
  143. {
  144. return paddr + ar2315_dev_offset(dev);
  145. }
  146. phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dma_addr)
  147. {
  148. return dma_addr - ar2315_dev_offset(dev);
  149. }
  150. static inline struct ar2315_pci_ctrl *ar2315_pci_bus_to_apc(struct pci_bus *bus)
  151. {
  152. struct pci_controller *hose = bus->sysdata;
  153. return container_of(hose, struct ar2315_pci_ctrl, pci_ctrl);
  154. }
  155. static inline u32 ar2315_pci_reg_read(struct ar2315_pci_ctrl *apc, u32 reg)
  156. {
  157. return __raw_readl(apc->mmr_mem + reg);
  158. }
  159. static inline void ar2315_pci_reg_write(struct ar2315_pci_ctrl *apc, u32 reg,
  160. u32 val)
  161. {
  162. __raw_writel(val, apc->mmr_mem + reg);
  163. }
  164. static inline void ar2315_pci_reg_mask(struct ar2315_pci_ctrl *apc, u32 reg,
  165. u32 mask, u32 val)
  166. {
  167. u32 ret = ar2315_pci_reg_read(apc, reg);
  168. ret &= ~mask;
  169. ret |= val;
  170. ar2315_pci_reg_write(apc, reg, ret);
  171. }
  172. static int ar2315_pci_cfg_access(struct ar2315_pci_ctrl *apc, unsigned devfn,
  173. int where, int size, u32 *ptr, bool write)
  174. {
  175. int func = PCI_FUNC(devfn);
  176. int dev = PCI_SLOT(devfn);
  177. u32 addr = (1 << (13 + dev)) | (func << 8) | (where & ~3);
  178. u32 mask = 0xffffffff >> 8 * (4 - size);
  179. u32 sh = (where & 3) * 8;
  180. u32 value, isr;
  181. /* Prevent access past the remapped area */
  182. if (addr >= AR2315_PCI_CFG_SIZE || dev > 18)
  183. return PCIBIOS_DEVICE_NOT_FOUND;
  184. /* Clear pending errors */
  185. ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
  186. /* Select Configuration access */
  187. ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, 0,
  188. AR2315_PCIMISC_CFG_SEL);
  189. mb(); /* PCI must see space change before we begin */
  190. value = __raw_readl(apc->cfg_mem + addr);
  191. isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
  192. if (isr & AR2315_PCI_INT_ABORT)
  193. goto exit_err;
  194. if (write) {
  195. value = (value & ~(mask << sh)) | *ptr << sh;
  196. __raw_writel(value, apc->cfg_mem + addr);
  197. isr = ar2315_pci_reg_read(apc, AR2315_PCI_ISR);
  198. if (isr & AR2315_PCI_INT_ABORT)
  199. goto exit_err;
  200. } else {
  201. *ptr = (value >> sh) & mask;
  202. }
  203. goto exit;
  204. exit_err:
  205. ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
  206. if (!write)
  207. *ptr = 0xffffffff;
  208. exit:
  209. /* Select Memory access */
  210. ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL,
  211. 0);
  212. return isr & AR2315_PCI_INT_ABORT ? PCIBIOS_DEVICE_NOT_FOUND :
  213. PCIBIOS_SUCCESSFUL;
  214. }
  215. static inline int ar2315_pci_local_cfg_rd(struct ar2315_pci_ctrl *apc,
  216. unsigned devfn, int where, u32 *val)
  217. {
  218. return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), val,
  219. false);
  220. }
  221. static inline int ar2315_pci_local_cfg_wr(struct ar2315_pci_ctrl *apc,
  222. unsigned devfn, int where, u32 val)
  223. {
  224. return ar2315_pci_cfg_access(apc, devfn, where, sizeof(u32), &val,
  225. true);
  226. }
  227. static int ar2315_pci_cfg_read(struct pci_bus *bus, unsigned devfn, int where,
  228. int size, u32 *value)
  229. {
  230. struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
  231. if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
  232. return PCIBIOS_DEVICE_NOT_FOUND;
  233. return ar2315_pci_cfg_access(apc, devfn, where, size, value, false);
  234. }
  235. static int ar2315_pci_cfg_write(struct pci_bus *bus, unsigned devfn, int where,
  236. int size, u32 value)
  237. {
  238. struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(bus);
  239. if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
  240. return PCIBIOS_DEVICE_NOT_FOUND;
  241. return ar2315_pci_cfg_access(apc, devfn, where, size, &value, true);
  242. }
  243. static struct pci_ops ar2315_pci_ops = {
  244. .read = ar2315_pci_cfg_read,
  245. .write = ar2315_pci_cfg_write,
  246. };
  247. static int ar2315_pci_host_setup(struct ar2315_pci_ctrl *apc)
  248. {
  249. unsigned devfn = PCI_DEVFN(AR2315_PCI_HOST_SLOT, 0);
  250. int res;
  251. u32 id;
  252. res = ar2315_pci_local_cfg_rd(apc, devfn, PCI_VENDOR_ID, &id);
  253. if (res != PCIBIOS_SUCCESSFUL || id != AR2315_PCI_HOST_DEVID)
  254. return -ENODEV;
  255. /* Program MBARs */
  256. ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_0,
  257. AR2315_PCI_HOST_MBAR0);
  258. ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_1,
  259. AR2315_PCI_HOST_MBAR1);
  260. ar2315_pci_local_cfg_wr(apc, devfn, PCI_BASE_ADDRESS_2,
  261. AR2315_PCI_HOST_MBAR2);
  262. /* Run */
  263. ar2315_pci_local_cfg_wr(apc, devfn, PCI_COMMAND, PCI_COMMAND_MEMORY |
  264. PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
  265. PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
  266. PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
  267. return 0;
  268. }
  269. static void ar2315_pci_irq_handler(struct irq_desc *desc)
  270. {
  271. struct ar2315_pci_ctrl *apc = irq_desc_get_handler_data(desc);
  272. u32 pending = ar2315_pci_reg_read(apc, AR2315_PCI_ISR) &
  273. ar2315_pci_reg_read(apc, AR2315_PCI_IMR);
  274. int ret = 0;
  275. if (pending)
  276. ret = generic_handle_domain_irq(apc->domain, __ffs(pending));
  277. if (!pending || ret)
  278. spurious_interrupt();
  279. }
  280. static void ar2315_pci_irq_mask(struct irq_data *d)
  281. {
  282. struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
  283. ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, BIT(d->hwirq), 0);
  284. }
  285. static void ar2315_pci_irq_mask_ack(struct irq_data *d)
  286. {
  287. struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
  288. u32 m = BIT(d->hwirq);
  289. ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, m, 0);
  290. ar2315_pci_reg_write(apc, AR2315_PCI_ISR, m);
  291. }
  292. static void ar2315_pci_irq_unmask(struct irq_data *d)
  293. {
  294. struct ar2315_pci_ctrl *apc = irq_data_get_irq_chip_data(d);
  295. ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, 0, BIT(d->hwirq));
  296. }
  297. static struct irq_chip ar2315_pci_irq_chip = {
  298. .name = "AR2315-PCI",
  299. .irq_mask = ar2315_pci_irq_mask,
  300. .irq_mask_ack = ar2315_pci_irq_mask_ack,
  301. .irq_unmask = ar2315_pci_irq_unmask,
  302. };
  303. static int ar2315_pci_irq_map(struct irq_domain *d, unsigned irq,
  304. irq_hw_number_t hw)
  305. {
  306. irq_set_chip_and_handler(irq, &ar2315_pci_irq_chip, handle_level_irq);
  307. irq_set_chip_data(irq, d->host_data);
  308. return 0;
  309. }
  310. static const struct irq_domain_ops ar2315_pci_irq_domain_ops = {
  311. .map = ar2315_pci_irq_map,
  312. };
  313. static void ar2315_pci_irq_init(struct ar2315_pci_ctrl *apc)
  314. {
  315. ar2315_pci_reg_mask(apc, AR2315_PCI_IER, AR2315_PCI_IER_ENABLE, 0);
  316. ar2315_pci_reg_mask(apc, AR2315_PCI_IMR, (AR2315_PCI_INT_ABORT |
  317. AR2315_PCI_INT_EXT), 0);
  318. apc->irq_ext = irq_create_mapping(apc->domain, AR2315_PCI_IRQ_EXT);
  319. irq_set_chained_handler_and_data(apc->irq, ar2315_pci_irq_handler,
  320. apc);
  321. /* Clear any pending Abort or external Interrupts
  322. * and enable interrupt processing */
  323. ar2315_pci_reg_write(apc, AR2315_PCI_ISR, AR2315_PCI_INT_ABORT |
  324. AR2315_PCI_INT_EXT);
  325. ar2315_pci_reg_mask(apc, AR2315_PCI_IER, 0, AR2315_PCI_IER_ENABLE);
  326. }
  327. static int ar2315_pci_probe(struct platform_device *pdev)
  328. {
  329. struct ar2315_pci_ctrl *apc;
  330. struct device *dev = &pdev->dev;
  331. struct resource *res;
  332. int irq, err;
  333. apc = devm_kzalloc(dev, sizeof(*apc), GFP_KERNEL);
  334. if (!apc)
  335. return -ENOMEM;
  336. irq = platform_get_irq(pdev, 0);
  337. if (irq < 0)
  338. return -EINVAL;
  339. apc->irq = irq;
  340. apc->mmr_mem = devm_platform_ioremap_resource_byname(pdev,
  341. "ar2315-pci-ctrl");
  342. if (IS_ERR(apc->mmr_mem))
  343. return PTR_ERR(apc->mmr_mem);
  344. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  345. "ar2315-pci-ext");
  346. if (!res)
  347. return -EINVAL;
  348. apc->mem_res.name = "AR2315 PCI mem space";
  349. apc->mem_res.parent = res;
  350. apc->mem_res.start = res->start;
  351. apc->mem_res.end = res->end;
  352. apc->mem_res.flags = IORESOURCE_MEM;
  353. /* Remap PCI config space */
  354. apc->cfg_mem = devm_ioremap(dev, res->start,
  355. AR2315_PCI_CFG_SIZE);
  356. if (!apc->cfg_mem) {
  357. dev_err(dev, "failed to remap PCI config space\n");
  358. return -ENOMEM;
  359. }
  360. /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
  361. ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
  362. AR2315_PCIMISC_RST_MODE,
  363. AR2315_PCIRST_LOW);
  364. msleep(100);
  365. /* Bring the PCI out of reset */
  366. ar2315_pci_reg_mask(apc, AR2315_PCI_MISC_CONFIG,
  367. AR2315_PCIMISC_RST_MODE,
  368. AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
  369. ar2315_pci_reg_write(apc, AR2315_PCI_UNCACHE_CFG,
  370. 0x1E | /* 1GB uncached */
  371. (1 << 5) | /* Enable uncached */
  372. (0x2 << 30) /* Base: 0x80000000 */);
  373. ar2315_pci_reg_read(apc, AR2315_PCI_UNCACHE_CFG);
  374. msleep(500);
  375. err = ar2315_pci_host_setup(apc);
  376. if (err)
  377. return err;
  378. apc->domain = irq_domain_add_linear(NULL, AR2315_PCI_IRQ_COUNT,
  379. &ar2315_pci_irq_domain_ops, apc);
  380. if (!apc->domain) {
  381. dev_err(dev, "failed to add IRQ domain\n");
  382. return -ENOMEM;
  383. }
  384. ar2315_pci_irq_init(apc);
  385. /* PCI controller does not support I/O ports */
  386. apc->io_res.name = "AR2315 IO space";
  387. apc->io_res.start = 0;
  388. apc->io_res.end = 0;
  389. apc->io_res.flags = IORESOURCE_IO;
  390. apc->pci_ctrl.pci_ops = &ar2315_pci_ops;
  391. apc->pci_ctrl.mem_resource = &apc->mem_res;
  392. apc->pci_ctrl.io_resource = &apc->io_res;
  393. register_pci_controller(&apc->pci_ctrl);
  394. dev_info(dev, "register PCI controller\n");
  395. return 0;
  396. }
  397. static struct platform_driver ar2315_pci_driver = {
  398. .probe = ar2315_pci_probe,
  399. .driver = {
  400. .name = "ar2315-pci",
  401. },
  402. };
  403. static int __init ar2315_pci_init(void)
  404. {
  405. return platform_driver_register(&ar2315_pci_driver);
  406. }
  407. arch_initcall(ar2315_pci_init);
  408. int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  409. {
  410. struct ar2315_pci_ctrl *apc = ar2315_pci_bus_to_apc(dev->bus);
  411. return slot ? 0 : apc->irq_ext;
  412. }
  413. int pcibios_plat_dev_init(struct pci_dev *dev)
  414. {
  415. return 0;
  416. }