ops-tx4927.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Define the pci_ops for the PCIC on Toshiba TX4927, TX4938, etc.
  4. *
  5. * Based on linux/arch/mips/pci/ops-tx4938.c,
  6. * linux/arch/mips/pci/fixup-rbtx4938.c,
  7. * linux/arch/mips/txx9/rbtx4938/setup.c,
  8. * and RBTX49xx patch from CELF patch archive.
  9. *
  10. * 2003-2005 (c) MontaVista Software, Inc.
  11. * Copyright (C) 2004 by Ralf Baechle ([email protected])
  12. * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/irq.h>
  17. #include <asm/txx9/pci.h>
  18. #include <asm/txx9/tx4927pcic.h>
  19. static struct {
  20. struct pci_controller *channel;
  21. struct tx4927_pcic_reg __iomem *pcicptr;
  22. } pcicptrs[2]; /* TX4938 has 2 pcic */
  23. static void __init set_tx4927_pcicptr(struct pci_controller *channel,
  24. struct tx4927_pcic_reg __iomem *pcicptr)
  25. {
  26. int i;
  27. for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
  28. if (pcicptrs[i].channel == channel) {
  29. pcicptrs[i].pcicptr = pcicptr;
  30. return;
  31. }
  32. }
  33. for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
  34. if (!pcicptrs[i].channel) {
  35. pcicptrs[i].channel = channel;
  36. pcicptrs[i].pcicptr = pcicptr;
  37. return;
  38. }
  39. }
  40. BUG();
  41. }
  42. struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr(
  43. struct pci_controller *channel)
  44. {
  45. int i;
  46. for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
  47. if (pcicptrs[i].channel == channel)
  48. return pcicptrs[i].pcicptr;
  49. }
  50. return NULL;
  51. }
  52. static int mkaddr(struct pci_bus *bus, unsigned int devfn, int where,
  53. struct tx4927_pcic_reg __iomem *pcicptr)
  54. {
  55. if (bus->parent == NULL &&
  56. devfn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0))
  57. return -1;
  58. __raw_writel(((bus->number & 0xff) << 0x10)
  59. | ((devfn & 0xff) << 0x08) | (where & 0xfc)
  60. | (bus->parent ? 1 : 0),
  61. &pcicptr->g2pcfgadrs);
  62. /* clear M_ABORT and Disable M_ABORT Int. */
  63. __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
  64. | (PCI_STATUS_REC_MASTER_ABORT << 16),
  65. &pcicptr->pcistatus);
  66. return 0;
  67. }
  68. static int check_abort(struct tx4927_pcic_reg __iomem *pcicptr)
  69. {
  70. int code = PCIBIOS_SUCCESSFUL;
  71. /* wait write cycle completion before checking error status */
  72. while (__raw_readl(&pcicptr->pcicstatus) & TX4927_PCIC_PCICSTATUS_IWB)
  73. ;
  74. if (__raw_readl(&pcicptr->pcistatus)
  75. & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
  76. __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
  77. | (PCI_STATUS_REC_MASTER_ABORT << 16),
  78. &pcicptr->pcistatus);
  79. /* flush write buffer */
  80. iob();
  81. code = PCIBIOS_DEVICE_NOT_FOUND;
  82. }
  83. return code;
  84. }
  85. static u8 icd_readb(int offset, struct tx4927_pcic_reg __iomem *pcicptr)
  86. {
  87. #ifdef __BIG_ENDIAN
  88. offset ^= 3;
  89. #endif
  90. return __raw_readb((void __iomem *)&pcicptr->g2pcfgdata + offset);
  91. }
  92. static u16 icd_readw(int offset, struct tx4927_pcic_reg __iomem *pcicptr)
  93. {
  94. #ifdef __BIG_ENDIAN
  95. offset ^= 2;
  96. #endif
  97. return __raw_readw((void __iomem *)&pcicptr->g2pcfgdata + offset);
  98. }
  99. static u32 icd_readl(struct tx4927_pcic_reg __iomem *pcicptr)
  100. {
  101. return __raw_readl(&pcicptr->g2pcfgdata);
  102. }
  103. static void icd_writeb(u8 val, int offset,
  104. struct tx4927_pcic_reg __iomem *pcicptr)
  105. {
  106. #ifdef __BIG_ENDIAN
  107. offset ^= 3;
  108. #endif
  109. __raw_writeb(val, (void __iomem *)&pcicptr->g2pcfgdata + offset);
  110. }
  111. static void icd_writew(u16 val, int offset,
  112. struct tx4927_pcic_reg __iomem *pcicptr)
  113. {
  114. #ifdef __BIG_ENDIAN
  115. offset ^= 2;
  116. #endif
  117. __raw_writew(val, (void __iomem *)&pcicptr->g2pcfgdata + offset);
  118. }
  119. static void icd_writel(u32 val, struct tx4927_pcic_reg __iomem *pcicptr)
  120. {
  121. __raw_writel(val, &pcicptr->g2pcfgdata);
  122. }
  123. static struct tx4927_pcic_reg __iomem *pci_bus_to_pcicptr(struct pci_bus *bus)
  124. {
  125. struct pci_controller *channel = bus->sysdata;
  126. return get_tx4927_pcicptr(channel);
  127. }
  128. static int tx4927_pci_config_read(struct pci_bus *bus, unsigned int devfn,
  129. int where, int size, u32 *val)
  130. {
  131. struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus);
  132. if (mkaddr(bus, devfn, where, pcicptr)) {
  133. *val = 0xffffffff;
  134. return -1;
  135. }
  136. switch (size) {
  137. case 1:
  138. *val = icd_readb(where & 3, pcicptr);
  139. break;
  140. case 2:
  141. *val = icd_readw(where & 3, pcicptr);
  142. break;
  143. default:
  144. *val = icd_readl(pcicptr);
  145. }
  146. return check_abort(pcicptr);
  147. }
  148. static int tx4927_pci_config_write(struct pci_bus *bus, unsigned int devfn,
  149. int where, int size, u32 val)
  150. {
  151. struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus);
  152. if (mkaddr(bus, devfn, where, pcicptr))
  153. return -1;
  154. switch (size) {
  155. case 1:
  156. icd_writeb(val, where & 3, pcicptr);
  157. break;
  158. case 2:
  159. icd_writew(val, where & 3, pcicptr);
  160. break;
  161. default:
  162. icd_writel(val, pcicptr);
  163. }
  164. return check_abort(pcicptr);
  165. }
  166. static struct pci_ops tx4927_pci_ops = {
  167. .read = tx4927_pci_config_read,
  168. .write = tx4927_pci_config_write,
  169. };
  170. static struct {
  171. u8 trdyto;
  172. u8 retryto;
  173. u16 gbwc;
  174. } tx4927_pci_opts = {
  175. .trdyto = 0,
  176. .retryto = 0,
  177. .gbwc = 0xfe0, /* 4064 GBUSCLK for CCFG.GTOT=0b11 */
  178. };
  179. char *tx4927_pcibios_setup(char *str)
  180. {
  181. if (!strncmp(str, "trdyto=", 7)) {
  182. u8 val = 0;
  183. if (kstrtou8(str + 7, 0, &val) == 0)
  184. tx4927_pci_opts.trdyto = val;
  185. return NULL;
  186. }
  187. if (!strncmp(str, "retryto=", 8)) {
  188. u8 val = 0;
  189. if (kstrtou8(str + 8, 0, &val) == 0)
  190. tx4927_pci_opts.retryto = val;
  191. return NULL;
  192. }
  193. if (!strncmp(str, "gbwc=", 5)) {
  194. u16 val;
  195. if (kstrtou16(str + 5, 0, &val) == 0)
  196. tx4927_pci_opts.gbwc = val;
  197. return NULL;
  198. }
  199. return str;
  200. }
  201. void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
  202. struct pci_controller *channel, int extarb)
  203. {
  204. int i;
  205. unsigned long flags;
  206. set_tx4927_pcicptr(channel, pcicptr);
  207. if (!channel->pci_ops)
  208. printk(KERN_INFO
  209. "PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
  210. __raw_readl(&pcicptr->pciid) >> 16,
  211. __raw_readl(&pcicptr->pciid) & 0xffff,
  212. __raw_readl(&pcicptr->pciccrev) & 0xff,
  213. extarb ? "External" : "Internal");
  214. channel->pci_ops = &tx4927_pci_ops;
  215. local_irq_save(flags);
  216. /* Disable All Initiator Space */
  217. __raw_writel(__raw_readl(&pcicptr->pciccfg)
  218. & ~(TX4927_PCIC_PCICCFG_G2PMEN(0)
  219. | TX4927_PCIC_PCICCFG_G2PMEN(1)
  220. | TX4927_PCIC_PCICCFG_G2PMEN(2)
  221. | TX4927_PCIC_PCICCFG_G2PIOEN),
  222. &pcicptr->pciccfg);
  223. /* GB->PCI mappings */
  224. __raw_writel((channel->io_resource->end - channel->io_resource->start)
  225. >> 4,
  226. &pcicptr->g2piomask);
  227. ____raw_writeq((channel->io_resource->start +
  228. channel->io_map_base - IO_BASE) |
  229. #ifdef __BIG_ENDIAN
  230. TX4927_PCIC_G2PIOGBASE_ECHG
  231. #else
  232. TX4927_PCIC_G2PIOGBASE_BSDIS
  233. #endif
  234. , &pcicptr->g2piogbase);
  235. ____raw_writeq(channel->io_resource->start - channel->io_offset,
  236. &pcicptr->g2piopbase);
  237. for (i = 0; i < 3; i++) {
  238. __raw_writel(0, &pcicptr->g2pmmask[i]);
  239. ____raw_writeq(0, &pcicptr->g2pmgbase[i]);
  240. ____raw_writeq(0, &pcicptr->g2pmpbase[i]);
  241. }
  242. if (channel->mem_resource->end) {
  243. __raw_writel((channel->mem_resource->end
  244. - channel->mem_resource->start) >> 4,
  245. &pcicptr->g2pmmask[0]);
  246. ____raw_writeq(channel->mem_resource->start |
  247. #ifdef __BIG_ENDIAN
  248. TX4927_PCIC_G2PMnGBASE_ECHG
  249. #else
  250. TX4927_PCIC_G2PMnGBASE_BSDIS
  251. #endif
  252. , &pcicptr->g2pmgbase[0]);
  253. ____raw_writeq(channel->mem_resource->start -
  254. channel->mem_offset,
  255. &pcicptr->g2pmpbase[0]);
  256. }
  257. /* PCI->GB mappings (I/O 256B) */
  258. __raw_writel(0, &pcicptr->p2giopbase); /* 256B */
  259. ____raw_writeq(0, &pcicptr->p2giogbase);
  260. /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */
  261. __raw_writel(0, &pcicptr->p2gm0plbase);
  262. __raw_writel(0, &pcicptr->p2gm0pubase);
  263. ____raw_writeq(TX4927_PCIC_P2GMnGBASE_TMEMEN |
  264. #ifdef __BIG_ENDIAN
  265. TX4927_PCIC_P2GMnGBASE_TECHG
  266. #else
  267. TX4927_PCIC_P2GMnGBASE_TBSDIS
  268. #endif
  269. , &pcicptr->p2gmgbase[0]);
  270. /* PCI->GB mappings (MEM 16MB) */
  271. __raw_writel(0xffffffff, &pcicptr->p2gm1plbase);
  272. __raw_writel(0xffffffff, &pcicptr->p2gm1pubase);
  273. ____raw_writeq(0, &pcicptr->p2gmgbase[1]);
  274. /* PCI->GB mappings (MEM 1MB) */
  275. __raw_writel(0xffffffff, &pcicptr->p2gm2pbase); /* 1MB */
  276. ____raw_writeq(0, &pcicptr->p2gmgbase[2]);
  277. /* Clear all (including IRBER) except for GBWC */
  278. __raw_writel((tx4927_pci_opts.gbwc << 16)
  279. & TX4927_PCIC_PCICCFG_GBWC_MASK,
  280. &pcicptr->pciccfg);
  281. /* Enable Initiator Memory Space */
  282. if (channel->mem_resource->end)
  283. __raw_writel(__raw_readl(&pcicptr->pciccfg)
  284. | TX4927_PCIC_PCICCFG_G2PMEN(0),
  285. &pcicptr->pciccfg);
  286. /* Enable Initiator I/O Space */
  287. if (channel->io_resource->end)
  288. __raw_writel(__raw_readl(&pcicptr->pciccfg)
  289. | TX4927_PCIC_PCICCFG_G2PIOEN,
  290. &pcicptr->pciccfg);
  291. /* Enable Initiator Config */
  292. __raw_writel(__raw_readl(&pcicptr->pciccfg)
  293. | TX4927_PCIC_PCICCFG_ICAEN | TX4927_PCIC_PCICCFG_TCAR,
  294. &pcicptr->pciccfg);
  295. /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
  296. __raw_writel(0, &pcicptr->pcicfg1);
  297. __raw_writel((__raw_readl(&pcicptr->g2ptocnt) & ~0xffff)
  298. | (tx4927_pci_opts.trdyto & 0xff)
  299. | ((tx4927_pci_opts.retryto & 0xff) << 8),
  300. &pcicptr->g2ptocnt);
  301. /* Clear All Local Bus Status */
  302. __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus);
  303. /* Enable All Local Bus Interrupts */
  304. __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicmask);
  305. /* Clear All Initiator Status */
  306. __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus);
  307. /* Enable All Initiator Interrupts */
  308. __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pmask);
  309. /* Clear All PCI Status Error */
  310. __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
  311. | (TX4927_PCIC_PCISTATUS_ALL << 16),
  312. &pcicptr->pcistatus);
  313. /* Enable All PCI Status Error Interrupts */
  314. __raw_writel(TX4927_PCIC_PCISTATUS_ALL, &pcicptr->pcimask);
  315. if (!extarb) {
  316. /* Reset Bus Arbiter */
  317. __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg);
  318. __raw_writel(0, &pcicptr->pbabm);
  319. /* Enable Bus Arbiter */
  320. __raw_writel(TX4927_PCIC_PBACFG_PBAEN, &pcicptr->pbacfg);
  321. }
  322. __raw_writel(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
  323. | PCI_COMMAND_PARITY | PCI_COMMAND_SERR,
  324. &pcicptr->pcistatus);
  325. local_irq_restore(flags);
  326. printk(KERN_DEBUG
  327. "PCI: COMMAND=%04x,PCIMASK=%04x,"
  328. "TRDYTO=%02x,RETRYTO=%02x,GBWC=%03x\n",
  329. __raw_readl(&pcicptr->pcistatus) & 0xffff,
  330. __raw_readl(&pcicptr->pcimask) & 0xffff,
  331. __raw_readl(&pcicptr->g2ptocnt) & 0xff,
  332. (__raw_readl(&pcicptr->g2ptocnt) & 0xff00) >> 8,
  333. (__raw_readl(&pcicptr->pciccfg) >> 16) & 0xfff);
  334. }
  335. static void tx4927_report_pcic_status1(struct tx4927_pcic_reg __iomem *pcicptr)
  336. {
  337. __u16 pcistatus = (__u16)(__raw_readl(&pcicptr->pcistatus) >> 16);
  338. __u32 g2pstatus = __raw_readl(&pcicptr->g2pstatus);
  339. __u32 pcicstatus = __raw_readl(&pcicptr->pcicstatus);
  340. static struct {
  341. __u32 flag;
  342. const char *str;
  343. } pcistat_tbl[] = {
  344. { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" },
  345. { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" },
  346. { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" },
  347. { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" },
  348. { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" },
  349. { PCI_STATUS_PARITY, "MasterParityError" },
  350. }, g2pstat_tbl[] = {
  351. { TX4927_PCIC_G2PSTATUS_TTOE, "TIOE" },
  352. { TX4927_PCIC_G2PSTATUS_RTOE, "RTOE" },
  353. }, pcicstat_tbl[] = {
  354. { TX4927_PCIC_PCICSTATUS_PME, "PME" },
  355. { TX4927_PCIC_PCICSTATUS_TLB, "TLB" },
  356. { TX4927_PCIC_PCICSTATUS_NIB, "NIB" },
  357. { TX4927_PCIC_PCICSTATUS_ZIB, "ZIB" },
  358. { TX4927_PCIC_PCICSTATUS_PERR, "PERR" },
  359. { TX4927_PCIC_PCICSTATUS_SERR, "SERR" },
  360. { TX4927_PCIC_PCICSTATUS_GBE, "GBE" },
  361. { TX4927_PCIC_PCICSTATUS_IWB, "IWB" },
  362. };
  363. int i, cont;
  364. printk(KERN_ERR "");
  365. if (pcistatus & TX4927_PCIC_PCISTATUS_ALL) {
  366. printk(KERN_CONT "pcistat:%04x(", pcistatus);
  367. for (i = 0, cont = 0; i < ARRAY_SIZE(pcistat_tbl); i++)
  368. if (pcistatus & pcistat_tbl[i].flag)
  369. printk(KERN_CONT "%s%s",
  370. cont++ ? " " : "", pcistat_tbl[i].str);
  371. printk(KERN_CONT ") ");
  372. }
  373. if (g2pstatus & TX4927_PCIC_G2PSTATUS_ALL) {
  374. printk(KERN_CONT "g2pstatus:%08x(", g2pstatus);
  375. for (i = 0, cont = 0; i < ARRAY_SIZE(g2pstat_tbl); i++)
  376. if (g2pstatus & g2pstat_tbl[i].flag)
  377. printk(KERN_CONT "%s%s",
  378. cont++ ? " " : "", g2pstat_tbl[i].str);
  379. printk(KERN_CONT ") ");
  380. }
  381. if (pcicstatus & TX4927_PCIC_PCICSTATUS_ALL) {
  382. printk(KERN_CONT "pcicstatus:%08x(", pcicstatus);
  383. for (i = 0, cont = 0; i < ARRAY_SIZE(pcicstat_tbl); i++)
  384. if (pcicstatus & pcicstat_tbl[i].flag)
  385. printk(KERN_CONT "%s%s",
  386. cont++ ? " " : "", pcicstat_tbl[i].str);
  387. printk(KERN_CONT ")");
  388. }
  389. printk(KERN_CONT "\n");
  390. }
  391. void tx4927_report_pcic_status(void)
  392. {
  393. int i;
  394. for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
  395. if (pcicptrs[i].pcicptr)
  396. tx4927_report_pcic_status1(pcicptrs[i].pcicptr);
  397. }
  398. }
  399. static void tx4927_dump_pcic_settings1(struct tx4927_pcic_reg __iomem *pcicptr)
  400. {
  401. int i;
  402. __u32 __iomem *preg = (__u32 __iomem *)pcicptr;
  403. printk(KERN_INFO "tx4927 pcic (0x%p) settings:", pcicptr);
  404. for (i = 0; i < sizeof(struct tx4927_pcic_reg); i += 4, preg++) {
  405. if (i % 32 == 0) {
  406. printk(KERN_CONT "\n");
  407. printk(KERN_INFO "%04x:", i);
  408. }
  409. /* skip registers with side-effects */
  410. if (i == offsetof(struct tx4927_pcic_reg, g2pintack)
  411. || i == offsetof(struct tx4927_pcic_reg, g2pspc)
  412. || i == offsetof(struct tx4927_pcic_reg, g2pcfgadrs)
  413. || i == offsetof(struct tx4927_pcic_reg, g2pcfgdata)) {
  414. printk(KERN_CONT " XXXXXXXX");
  415. continue;
  416. }
  417. printk(KERN_CONT " %08x", __raw_readl(preg));
  418. }
  419. printk(KERN_CONT "\n");
  420. }
  421. void tx4927_dump_pcic_settings(void)
  422. {
  423. int i;
  424. for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
  425. if (pcicptrs[i].pcicptr)
  426. tx4927_dump_pcic_settings1(pcicptrs[i].pcicptr);
  427. }
  428. }
  429. irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id)
  430. {
  431. struct pt_regs *regs = get_irq_regs();
  432. struct tx4927_pcic_reg __iomem *pcicptr =
  433. (struct tx4927_pcic_reg __iomem *)(unsigned long)dev_id;
  434. if (txx9_pci_err_action != TXX9_PCI_ERR_IGNORE) {
  435. printk(KERN_WARNING "PCIERR interrupt at 0x%0*lx\n",
  436. (int)(2 * sizeof(unsigned long)), regs->cp0_epc);
  437. tx4927_report_pcic_status1(pcicptr);
  438. }
  439. if (txx9_pci_err_action != TXX9_PCI_ERR_PANIC) {
  440. /* clear all pci errors */
  441. __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
  442. | (TX4927_PCIC_PCISTATUS_ALL << 16),
  443. &pcicptr->pcistatus);
  444. __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus);
  445. __raw_writel(TX4927_PCIC_PBASTATUS_ALL, &pcicptr->pbastatus);
  446. __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus);
  447. return IRQ_HANDLED;
  448. }
  449. console_verbose();
  450. tx4927_dump_pcic_settings1(pcicptr);
  451. panic("PCI error.");
  452. }
  453. #ifdef CONFIG_TOSHIBA_FPCIB0
  454. static void tx4927_quirk_slc90e66_bridge(struct pci_dev *dev)
  455. {
  456. struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(dev->bus);
  457. if (!pcicptr)
  458. return;
  459. if (__raw_readl(&pcicptr->pbacfg) & TX4927_PCIC_PBACFG_PBAEN) {
  460. /* Reset Bus Arbiter */
  461. __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg);
  462. /*
  463. * swap reqBP and reqXP (raise priority of SLC90E66).
  464. * SLC90E66(PCI-ISA bridge) is connected to REQ2 on
  465. * PCI Backplane board.
  466. */
  467. __raw_writel(0x72543610, &pcicptr->pbareqport);
  468. __raw_writel(0, &pcicptr->pbabm);
  469. /* Use Fixed ParkMaster (required by SLC90E66) */
  470. __raw_writel(TX4927_PCIC_PBACFG_FIXPA, &pcicptr->pbacfg);
  471. /* Enable Bus Arbiter */
  472. __raw_writel(TX4927_PCIC_PBACFG_FIXPA |
  473. TX4927_PCIC_PBACFG_PBAEN,
  474. &pcicptr->pbacfg);
  475. printk(KERN_INFO "PCI: Use Fixed Park Master (REQPORT %08x)\n",
  476. __raw_readl(&pcicptr->pbareqport));
  477. }
  478. }
  479. #define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460
  480. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0,
  481. tx4927_quirk_slc90e66_bridge);
  482. #endif