ops-lantiq.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. *
  4. * Copyright (C) 2010 John Crispin <[email protected]>
  5. */
  6. #include <linux/types.h>
  7. #include <linux/pci.h>
  8. #include <linux/kernel.h>
  9. #include <linux/delay.h>
  10. #include <linux/mm.h>
  11. #include <asm/addrspace.h>
  12. #include <linux/vmalloc.h>
  13. #include <lantiq_soc.h>
  14. #include "pci-lantiq.h"
  15. #define LTQ_PCI_CFG_BUSNUM_SHF 16
  16. #define LTQ_PCI_CFG_DEVNUM_SHF 11
  17. #define LTQ_PCI_CFG_FUNNUM_SHF 8
  18. #define PCI_ACCESS_READ 0
  19. #define PCI_ACCESS_WRITE 1
  20. static int ltq_pci_config_access(unsigned char access_type, struct pci_bus *bus,
  21. unsigned int devfn, unsigned int where, u32 *data)
  22. {
  23. unsigned long cfg_base;
  24. unsigned long flags;
  25. u32 temp;
  26. /* we support slot from 0 to 15 dev_fn & 0x68 (AD29) is the
  27. SoC itself */
  28. if ((bus->number != 0) || ((devfn & 0xf8) > 0x78)
  29. || ((devfn & 0xf8) == 0) || ((devfn & 0xf8) == 0x68))
  30. return 1;
  31. spin_lock_irqsave(&ebu_lock, flags);
  32. cfg_base = (unsigned long) ltq_pci_mapped_cfg;
  33. cfg_base |= (bus->number << LTQ_PCI_CFG_BUSNUM_SHF) | (devfn <<
  34. LTQ_PCI_CFG_FUNNUM_SHF) | (where & ~0x3);
  35. /* Perform access */
  36. if (access_type == PCI_ACCESS_WRITE) {
  37. ltq_w32(swab32(*data), ((u32 *)cfg_base));
  38. } else {
  39. *data = ltq_r32(((u32 *)(cfg_base)));
  40. *data = swab32(*data);
  41. }
  42. wmb();
  43. /* clean possible Master abort */
  44. cfg_base = (unsigned long) ltq_pci_mapped_cfg;
  45. cfg_base |= (0x0 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
  46. temp = ltq_r32(((u32 *)(cfg_base)));
  47. temp = swab32(temp);
  48. cfg_base = (unsigned long) ltq_pci_mapped_cfg;
  49. cfg_base |= (0x68 << LTQ_PCI_CFG_FUNNUM_SHF) + 4;
  50. ltq_w32(temp, ((u32 *)cfg_base));
  51. spin_unlock_irqrestore(&ebu_lock, flags);
  52. if (((*data) == 0xffffffff) && (access_type == PCI_ACCESS_READ))
  53. return 1;
  54. return 0;
  55. }
  56. int ltq_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn,
  57. int where, int size, u32 *val)
  58. {
  59. u32 data = 0;
  60. if (ltq_pci_config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
  61. return PCIBIOS_DEVICE_NOT_FOUND;
  62. if (size == 1)
  63. *val = (data >> ((where & 3) << 3)) & 0xff;
  64. else if (size == 2)
  65. *val = (data >> ((where & 3) << 3)) & 0xffff;
  66. else
  67. *val = data;
  68. return PCIBIOS_SUCCESSFUL;
  69. }
  70. int ltq_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn,
  71. int where, int size, u32 val)
  72. {
  73. u32 data = 0;
  74. if (size == 4) {
  75. data = val;
  76. } else {
  77. if (ltq_pci_config_access(PCI_ACCESS_READ, bus,
  78. devfn, where, &data))
  79. return PCIBIOS_DEVICE_NOT_FOUND;
  80. if (size == 1)
  81. data = (data & ~(0xff << ((where & 3) << 3))) |
  82. (val << ((where & 3) << 3));
  83. else if (size == 2)
  84. data = (data & ~(0xffff << ((where & 3) << 3))) |
  85. (val << ((where & 3) << 3));
  86. }
  87. if (ltq_pci_config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
  88. return PCIBIOS_DEVICE_NOT_FOUND;
  89. return PCIBIOS_SUCCESSFUL;
  90. }