msi-octeon.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414
  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2005-2009, 2010 Cavium Networks
  7. */
  8. #include <linux/kernel.h>
  9. #include <linux/init.h>
  10. #include <linux/msi.h>
  11. #include <linux/spinlock.h>
  12. #include <linux/interrupt.h>
  13. #include <asm/octeon/octeon.h>
  14. #include <asm/octeon/cvmx-npi-defs.h>
  15. #include <asm/octeon/cvmx-pci-defs.h>
  16. #include <asm/octeon/cvmx-npei-defs.h>
  17. #include <asm/octeon/cvmx-sli-defs.h>
  18. #include <asm/octeon/cvmx-pexp-defs.h>
  19. #include <asm/octeon/pci-octeon.h>
  20. /*
  21. * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
  22. * in use.
  23. */
  24. static u64 msi_free_irq_bitmask[4];
  25. /*
  26. * Each bit in msi_multiple_irq_bitmask tells that the device using
  27. * this bit in msi_free_irq_bitmask is also using the next bit. This
  28. * is used so we can disable all of the MSI interrupts when a device
  29. * uses multiple.
  30. */
  31. static u64 msi_multiple_irq_bitmask[4];
  32. /*
  33. * This lock controls updates to msi_free_irq_bitmask and
  34. * msi_multiple_irq_bitmask.
  35. */
  36. static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock);
  37. /*
  38. * Number of MSI IRQs used. This variable is set up in
  39. * the module init time.
  40. */
  41. static int msi_irq_size;
  42. /**
  43. * arch_setup_msi_irq() - setup MSI IRQs for a device
  44. * @dev: Device requesting MSI interrupts
  45. * @desc: MSI descriptor
  46. *
  47. * Called when a driver requests MSI interrupts instead of the
  48. * legacy INT A-D. This routine will allocate multiple interrupts
  49. * for MSI devices that support them. A device can override this by
  50. * programming the MSI control bits [6:4] before calling
  51. * pci_enable_msi().
  52. *
  53. * Return: %0 on success, non-%0 on error.
  54. */
  55. int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
  56. {
  57. struct msi_msg msg;
  58. u16 control;
  59. int configured_private_bits;
  60. int request_private_bits;
  61. int irq = 0;
  62. int irq_step;
  63. u64 search_mask;
  64. int index;
  65. if (desc->pci.msi_attrib.is_msix)
  66. return -EINVAL;
  67. /*
  68. * Read the MSI config to figure out how many IRQs this device
  69. * wants. Most devices only want 1, which will give
  70. * configured_private_bits and request_private_bits equal 0.
  71. */
  72. pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
  73. /*
  74. * If the number of private bits has been configured then use
  75. * that value instead of the requested number. This gives the
  76. * driver the chance to override the number of interrupts
  77. * before calling pci_enable_msi().
  78. */
  79. configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4;
  80. if (configured_private_bits == 0) {
  81. /* Nothing is configured, so use the hardware requested size */
  82. request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1;
  83. } else {
  84. /*
  85. * Use the number of configured bits, assuming the
  86. * driver wanted to override the hardware request
  87. * value.
  88. */
  89. request_private_bits = configured_private_bits;
  90. }
  91. /*
  92. * The PCI 2.3 spec mandates that there are at most 32
  93. * interrupts. If this device asks for more, only give it one.
  94. */
  95. if (request_private_bits > 5)
  96. request_private_bits = 0;
  97. try_only_one:
  98. /*
  99. * The IRQs have to be aligned on a power of two based on the
  100. * number being requested.
  101. */
  102. irq_step = 1 << request_private_bits;
  103. /* Mask with one bit for each IRQ */
  104. search_mask = (1 << irq_step) - 1;
  105. /*
  106. * We're going to search msi_free_irq_bitmask_lock for zero
  107. * bits. This represents an MSI interrupt number that isn't in
  108. * use.
  109. */
  110. spin_lock(&msi_free_irq_bitmask_lock);
  111. for (index = 0; index < msi_irq_size/64; index++) {
  112. for (irq = 0; irq < 64; irq += irq_step) {
  113. if ((msi_free_irq_bitmask[index] & (search_mask << irq)) == 0) {
  114. msi_free_irq_bitmask[index] |= search_mask << irq;
  115. msi_multiple_irq_bitmask[index] |= (search_mask >> 1) << irq;
  116. goto msi_irq_allocated;
  117. }
  118. }
  119. }
  120. msi_irq_allocated:
  121. spin_unlock(&msi_free_irq_bitmask_lock);
  122. /* Make sure the search for available interrupts didn't fail */
  123. if (irq >= 64) {
  124. if (request_private_bits) {
  125. pr_err("arch_setup_msi_irq: Unable to find %d free interrupts, trying just one",
  126. 1 << request_private_bits);
  127. request_private_bits = 0;
  128. goto try_only_one;
  129. } else
  130. panic("arch_setup_msi_irq: Unable to find a free MSI interrupt");
  131. }
  132. /* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */
  133. irq += index*64;
  134. irq += OCTEON_IRQ_MSI_BIT0;
  135. switch (octeon_dma_bar_type) {
  136. case OCTEON_DMA_BAR_TYPE_SMALL:
  137. /* When not using big bar, Bar 0 is based at 128MB */
  138. msg.address_lo =
  139. ((128ul << 20) + CVMX_PCI_MSI_RCV) & 0xffffffff;
  140. msg.address_hi = ((128ul << 20) + CVMX_PCI_MSI_RCV) >> 32;
  141. break;
  142. case OCTEON_DMA_BAR_TYPE_BIG:
  143. /* When using big bar, Bar 0 is based at 0 */
  144. msg.address_lo = (0 + CVMX_PCI_MSI_RCV) & 0xffffffff;
  145. msg.address_hi = (0 + CVMX_PCI_MSI_RCV) >> 32;
  146. break;
  147. case OCTEON_DMA_BAR_TYPE_PCIE:
  148. /* When using PCIe, Bar 0 is based at 0 */
  149. /* FIXME CVMX_NPEI_MSI_RCV* other than 0? */
  150. msg.address_lo = (0 + CVMX_NPEI_PCIE_MSI_RCV) & 0xffffffff;
  151. msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32;
  152. break;
  153. case OCTEON_DMA_BAR_TYPE_PCIE2:
  154. /* When using PCIe2, Bar 0 is based at 0 */
  155. msg.address_lo = (0 + CVMX_SLI_PCIE_MSI_RCV) & 0xffffffff;
  156. msg.address_hi = (0 + CVMX_SLI_PCIE_MSI_RCV) >> 32;
  157. break;
  158. default:
  159. panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type");
  160. }
  161. msg.data = irq - OCTEON_IRQ_MSI_BIT0;
  162. /* Update the number of IRQs the device has available to it */
  163. control &= ~PCI_MSI_FLAGS_QSIZE;
  164. control |= request_private_bits << 4;
  165. pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
  166. irq_set_msi_desc(irq, desc);
  167. pci_write_msi_msg(irq, &msg);
  168. return 0;
  169. }
  170. /**
  171. * arch_teardown_msi_irq() - release MSI IRQs for a device
  172. * @irq: The devices first irq number. There may be multiple in sequence.
  173. *
  174. * Called when a device no longer needs its MSI interrupts. All
  175. * MSI interrupts for the device are freed.
  176. */
  177. void arch_teardown_msi_irq(unsigned int irq)
  178. {
  179. int number_irqs;
  180. u64 bitmask;
  181. int index = 0;
  182. int irq0;
  183. if ((irq < OCTEON_IRQ_MSI_BIT0)
  184. || (irq > msi_irq_size + OCTEON_IRQ_MSI_BIT0))
  185. panic("arch_teardown_msi_irq: Attempted to teardown illegal "
  186. "MSI interrupt (%d)", irq);
  187. irq -= OCTEON_IRQ_MSI_BIT0;
  188. index = irq / 64;
  189. irq0 = irq % 64;
  190. /*
  191. * Count the number of IRQs we need to free by looking at the
  192. * msi_multiple_irq_bitmask. Each bit set means that the next
  193. * IRQ is also owned by this device.
  194. */
  195. number_irqs = 0;
  196. while ((irq0 + number_irqs < 64) &&
  197. (msi_multiple_irq_bitmask[index]
  198. & (1ull << (irq0 + number_irqs))))
  199. number_irqs++;
  200. number_irqs++;
  201. /* Mask with one bit for each IRQ */
  202. bitmask = (1 << number_irqs) - 1;
  203. /* Shift the mask to the correct bit location */
  204. bitmask <<= irq0;
  205. if ((msi_free_irq_bitmask[index] & bitmask) != bitmask)
  206. panic("arch_teardown_msi_irq: Attempted to teardown MSI "
  207. "interrupt (%d) not in use", irq);
  208. /* Checks are done, update the in use bitmask */
  209. spin_lock(&msi_free_irq_bitmask_lock);
  210. msi_free_irq_bitmask[index] &= ~bitmask;
  211. msi_multiple_irq_bitmask[index] &= ~bitmask;
  212. spin_unlock(&msi_free_irq_bitmask_lock);
  213. }
  214. static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock);
  215. static u64 msi_rcv_reg[4];
  216. static u64 mis_ena_reg[4];
  217. static void octeon_irq_msi_enable_pcie(struct irq_data *data)
  218. {
  219. u64 en;
  220. unsigned long flags;
  221. int msi_number = data->irq - OCTEON_IRQ_MSI_BIT0;
  222. int irq_index = msi_number >> 6;
  223. int irq_bit = msi_number & 0x3f;
  224. raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
  225. en = cvmx_read_csr(mis_ena_reg[irq_index]);
  226. en |= 1ull << irq_bit;
  227. cvmx_write_csr(mis_ena_reg[irq_index], en);
  228. cvmx_read_csr(mis_ena_reg[irq_index]);
  229. raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
  230. }
  231. static void octeon_irq_msi_disable_pcie(struct irq_data *data)
  232. {
  233. u64 en;
  234. unsigned long flags;
  235. int msi_number = data->irq - OCTEON_IRQ_MSI_BIT0;
  236. int irq_index = msi_number >> 6;
  237. int irq_bit = msi_number & 0x3f;
  238. raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
  239. en = cvmx_read_csr(mis_ena_reg[irq_index]);
  240. en &= ~(1ull << irq_bit);
  241. cvmx_write_csr(mis_ena_reg[irq_index], en);
  242. cvmx_read_csr(mis_ena_reg[irq_index]);
  243. raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
  244. }
  245. static struct irq_chip octeon_irq_chip_msi_pcie = {
  246. .name = "MSI",
  247. .irq_enable = octeon_irq_msi_enable_pcie,
  248. .irq_disable = octeon_irq_msi_disable_pcie,
  249. };
  250. static void octeon_irq_msi_enable_pci(struct irq_data *data)
  251. {
  252. /*
  253. * Octeon PCI doesn't have the ability to mask/unmask MSI
  254. * interrupts individually. Instead of masking/unmasking them
  255. * in groups of 16, we simple assume MSI devices are well
  256. * behaved. MSI interrupts are always enable and the ACK is
  257. * assumed to be enough
  258. */
  259. }
  260. static void octeon_irq_msi_disable_pci(struct irq_data *data)
  261. {
  262. /* See comment in enable */
  263. }
  264. static struct irq_chip octeon_irq_chip_msi_pci = {
  265. .name = "MSI",
  266. .irq_enable = octeon_irq_msi_enable_pci,
  267. .irq_disable = octeon_irq_msi_disable_pci,
  268. };
  269. /*
  270. * Called by the interrupt handling code when an MSI interrupt
  271. * occurs.
  272. */
  273. static irqreturn_t __octeon_msi_do_interrupt(int index, u64 msi_bits)
  274. {
  275. int irq;
  276. int bit;
  277. bit = fls64(msi_bits);
  278. if (bit) {
  279. bit--;
  280. /* Acknowledge it first. */
  281. cvmx_write_csr(msi_rcv_reg[index], 1ull << bit);
  282. irq = bit + OCTEON_IRQ_MSI_BIT0 + 64 * index;
  283. do_IRQ(irq);
  284. return IRQ_HANDLED;
  285. }
  286. return IRQ_NONE;
  287. }
  288. #define OCTEON_MSI_INT_HANDLER_X(x) \
  289. static irqreturn_t octeon_msi_interrupt##x(int cpl, void *dev_id) \
  290. { \
  291. u64 msi_bits = cvmx_read_csr(msi_rcv_reg[(x)]); \
  292. return __octeon_msi_do_interrupt((x), msi_bits); \
  293. }
  294. /*
  295. * Create octeon_msi_interrupt{0-3} function body
  296. */
  297. OCTEON_MSI_INT_HANDLER_X(0);
  298. OCTEON_MSI_INT_HANDLER_X(1);
  299. OCTEON_MSI_INT_HANDLER_X(2);
  300. OCTEON_MSI_INT_HANDLER_X(3);
  301. /*
  302. * Initializes the MSI interrupt handling code
  303. */
  304. int __init octeon_msi_initialize(void)
  305. {
  306. int irq;
  307. struct irq_chip *msi;
  308. if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_INVALID) {
  309. return 0;
  310. } else if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE) {
  311. msi_rcv_reg[0] = CVMX_PEXP_NPEI_MSI_RCV0;
  312. msi_rcv_reg[1] = CVMX_PEXP_NPEI_MSI_RCV1;
  313. msi_rcv_reg[2] = CVMX_PEXP_NPEI_MSI_RCV2;
  314. msi_rcv_reg[3] = CVMX_PEXP_NPEI_MSI_RCV3;
  315. mis_ena_reg[0] = CVMX_PEXP_NPEI_MSI_ENB0;
  316. mis_ena_reg[1] = CVMX_PEXP_NPEI_MSI_ENB1;
  317. mis_ena_reg[2] = CVMX_PEXP_NPEI_MSI_ENB2;
  318. mis_ena_reg[3] = CVMX_PEXP_NPEI_MSI_ENB3;
  319. msi = &octeon_irq_chip_msi_pcie;
  320. } else {
  321. msi_rcv_reg[0] = CVMX_NPI_NPI_MSI_RCV;
  322. #define INVALID_GENERATE_ADE 0x8700000000000000ULL;
  323. msi_rcv_reg[1] = INVALID_GENERATE_ADE;
  324. msi_rcv_reg[2] = INVALID_GENERATE_ADE;
  325. msi_rcv_reg[3] = INVALID_GENERATE_ADE;
  326. mis_ena_reg[0] = INVALID_GENERATE_ADE;
  327. mis_ena_reg[1] = INVALID_GENERATE_ADE;
  328. mis_ena_reg[2] = INVALID_GENERATE_ADE;
  329. mis_ena_reg[3] = INVALID_GENERATE_ADE;
  330. msi = &octeon_irq_chip_msi_pci;
  331. }
  332. for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_LAST; irq++)
  333. irq_set_chip_and_handler(irq, msi, handle_simple_irq);
  334. if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
  335. if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0,
  336. 0, "MSI[0:63]", octeon_msi_interrupt0))
  337. panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
  338. if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt1,
  339. 0, "MSI[64:127]", octeon_msi_interrupt1))
  340. panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed");
  341. if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt2,
  342. 0, "MSI[127:191]", octeon_msi_interrupt2))
  343. panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed");
  344. if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt3,
  345. 0, "MSI[192:255]", octeon_msi_interrupt3))
  346. panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed");
  347. msi_irq_size = 256;
  348. } else if (octeon_is_pci_host()) {
  349. if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0,
  350. 0, "MSI[0:15]", octeon_msi_interrupt0))
  351. panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
  352. if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt0,
  353. 0, "MSI[16:31]", octeon_msi_interrupt0))
  354. panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed");
  355. if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt0,
  356. 0, "MSI[32:47]", octeon_msi_interrupt0))
  357. panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed");
  358. if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt0,
  359. 0, "MSI[48:63]", octeon_msi_interrupt0))
  360. panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed");
  361. msi_irq_size = 64;
  362. }
  363. return 0;
  364. }
  365. subsys_initcall(octeon_msi_initialize);