dump_tlb.c 5.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Dump R4x00 TLB for debugging purposes.
  4. *
  5. * Copyright (C) 1994, 1995 by Waldorf Electronics, written by Ralf Baechle.
  6. * Copyright (C) 1999 by Silicon Graphics, Inc.
  7. */
  8. #include <linux/kernel.h>
  9. #include <linux/mm.h>
  10. #include <asm/hazards.h>
  11. #include <asm/mipsregs.h>
  12. #include <asm/mmu_context.h>
  13. #include <asm/page.h>
  14. #include <asm/tlbdebug.h>
  15. void dump_tlb_regs(void)
  16. {
  17. const int field = 2 * sizeof(unsigned long);
  18. pr_info("Index : %0x\n", read_c0_index());
  19. pr_info("PageMask : %0x\n", read_c0_pagemask());
  20. if (cpu_has_guestid)
  21. pr_info("GuestCtl1: %0x\n", read_c0_guestctl1());
  22. pr_info("EntryHi : %0*lx\n", field, read_c0_entryhi());
  23. pr_info("EntryLo0 : %0*lx\n", field, read_c0_entrylo0());
  24. pr_info("EntryLo1 : %0*lx\n", field, read_c0_entrylo1());
  25. pr_info("Wired : %0x\n", read_c0_wired());
  26. switch (current_cpu_type()) {
  27. case CPU_R10000:
  28. case CPU_R12000:
  29. case CPU_R14000:
  30. case CPU_R16000:
  31. pr_info("FrameMask: %0x\n", read_c0_framemask());
  32. break;
  33. }
  34. if (cpu_has_small_pages || cpu_has_rixi || cpu_has_xpa)
  35. pr_info("PageGrain: %0x\n", read_c0_pagegrain());
  36. if (cpu_has_htw) {
  37. pr_info("PWField : %0*lx\n", field, read_c0_pwfield());
  38. pr_info("PWSize : %0*lx\n", field, read_c0_pwsize());
  39. pr_info("PWCtl : %0x\n", read_c0_pwctl());
  40. }
  41. }
  42. static inline const char *msk2str(unsigned int mask)
  43. {
  44. switch (mask) {
  45. case PM_4K: return "4kb";
  46. case PM_16K: return "16kb";
  47. case PM_64K: return "64kb";
  48. case PM_256K: return "256kb";
  49. #ifdef CONFIG_CPU_CAVIUM_OCTEON
  50. case PM_8K: return "8kb";
  51. case PM_32K: return "32kb";
  52. case PM_128K: return "128kb";
  53. case PM_512K: return "512kb";
  54. case PM_2M: return "2Mb";
  55. case PM_8M: return "8Mb";
  56. case PM_32M: return "32Mb";
  57. #endif
  58. }
  59. return "";
  60. }
  61. static void dump_tlb(int first, int last)
  62. {
  63. unsigned long s_entryhi, entryhi, asid, mmid;
  64. unsigned long long entrylo0, entrylo1, pa;
  65. unsigned int s_index, s_pagemask, s_guestctl1 = 0;
  66. unsigned int pagemask, guestctl1 = 0, c0, c1, i;
  67. unsigned long asidmask = cpu_asid_mask(&current_cpu_data);
  68. int asidwidth = DIV_ROUND_UP(ilog2(asidmask) + 1, 4);
  69. unsigned long s_mmid;
  70. #ifdef CONFIG_32BIT
  71. bool xpa = cpu_has_xpa && (read_c0_pagegrain() & PG_ELPA);
  72. int pwidth = xpa ? 11 : 8;
  73. int vwidth = 8;
  74. #else
  75. bool xpa = false;
  76. int pwidth = 11;
  77. int vwidth = 11;
  78. #endif
  79. s_pagemask = read_c0_pagemask();
  80. s_entryhi = read_c0_entryhi();
  81. s_index = read_c0_index();
  82. if (cpu_has_mmid)
  83. asid = s_mmid = read_c0_memorymapid();
  84. else
  85. asid = s_entryhi & asidmask;
  86. if (cpu_has_guestid)
  87. s_guestctl1 = read_c0_guestctl1();
  88. for (i = first; i <= last; i++) {
  89. write_c0_index(i);
  90. mtc0_tlbr_hazard();
  91. tlb_read();
  92. tlb_read_hazard();
  93. pagemask = read_c0_pagemask();
  94. entryhi = read_c0_entryhi();
  95. entrylo0 = read_c0_entrylo0();
  96. entrylo1 = read_c0_entrylo1();
  97. if (cpu_has_mmid)
  98. mmid = read_c0_memorymapid();
  99. else
  100. mmid = entryhi & asidmask;
  101. if (cpu_has_guestid)
  102. guestctl1 = read_c0_guestctl1();
  103. /* EHINV bit marks entire entry as invalid */
  104. if (cpu_has_tlbinv && entryhi & MIPS_ENTRYHI_EHINV)
  105. continue;
  106. /*
  107. * Prior to tlbinv, unused entries have a virtual address of
  108. * CKSEG0.
  109. */
  110. if ((entryhi & ~0x1ffffUL) == CKSEG0)
  111. continue;
  112. /*
  113. * ASID takes effect in absence of G (global) bit.
  114. * We check both G bits, even though architecturally they should
  115. * match one another, because some revisions of the SB1 core may
  116. * leave only a single G bit set after a machine check exception
  117. * due to duplicate TLB entry.
  118. */
  119. if (!((entrylo0 | entrylo1) & ENTRYLO_G) && (mmid != asid))
  120. continue;
  121. /*
  122. * Only print entries in use
  123. */
  124. printk("Index: %2d pgmask=%s ", i, msk2str(pagemask));
  125. c0 = (entrylo0 & ENTRYLO_C) >> ENTRYLO_C_SHIFT;
  126. c1 = (entrylo1 & ENTRYLO_C) >> ENTRYLO_C_SHIFT;
  127. pr_cont("va=%0*lx asid=%0*lx",
  128. vwidth, (entryhi & ~0x1fffUL),
  129. asidwidth, mmid);
  130. if (cpu_has_guestid)
  131. pr_cont(" gid=%02lx",
  132. (guestctl1 & MIPS_GCTL1_RID)
  133. >> MIPS_GCTL1_RID_SHIFT);
  134. /* RI/XI are in awkward places, so mask them off separately */
  135. pa = entrylo0 & ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI);
  136. if (xpa)
  137. pa |= (unsigned long long)readx_c0_entrylo0() << 30;
  138. pa = (pa << 6) & PAGE_MASK;
  139. pr_cont("\n\t[");
  140. if (cpu_has_rixi)
  141. pr_cont("ri=%d xi=%d ",
  142. (entrylo0 & MIPS_ENTRYLO_RI) ? 1 : 0,
  143. (entrylo0 & MIPS_ENTRYLO_XI) ? 1 : 0);
  144. pr_cont("pa=%0*llx c=%d d=%d v=%d g=%d] [",
  145. pwidth, pa, c0,
  146. (entrylo0 & ENTRYLO_D) ? 1 : 0,
  147. (entrylo0 & ENTRYLO_V) ? 1 : 0,
  148. (entrylo0 & ENTRYLO_G) ? 1 : 0);
  149. /* RI/XI are in awkward places, so mask them off separately */
  150. pa = entrylo1 & ~(MIPS_ENTRYLO_RI | MIPS_ENTRYLO_XI);
  151. if (xpa)
  152. pa |= (unsigned long long)readx_c0_entrylo1() << 30;
  153. pa = (pa << 6) & PAGE_MASK;
  154. if (cpu_has_rixi)
  155. pr_cont("ri=%d xi=%d ",
  156. (entrylo1 & MIPS_ENTRYLO_RI) ? 1 : 0,
  157. (entrylo1 & MIPS_ENTRYLO_XI) ? 1 : 0);
  158. pr_cont("pa=%0*llx c=%d d=%d v=%d g=%d]\n",
  159. pwidth, pa, c1,
  160. (entrylo1 & ENTRYLO_D) ? 1 : 0,
  161. (entrylo1 & ENTRYLO_V) ? 1 : 0,
  162. (entrylo1 & ENTRYLO_G) ? 1 : 0);
  163. }
  164. printk("\n");
  165. write_c0_entryhi(s_entryhi);
  166. write_c0_index(s_index);
  167. write_c0_pagemask(s_pagemask);
  168. if (cpu_has_guestid)
  169. write_c0_guestctl1(s_guestctl1);
  170. }
  171. void dump_tlb_all(void)
  172. {
  173. dump_tlb(0, current_cpu_data.tlbsize - 1);
  174. }