watch.c 5.3 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2008 David Daney
  7. */
  8. #include <linux/sched.h>
  9. #include <asm/processor.h>
  10. #include <asm/watch.h>
  11. /*
  12. * Install the watch registers for the current thread. A maximum of
  13. * four registers are installed although the machine may have more.
  14. */
  15. void mips_install_watch_registers(struct task_struct *t)
  16. {
  17. struct mips3264_watch_reg_state *watches = &t->thread.watch.mips3264;
  18. unsigned int watchhi = MIPS_WATCHHI_G | /* Trap all ASIDs */
  19. MIPS_WATCHHI_IRW; /* Clear result bits */
  20. switch (current_cpu_data.watch_reg_use_cnt) {
  21. default:
  22. BUG();
  23. case 4:
  24. write_c0_watchlo3(watches->watchlo[3]);
  25. write_c0_watchhi3(watchhi | watches->watchhi[3]);
  26. fallthrough;
  27. case 3:
  28. write_c0_watchlo2(watches->watchlo[2]);
  29. write_c0_watchhi2(watchhi | watches->watchhi[2]);
  30. fallthrough;
  31. case 2:
  32. write_c0_watchlo1(watches->watchlo[1]);
  33. write_c0_watchhi1(watchhi | watches->watchhi[1]);
  34. fallthrough;
  35. case 1:
  36. write_c0_watchlo0(watches->watchlo[0]);
  37. write_c0_watchhi0(watchhi | watches->watchhi[0]);
  38. }
  39. }
  40. /*
  41. * Read back the watchhi registers so the user space debugger has
  42. * access to the I, R, and W bits. A maximum of four registers are
  43. * read although the machine may have more.
  44. */
  45. void mips_read_watch_registers(void)
  46. {
  47. struct mips3264_watch_reg_state *watches =
  48. &current->thread.watch.mips3264;
  49. unsigned int watchhi_mask = MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW;
  50. switch (current_cpu_data.watch_reg_use_cnt) {
  51. default:
  52. BUG();
  53. case 4:
  54. watches->watchhi[3] = (read_c0_watchhi3() & watchhi_mask);
  55. fallthrough;
  56. case 3:
  57. watches->watchhi[2] = (read_c0_watchhi2() & watchhi_mask);
  58. fallthrough;
  59. case 2:
  60. watches->watchhi[1] = (read_c0_watchhi1() & watchhi_mask);
  61. fallthrough;
  62. case 1:
  63. watches->watchhi[0] = (read_c0_watchhi0() & watchhi_mask);
  64. }
  65. if (current_cpu_data.watch_reg_use_cnt == 1 &&
  66. (watches->watchhi[0] & MIPS_WATCHHI_IRW) == 0) {
  67. /* Pathological case of release 1 architecture that
  68. * doesn't set the condition bits. We assume that
  69. * since we got here, the watch condition was met and
  70. * signal that the conditions requested in watchlo
  71. * were met. */
  72. watches->watchhi[0] |= (watches->watchlo[0] & MIPS_WATCHHI_IRW);
  73. }
  74. }
  75. /*
  76. * Disable all watch registers. Although only four registers are
  77. * installed, all are cleared to eliminate the possibility of endless
  78. * looping in the watch handler.
  79. */
  80. void mips_clear_watch_registers(void)
  81. {
  82. switch (current_cpu_data.watch_reg_count) {
  83. default:
  84. BUG();
  85. case 8:
  86. write_c0_watchlo7(0);
  87. fallthrough;
  88. case 7:
  89. write_c0_watchlo6(0);
  90. fallthrough;
  91. case 6:
  92. write_c0_watchlo5(0);
  93. fallthrough;
  94. case 5:
  95. write_c0_watchlo4(0);
  96. fallthrough;
  97. case 4:
  98. write_c0_watchlo3(0);
  99. fallthrough;
  100. case 3:
  101. write_c0_watchlo2(0);
  102. fallthrough;
  103. case 2:
  104. write_c0_watchlo1(0);
  105. fallthrough;
  106. case 1:
  107. write_c0_watchlo0(0);
  108. }
  109. }
  110. void mips_probe_watch_registers(struct cpuinfo_mips *c)
  111. {
  112. unsigned int t;
  113. if ((c->options & MIPS_CPU_WATCH) == 0)
  114. return;
  115. /*
  116. * Check which of the I,R and W bits are supported, then
  117. * disable the register.
  118. */
  119. write_c0_watchlo0(MIPS_WATCHLO_IRW);
  120. back_to_back_c0_hazard();
  121. t = read_c0_watchlo0();
  122. write_c0_watchlo0(0);
  123. c->watch_reg_masks[0] = t & MIPS_WATCHLO_IRW;
  124. /* Write the mask bits and read them back to determine which
  125. * can be used. */
  126. c->watch_reg_count = 1;
  127. c->watch_reg_use_cnt = 1;
  128. t = read_c0_watchhi0();
  129. write_c0_watchhi0(t | MIPS_WATCHHI_MASK);
  130. back_to_back_c0_hazard();
  131. t = read_c0_watchhi0();
  132. c->watch_reg_masks[0] |= (t & MIPS_WATCHHI_MASK);
  133. if ((t & MIPS_WATCHHI_M) == 0)
  134. return;
  135. write_c0_watchlo1(MIPS_WATCHLO_IRW);
  136. back_to_back_c0_hazard();
  137. t = read_c0_watchlo1();
  138. write_c0_watchlo1(0);
  139. c->watch_reg_masks[1] = t & MIPS_WATCHLO_IRW;
  140. c->watch_reg_count = 2;
  141. c->watch_reg_use_cnt = 2;
  142. t = read_c0_watchhi1();
  143. write_c0_watchhi1(t | MIPS_WATCHHI_MASK);
  144. back_to_back_c0_hazard();
  145. t = read_c0_watchhi1();
  146. c->watch_reg_masks[1] |= (t & MIPS_WATCHHI_MASK);
  147. if ((t & MIPS_WATCHHI_M) == 0)
  148. return;
  149. write_c0_watchlo2(MIPS_WATCHLO_IRW);
  150. back_to_back_c0_hazard();
  151. t = read_c0_watchlo2();
  152. write_c0_watchlo2(0);
  153. c->watch_reg_masks[2] = t & MIPS_WATCHLO_IRW;
  154. c->watch_reg_count = 3;
  155. c->watch_reg_use_cnt = 3;
  156. t = read_c0_watchhi2();
  157. write_c0_watchhi2(t | MIPS_WATCHHI_MASK);
  158. back_to_back_c0_hazard();
  159. t = read_c0_watchhi2();
  160. c->watch_reg_masks[2] |= (t & MIPS_WATCHHI_MASK);
  161. if ((t & MIPS_WATCHHI_M) == 0)
  162. return;
  163. write_c0_watchlo3(MIPS_WATCHLO_IRW);
  164. back_to_back_c0_hazard();
  165. t = read_c0_watchlo3();
  166. write_c0_watchlo3(0);
  167. c->watch_reg_masks[3] = t & MIPS_WATCHLO_IRW;
  168. c->watch_reg_count = 4;
  169. c->watch_reg_use_cnt = 4;
  170. t = read_c0_watchhi3();
  171. write_c0_watchhi3(t | MIPS_WATCHHI_MASK);
  172. back_to_back_c0_hazard();
  173. t = read_c0_watchhi3();
  174. c->watch_reg_masks[3] |= (t & MIPS_WATCHHI_MASK);
  175. if ((t & MIPS_WATCHHI_M) == 0)
  176. return;
  177. /* We use at most 4, but probe and report up to 8. */
  178. c->watch_reg_count = 5;
  179. t = read_c0_watchhi4();
  180. if ((t & MIPS_WATCHHI_M) == 0)
  181. return;
  182. c->watch_reg_count = 6;
  183. t = read_c0_watchhi5();
  184. if ((t & MIPS_WATCHHI_M) == 0)
  185. return;
  186. c->watch_reg_count = 7;
  187. t = read_c0_watchhi6();
  188. if ((t & MIPS_WATCHHI_M) == 0)
  189. return;
  190. c->watch_reg_count = 8;
  191. }