uprobes.c 6.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. #include <linux/highmem.h>
  3. #include <linux/kdebug.h>
  4. #include <linux/types.h>
  5. #include <linux/notifier.h>
  6. #include <linux/sched.h>
  7. #include <linux/uprobes.h>
  8. #include <asm/branch.h>
  9. #include <asm/cpu-features.h>
  10. #include <asm/ptrace.h>
  11. #include "probes-common.h"
  12. static inline int insn_has_delay_slot(const union mips_instruction insn)
  13. {
  14. return __insn_has_delay_slot(insn);
  15. }
  16. /**
  17. * arch_uprobe_analyze_insn - instruction analysis including validity and fixups.
  18. * @mm: the probed address space.
  19. * @arch_uprobe: the probepoint information.
  20. * @addr: virtual address at which to install the probepoint
  21. * Return 0 on success or a -ve number on error.
  22. */
  23. int arch_uprobe_analyze_insn(struct arch_uprobe *aup,
  24. struct mm_struct *mm, unsigned long addr)
  25. {
  26. union mips_instruction inst;
  27. /*
  28. * For the time being this also blocks attempts to use uprobes with
  29. * MIPS16 and microMIPS.
  30. */
  31. if (addr & 0x03)
  32. return -EINVAL;
  33. inst.word = aup->insn[0];
  34. if (__insn_is_compact_branch(inst)) {
  35. pr_notice("Uprobes for compact branches are not supported\n");
  36. return -EINVAL;
  37. }
  38. aup->ixol[0] = aup->insn[insn_has_delay_slot(inst)];
  39. aup->ixol[1] = UPROBE_BRK_UPROBE_XOL; /* NOP */
  40. return 0;
  41. }
  42. /**
  43. * is_trap_insn - check if the instruction is a trap variant
  44. * @insn: instruction to be checked.
  45. * Returns true if @insn is a trap variant.
  46. *
  47. * This definition overrides the weak definition in kernel/events/uprobes.c.
  48. * and is needed for the case where an architecture has multiple trap
  49. * instructions (like PowerPC or MIPS). We treat BREAK just like the more
  50. * modern conditional trap instructions.
  51. */
  52. bool is_trap_insn(uprobe_opcode_t *insn)
  53. {
  54. union mips_instruction inst;
  55. inst.word = *insn;
  56. switch (inst.i_format.opcode) {
  57. case spec_op:
  58. switch (inst.r_format.func) {
  59. case break_op:
  60. case teq_op:
  61. case tge_op:
  62. case tgeu_op:
  63. case tlt_op:
  64. case tltu_op:
  65. case tne_op:
  66. return true;
  67. }
  68. break;
  69. case bcond_op: /* Yes, really ... */
  70. switch (inst.u_format.rt) {
  71. case teqi_op:
  72. case tgei_op:
  73. case tgeiu_op:
  74. case tlti_op:
  75. case tltiu_op:
  76. case tnei_op:
  77. return true;
  78. }
  79. break;
  80. }
  81. return false;
  82. }
  83. #define UPROBE_TRAP_NR ULONG_MAX
  84. /*
  85. * arch_uprobe_pre_xol - prepare to execute out of line.
  86. * @auprobe: the probepoint information.
  87. * @regs: reflects the saved user state of current task.
  88. */
  89. int arch_uprobe_pre_xol(struct arch_uprobe *aup, struct pt_regs *regs)
  90. {
  91. struct uprobe_task *utask = current->utask;
  92. /*
  93. * Now find the EPC where to resume after the breakpoint has been
  94. * dealt with. This may require emulation of a branch.
  95. */
  96. aup->resume_epc = regs->cp0_epc + 4;
  97. if (insn_has_delay_slot((union mips_instruction) aup->insn[0])) {
  98. __compute_return_epc_for_insn(regs,
  99. (union mips_instruction) aup->insn[0]);
  100. aup->resume_epc = regs->cp0_epc;
  101. }
  102. utask->autask.saved_trap_nr = current->thread.trap_nr;
  103. current->thread.trap_nr = UPROBE_TRAP_NR;
  104. regs->cp0_epc = current->utask->xol_vaddr;
  105. return 0;
  106. }
  107. int arch_uprobe_post_xol(struct arch_uprobe *aup, struct pt_regs *regs)
  108. {
  109. struct uprobe_task *utask = current->utask;
  110. current->thread.trap_nr = utask->autask.saved_trap_nr;
  111. regs->cp0_epc = aup->resume_epc;
  112. return 0;
  113. }
  114. /*
  115. * If xol insn itself traps and generates a signal(Say,
  116. * SIGILL/SIGSEGV/etc), then detect the case where a singlestepped
  117. * instruction jumps back to its own address. It is assumed that anything
  118. * like do_page_fault/do_trap/etc sets thread.trap_nr != -1.
  119. *
  120. * arch_uprobe_pre_xol/arch_uprobe_post_xol save/restore thread.trap_nr,
  121. * arch_uprobe_xol_was_trapped() simply checks that ->trap_nr is not equal to
  122. * UPROBE_TRAP_NR == -1 set by arch_uprobe_pre_xol().
  123. */
  124. bool arch_uprobe_xol_was_trapped(struct task_struct *tsk)
  125. {
  126. if (tsk->thread.trap_nr != UPROBE_TRAP_NR)
  127. return true;
  128. return false;
  129. }
  130. int arch_uprobe_exception_notify(struct notifier_block *self,
  131. unsigned long val, void *data)
  132. {
  133. struct die_args *args = data;
  134. struct pt_regs *regs = args->regs;
  135. /* regs == NULL is a kernel bug */
  136. if (WARN_ON(!regs))
  137. return NOTIFY_DONE;
  138. /* We are only interested in userspace traps */
  139. if (!user_mode(regs))
  140. return NOTIFY_DONE;
  141. switch (val) {
  142. case DIE_UPROBE:
  143. if (uprobe_pre_sstep_notifier(regs))
  144. return NOTIFY_STOP;
  145. break;
  146. case DIE_UPROBE_XOL:
  147. if (uprobe_post_sstep_notifier(regs))
  148. return NOTIFY_STOP;
  149. break;
  150. default:
  151. break;
  152. }
  153. return 0;
  154. }
  155. /*
  156. * This function gets called when XOL instruction either gets trapped or
  157. * the thread has a fatal signal. Reset the instruction pointer to its
  158. * probed address for the potential restart or for post mortem analysis.
  159. */
  160. void arch_uprobe_abort_xol(struct arch_uprobe *aup,
  161. struct pt_regs *regs)
  162. {
  163. struct uprobe_task *utask = current->utask;
  164. instruction_pointer_set(regs, utask->vaddr);
  165. }
  166. unsigned long arch_uretprobe_hijack_return_addr(
  167. unsigned long trampoline_vaddr, struct pt_regs *regs)
  168. {
  169. unsigned long ra;
  170. ra = regs->regs[31];
  171. /* Replace the return address with the trampoline address */
  172. regs->regs[31] = trampoline_vaddr;
  173. return ra;
  174. }
  175. /**
  176. * set_swbp - store breakpoint at a given address.
  177. * @auprobe: arch specific probepoint information.
  178. * @mm: the probed process address space.
  179. * @vaddr: the virtual address to insert the opcode.
  180. *
  181. * For mm @mm, store the breakpoint instruction at @vaddr.
  182. * Return 0 (success) or a negative errno.
  183. *
  184. * This version overrides the weak version in kernel/events/uprobes.c.
  185. * It is required to handle MIPS16 and microMIPS.
  186. */
  187. int __weak set_swbp(struct arch_uprobe *auprobe, struct mm_struct *mm,
  188. unsigned long vaddr)
  189. {
  190. return uprobe_write_opcode(auprobe, mm, vaddr, UPROBE_SWBP_INSN);
  191. }
  192. void arch_uprobe_copy_ixol(struct page *page, unsigned long vaddr,
  193. void *src, unsigned long len)
  194. {
  195. unsigned long kaddr, kstart;
  196. /* Initialize the slot */
  197. kaddr = (unsigned long)kmap_atomic(page);
  198. kstart = kaddr + (vaddr & ~PAGE_MASK);
  199. memcpy((void *)kstart, src, len);
  200. flush_icache_range(kstart, kstart + len);
  201. kunmap_atomic((void *)kaddr);
  202. }
  203. /**
  204. * uprobe_get_swbp_addr - compute address of swbp given post-swbp regs
  205. * @regs: Reflects the saved state of the task after it has hit a breakpoint
  206. * instruction.
  207. * Return the address of the breakpoint instruction.
  208. *
  209. * This overrides the weak version in kernel/events/uprobes.c.
  210. */
  211. unsigned long uprobe_get_swbp_addr(struct pt_regs *regs)
  212. {
  213. return instruction_pointer(regs);
  214. }
  215. /*
  216. * See if the instruction can be emulated.
  217. * Returns true if instruction was emulated, false otherwise.
  218. *
  219. * For now we always emulate so this function just returns false.
  220. */
  221. bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
  222. {
  223. return false;
  224. }