traps.c 62 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
  7. * Copyright (C) 1995, 1996 Paul M. Antoine
  8. * Copyright (C) 1998 Ulf Carlsson
  9. * Copyright (C) 1999 Silicon Graphics, Inc.
  10. * Kevin D. Kissell, [email protected] and Carsten Langgaard, [email protected]
  11. * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
  12. * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
  13. * Copyright (C) 2014, Imagination Technologies Ltd.
  14. */
  15. #include <linux/bitops.h>
  16. #include <linux/bug.h>
  17. #include <linux/compiler.h>
  18. #include <linux/context_tracking.h>
  19. #include <linux/cpu_pm.h>
  20. #include <linux/kexec.h>
  21. #include <linux/init.h>
  22. #include <linux/kernel.h>
  23. #include <linux/module.h>
  24. #include <linux/extable.h>
  25. #include <linux/mm.h>
  26. #include <linux/sched/mm.h>
  27. #include <linux/sched/debug.h>
  28. #include <linux/smp.h>
  29. #include <linux/spinlock.h>
  30. #include <linux/kallsyms.h>
  31. #include <linux/memblock.h>
  32. #include <linux/interrupt.h>
  33. #include <linux/ptrace.h>
  34. #include <linux/kgdb.h>
  35. #include <linux/kdebug.h>
  36. #include <linux/kprobes.h>
  37. #include <linux/notifier.h>
  38. #include <linux/kdb.h>
  39. #include <linux/irq.h>
  40. #include <linux/perf_event.h>
  41. #include <asm/addrspace.h>
  42. #include <asm/bootinfo.h>
  43. #include <asm/branch.h>
  44. #include <asm/break.h>
  45. #include <asm/cop2.h>
  46. #include <asm/cpu.h>
  47. #include <asm/cpu-type.h>
  48. #include <asm/dsp.h>
  49. #include <asm/fpu.h>
  50. #include <asm/fpu_emulator.h>
  51. #include <asm/idle.h>
  52. #include <asm/isa-rev.h>
  53. #include <asm/mips-cps.h>
  54. #include <asm/mips-r2-to-r6-emul.h>
  55. #include <asm/mipsregs.h>
  56. #include <asm/mipsmtregs.h>
  57. #include <asm/module.h>
  58. #include <asm/msa.h>
  59. #include <asm/ptrace.h>
  60. #include <asm/sections.h>
  61. #include <asm/siginfo.h>
  62. #include <asm/tlbdebug.h>
  63. #include <asm/traps.h>
  64. #include <linux/uaccess.h>
  65. #include <asm/watch.h>
  66. #include <asm/mmu_context.h>
  67. #include <asm/types.h>
  68. #include <asm/stacktrace.h>
  69. #include <asm/tlbex.h>
  70. #include <asm/uasm.h>
  71. #include <asm/mach-loongson64/cpucfg-emul.h>
  72. #include "access-helper.h"
  73. extern void check_wait(void);
  74. extern asmlinkage void rollback_handle_int(void);
  75. extern asmlinkage void handle_int(void);
  76. extern asmlinkage void handle_adel(void);
  77. extern asmlinkage void handle_ades(void);
  78. extern asmlinkage void handle_ibe(void);
  79. extern asmlinkage void handle_dbe(void);
  80. extern asmlinkage void handle_sys(void);
  81. extern asmlinkage void handle_bp(void);
  82. extern asmlinkage void handle_ri(void);
  83. extern asmlinkage void handle_ri_rdhwr_tlbp(void);
  84. extern asmlinkage void handle_ri_rdhwr(void);
  85. extern asmlinkage void handle_cpu(void);
  86. extern asmlinkage void handle_ov(void);
  87. extern asmlinkage void handle_tr(void);
  88. extern asmlinkage void handle_msa_fpe(void);
  89. extern asmlinkage void handle_fpe(void);
  90. extern asmlinkage void handle_ftlb(void);
  91. extern asmlinkage void handle_gsexc(void);
  92. extern asmlinkage void handle_msa(void);
  93. extern asmlinkage void handle_mdmx(void);
  94. extern asmlinkage void handle_watch(void);
  95. extern asmlinkage void handle_mt(void);
  96. extern asmlinkage void handle_dsp(void);
  97. extern asmlinkage void handle_mcheck(void);
  98. extern asmlinkage void handle_reserved(void);
  99. extern void tlb_do_page_fault_0(void);
  100. void (*board_be_init)(void);
  101. static int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
  102. void (*board_nmi_handler_setup)(void);
  103. void (*board_ejtag_handler_setup)(void);
  104. void (*board_bind_eic_interrupt)(int irq, int regset);
  105. void (*board_ebase_setup)(void);
  106. void(*board_cache_error_setup)(void);
  107. void mips_set_be_handler(int (*handler)(struct pt_regs *regs, int is_fixup))
  108. {
  109. board_be_handler = handler;
  110. }
  111. EXPORT_SYMBOL_GPL(mips_set_be_handler);
  112. static void show_raw_backtrace(unsigned long reg29, const char *loglvl,
  113. bool user)
  114. {
  115. unsigned long *sp = (unsigned long *)(reg29 & ~3);
  116. unsigned long addr;
  117. printk("%sCall Trace:", loglvl);
  118. #ifdef CONFIG_KALLSYMS
  119. printk("%s\n", loglvl);
  120. #endif
  121. while (!kstack_end(sp)) {
  122. if (__get_addr(&addr, sp++, user)) {
  123. printk("%s (Bad stack address)", loglvl);
  124. break;
  125. }
  126. if (__kernel_text_address(addr))
  127. print_ip_sym(loglvl, addr);
  128. }
  129. printk("%s\n", loglvl);
  130. }
  131. #ifdef CONFIG_KALLSYMS
  132. int raw_show_trace;
  133. static int __init set_raw_show_trace(char *str)
  134. {
  135. raw_show_trace = 1;
  136. return 1;
  137. }
  138. __setup("raw_show_trace", set_raw_show_trace);
  139. #endif
  140. static void show_backtrace(struct task_struct *task, const struct pt_regs *regs,
  141. const char *loglvl, bool user)
  142. {
  143. unsigned long sp = regs->regs[29];
  144. unsigned long ra = regs->regs[31];
  145. unsigned long pc = regs->cp0_epc;
  146. if (!task)
  147. task = current;
  148. if (raw_show_trace || user_mode(regs) || !__kernel_text_address(pc)) {
  149. show_raw_backtrace(sp, loglvl, user);
  150. return;
  151. }
  152. printk("%sCall Trace:\n", loglvl);
  153. do {
  154. print_ip_sym(loglvl, pc);
  155. pc = unwind_stack(task, &sp, pc, &ra);
  156. } while (pc);
  157. pr_cont("\n");
  158. }
  159. /*
  160. * This routine abuses get_user()/put_user() to reference pointers
  161. * with at least a bit of error checking ...
  162. */
  163. static void show_stacktrace(struct task_struct *task,
  164. const struct pt_regs *regs, const char *loglvl, bool user)
  165. {
  166. const int field = 2 * sizeof(unsigned long);
  167. unsigned long stackdata;
  168. int i;
  169. unsigned long *sp = (unsigned long *)regs->regs[29];
  170. printk("%sStack :", loglvl);
  171. i = 0;
  172. while ((unsigned long) sp & (PAGE_SIZE - 1)) {
  173. if (i && ((i % (64 / field)) == 0)) {
  174. pr_cont("\n");
  175. printk("%s ", loglvl);
  176. }
  177. if (i > 39) {
  178. pr_cont(" ...");
  179. break;
  180. }
  181. if (__get_addr(&stackdata, sp++, user)) {
  182. pr_cont(" (Bad stack address)");
  183. break;
  184. }
  185. pr_cont(" %0*lx", field, stackdata);
  186. i++;
  187. }
  188. pr_cont("\n");
  189. show_backtrace(task, regs, loglvl, user);
  190. }
  191. void show_stack(struct task_struct *task, unsigned long *sp, const char *loglvl)
  192. {
  193. struct pt_regs regs;
  194. regs.cp0_status = KSU_KERNEL;
  195. if (sp) {
  196. regs.regs[29] = (unsigned long)sp;
  197. regs.regs[31] = 0;
  198. regs.cp0_epc = 0;
  199. } else {
  200. if (task && task != current) {
  201. regs.regs[29] = task->thread.reg29;
  202. regs.regs[31] = 0;
  203. regs.cp0_epc = task->thread.reg31;
  204. } else {
  205. prepare_frametrace(&regs);
  206. }
  207. }
  208. show_stacktrace(task, &regs, loglvl, false);
  209. }
  210. static void show_code(void *pc, bool user)
  211. {
  212. long i;
  213. unsigned short *pc16 = NULL;
  214. printk("Code:");
  215. if ((unsigned long)pc & 1)
  216. pc16 = (u16 *)((unsigned long)pc & ~1);
  217. for(i = -3 ; i < 6 ; i++) {
  218. if (pc16) {
  219. u16 insn16;
  220. if (__get_inst16(&insn16, pc16 + i, user))
  221. goto bad_address;
  222. pr_cont("%c%04x%c", (i?' ':'<'), insn16, (i?' ':'>'));
  223. } else {
  224. u32 insn32;
  225. if (__get_inst32(&insn32, (u32 *)pc + i, user))
  226. goto bad_address;
  227. pr_cont("%c%08x%c", (i?' ':'<'), insn32, (i?' ':'>'));
  228. }
  229. }
  230. pr_cont("\n");
  231. return;
  232. bad_address:
  233. pr_cont(" (Bad address in epc)\n\n");
  234. }
  235. static void __show_regs(const struct pt_regs *regs)
  236. {
  237. const int field = 2 * sizeof(unsigned long);
  238. unsigned int cause = regs->cp0_cause;
  239. unsigned int exccode;
  240. int i;
  241. show_regs_print_info(KERN_DEFAULT);
  242. /*
  243. * Saved main processor registers
  244. */
  245. for (i = 0; i < 32; ) {
  246. if ((i % 4) == 0)
  247. printk("$%2d :", i);
  248. if (i == 0)
  249. pr_cont(" %0*lx", field, 0UL);
  250. else if (i == 26 || i == 27)
  251. pr_cont(" %*s", field, "");
  252. else
  253. pr_cont(" %0*lx", field, regs->regs[i]);
  254. i++;
  255. if ((i % 4) == 0)
  256. pr_cont("\n");
  257. }
  258. #ifdef CONFIG_CPU_HAS_SMARTMIPS
  259. printk("Acx : %0*lx\n", field, regs->acx);
  260. #endif
  261. if (MIPS_ISA_REV < 6) {
  262. printk("Hi : %0*lx\n", field, regs->hi);
  263. printk("Lo : %0*lx\n", field, regs->lo);
  264. }
  265. /*
  266. * Saved cp0 registers
  267. */
  268. printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
  269. (void *) regs->cp0_epc);
  270. printk("ra : %0*lx %pS\n", field, regs->regs[31],
  271. (void *) regs->regs[31]);
  272. printk("Status: %08x ", (uint32_t) regs->cp0_status);
  273. if (cpu_has_3kex) {
  274. if (regs->cp0_status & ST0_KUO)
  275. pr_cont("KUo ");
  276. if (regs->cp0_status & ST0_IEO)
  277. pr_cont("IEo ");
  278. if (regs->cp0_status & ST0_KUP)
  279. pr_cont("KUp ");
  280. if (regs->cp0_status & ST0_IEP)
  281. pr_cont("IEp ");
  282. if (regs->cp0_status & ST0_KUC)
  283. pr_cont("KUc ");
  284. if (regs->cp0_status & ST0_IEC)
  285. pr_cont("IEc ");
  286. } else if (cpu_has_4kex) {
  287. if (regs->cp0_status & ST0_KX)
  288. pr_cont("KX ");
  289. if (regs->cp0_status & ST0_SX)
  290. pr_cont("SX ");
  291. if (regs->cp0_status & ST0_UX)
  292. pr_cont("UX ");
  293. switch (regs->cp0_status & ST0_KSU) {
  294. case KSU_USER:
  295. pr_cont("USER ");
  296. break;
  297. case KSU_SUPERVISOR:
  298. pr_cont("SUPERVISOR ");
  299. break;
  300. case KSU_KERNEL:
  301. pr_cont("KERNEL ");
  302. break;
  303. default:
  304. pr_cont("BAD_MODE ");
  305. break;
  306. }
  307. if (regs->cp0_status & ST0_ERL)
  308. pr_cont("ERL ");
  309. if (regs->cp0_status & ST0_EXL)
  310. pr_cont("EXL ");
  311. if (regs->cp0_status & ST0_IE)
  312. pr_cont("IE ");
  313. }
  314. pr_cont("\n");
  315. exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
  316. printk("Cause : %08x (ExcCode %02x)\n", cause, exccode);
  317. if (1 <= exccode && exccode <= 5)
  318. printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
  319. printk("PrId : %08x (%s)\n", read_c0_prid(),
  320. cpu_name_string());
  321. }
  322. /*
  323. * FIXME: really the generic show_regs should take a const pointer argument.
  324. */
  325. void show_regs(struct pt_regs *regs)
  326. {
  327. __show_regs(regs);
  328. dump_stack();
  329. }
  330. void show_registers(struct pt_regs *regs)
  331. {
  332. const int field = 2 * sizeof(unsigned long);
  333. __show_regs(regs);
  334. print_modules();
  335. printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
  336. current->comm, current->pid, current_thread_info(), current,
  337. field, current_thread_info()->tp_value);
  338. if (cpu_has_userlocal) {
  339. unsigned long tls;
  340. tls = read_c0_userlocal();
  341. if (tls != current_thread_info()->tp_value)
  342. printk("*HwTLS: %0*lx\n", field, tls);
  343. }
  344. show_stacktrace(current, regs, KERN_DEFAULT, user_mode(regs));
  345. show_code((void *)regs->cp0_epc, user_mode(regs));
  346. printk("\n");
  347. }
  348. static DEFINE_RAW_SPINLOCK(die_lock);
  349. void __noreturn die(const char *str, struct pt_regs *regs)
  350. {
  351. static int die_counter;
  352. int sig = SIGSEGV;
  353. oops_enter();
  354. if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_nr,
  355. SIGSEGV) == NOTIFY_STOP)
  356. sig = 0;
  357. console_verbose();
  358. raw_spin_lock_irq(&die_lock);
  359. bust_spinlocks(1);
  360. printk("%s[#%d]:\n", str, ++die_counter);
  361. show_registers(regs);
  362. add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
  363. raw_spin_unlock_irq(&die_lock);
  364. oops_exit();
  365. if (in_interrupt())
  366. panic("Fatal exception in interrupt");
  367. if (panic_on_oops)
  368. panic("Fatal exception");
  369. if (regs && kexec_should_crash(current))
  370. crash_kexec(regs);
  371. make_task_dead(sig);
  372. }
  373. extern struct exception_table_entry __start___dbe_table[];
  374. extern struct exception_table_entry __stop___dbe_table[];
  375. __asm__(
  376. " .section __dbe_table, \"a\"\n"
  377. " .previous \n");
  378. /* Given an address, look for it in the exception tables. */
  379. static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
  380. {
  381. const struct exception_table_entry *e;
  382. e = search_extable(__start___dbe_table,
  383. __stop___dbe_table - __start___dbe_table, addr);
  384. if (!e)
  385. e = search_module_dbetables(addr);
  386. return e;
  387. }
  388. asmlinkage void do_be(struct pt_regs *regs)
  389. {
  390. const int field = 2 * sizeof(unsigned long);
  391. const struct exception_table_entry *fixup = NULL;
  392. int data = regs->cp0_cause & 4;
  393. int action = MIPS_BE_FATAL;
  394. enum ctx_state prev_state;
  395. prev_state = exception_enter();
  396. /* XXX For now. Fixme, this searches the wrong table ... */
  397. if (data && !user_mode(regs))
  398. fixup = search_dbe_tables(exception_epc(regs));
  399. if (fixup)
  400. action = MIPS_BE_FIXUP;
  401. if (board_be_handler)
  402. action = board_be_handler(regs, fixup != NULL);
  403. else
  404. mips_cm_error_report();
  405. switch (action) {
  406. case MIPS_BE_DISCARD:
  407. goto out;
  408. case MIPS_BE_FIXUP:
  409. if (fixup) {
  410. regs->cp0_epc = fixup->nextinsn;
  411. goto out;
  412. }
  413. break;
  414. default:
  415. break;
  416. }
  417. /*
  418. * Assume it would be too dangerous to continue ...
  419. */
  420. printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
  421. data ? "Data" : "Instruction",
  422. field, regs->cp0_epc, field, regs->regs[31]);
  423. if (notify_die(DIE_OOPS, "bus error", regs, 0, current->thread.trap_nr,
  424. SIGBUS) == NOTIFY_STOP)
  425. goto out;
  426. die_if_kernel("Oops", regs);
  427. force_sig(SIGBUS);
  428. out:
  429. exception_exit(prev_state);
  430. }
  431. /*
  432. * ll/sc, rdhwr, sync emulation
  433. */
  434. #define OPCODE 0xfc000000
  435. #define BASE 0x03e00000
  436. #define RT 0x001f0000
  437. #define OFFSET 0x0000ffff
  438. #define LL 0xc0000000
  439. #define SC 0xe0000000
  440. #define SPEC0 0x00000000
  441. #define SPEC3 0x7c000000
  442. #define RD 0x0000f800
  443. #define FUNC 0x0000003f
  444. #define SYNC 0x0000000f
  445. #define RDHWR 0x0000003b
  446. /* microMIPS definitions */
  447. #define MM_POOL32A_FUNC 0xfc00ffff
  448. #define MM_RDHWR 0x00006b3c
  449. #define MM_RS 0x001f0000
  450. #define MM_RT 0x03e00000
  451. /*
  452. * The ll_bit is cleared by r*_switch.S
  453. */
  454. unsigned int ll_bit;
  455. struct task_struct *ll_task;
  456. static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
  457. {
  458. unsigned long value, __user *vaddr;
  459. long offset;
  460. /*
  461. * analyse the ll instruction that just caused a ri exception
  462. * and put the referenced address to addr.
  463. */
  464. /* sign extend offset */
  465. offset = opcode & OFFSET;
  466. offset <<= 16;
  467. offset >>= 16;
  468. vaddr = (unsigned long __user *)
  469. ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
  470. if ((unsigned long)vaddr & 3)
  471. return SIGBUS;
  472. if (get_user(value, vaddr))
  473. return SIGSEGV;
  474. preempt_disable();
  475. if (ll_task == NULL || ll_task == current) {
  476. ll_bit = 1;
  477. } else {
  478. ll_bit = 0;
  479. }
  480. ll_task = current;
  481. preempt_enable();
  482. regs->regs[(opcode & RT) >> 16] = value;
  483. return 0;
  484. }
  485. static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
  486. {
  487. unsigned long __user *vaddr;
  488. unsigned long reg;
  489. long offset;
  490. /*
  491. * analyse the sc instruction that just caused a ri exception
  492. * and put the referenced address to addr.
  493. */
  494. /* sign extend offset */
  495. offset = opcode & OFFSET;
  496. offset <<= 16;
  497. offset >>= 16;
  498. vaddr = (unsigned long __user *)
  499. ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
  500. reg = (opcode & RT) >> 16;
  501. if ((unsigned long)vaddr & 3)
  502. return SIGBUS;
  503. preempt_disable();
  504. if (ll_bit == 0 || ll_task != current) {
  505. regs->regs[reg] = 0;
  506. preempt_enable();
  507. return 0;
  508. }
  509. preempt_enable();
  510. if (put_user(regs->regs[reg], vaddr))
  511. return SIGSEGV;
  512. regs->regs[reg] = 1;
  513. return 0;
  514. }
  515. /*
  516. * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
  517. * opcodes are supposed to result in coprocessor unusable exceptions if
  518. * executed on ll/sc-less processors. That's the theory. In practice a
  519. * few processors such as NEC's VR4100 throw reserved instruction exceptions
  520. * instead, so we're doing the emulation thing in both exception handlers.
  521. */
  522. static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
  523. {
  524. if ((opcode & OPCODE) == LL) {
  525. perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
  526. 1, regs, 0);
  527. return simulate_ll(regs, opcode);
  528. }
  529. if ((opcode & OPCODE) == SC) {
  530. perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
  531. 1, regs, 0);
  532. return simulate_sc(regs, opcode);
  533. }
  534. return -1; /* Must be something else ... */
  535. }
  536. /*
  537. * Simulate trapping 'rdhwr' instructions to provide user accessible
  538. * registers not implemented in hardware.
  539. */
  540. static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
  541. {
  542. struct thread_info *ti = task_thread_info(current);
  543. perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
  544. 1, regs, 0);
  545. switch (rd) {
  546. case MIPS_HWR_CPUNUM: /* CPU number */
  547. regs->regs[rt] = smp_processor_id();
  548. return 0;
  549. case MIPS_HWR_SYNCISTEP: /* SYNCI length */
  550. regs->regs[rt] = min(current_cpu_data.dcache.linesz,
  551. current_cpu_data.icache.linesz);
  552. return 0;
  553. case MIPS_HWR_CC: /* Read count register */
  554. regs->regs[rt] = read_c0_count();
  555. return 0;
  556. case MIPS_HWR_CCRES: /* Count register resolution */
  557. switch (current_cpu_type()) {
  558. case CPU_20KC:
  559. case CPU_25KF:
  560. regs->regs[rt] = 1;
  561. break;
  562. default:
  563. regs->regs[rt] = 2;
  564. }
  565. return 0;
  566. case MIPS_HWR_ULR: /* Read UserLocal register */
  567. regs->regs[rt] = ti->tp_value;
  568. return 0;
  569. default:
  570. return -1;
  571. }
  572. }
  573. static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
  574. {
  575. if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
  576. int rd = (opcode & RD) >> 11;
  577. int rt = (opcode & RT) >> 16;
  578. simulate_rdhwr(regs, rd, rt);
  579. return 0;
  580. }
  581. /* Not ours. */
  582. return -1;
  583. }
  584. static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned int opcode)
  585. {
  586. if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) {
  587. int rd = (opcode & MM_RS) >> 16;
  588. int rt = (opcode & MM_RT) >> 21;
  589. simulate_rdhwr(regs, rd, rt);
  590. return 0;
  591. }
  592. /* Not ours. */
  593. return -1;
  594. }
  595. static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
  596. {
  597. if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
  598. perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
  599. 1, regs, 0);
  600. return 0;
  601. }
  602. return -1; /* Must be something else ... */
  603. }
  604. /*
  605. * Loongson-3 CSR instructions emulation
  606. */
  607. #ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION
  608. #define LWC2 0xc8000000
  609. #define RS BASE
  610. #define CSR_OPCODE2 0x00000118
  611. #define CSR_OPCODE2_MASK 0x000007ff
  612. #define CSR_FUNC_MASK RT
  613. #define CSR_FUNC_CPUCFG 0x8
  614. static int simulate_loongson3_cpucfg(struct pt_regs *regs,
  615. unsigned int opcode)
  616. {
  617. int op = opcode & OPCODE;
  618. int op2 = opcode & CSR_OPCODE2_MASK;
  619. int csr_func = (opcode & CSR_FUNC_MASK) >> 16;
  620. if (op == LWC2 && op2 == CSR_OPCODE2 && csr_func == CSR_FUNC_CPUCFG) {
  621. int rd = (opcode & RD) >> 11;
  622. int rs = (opcode & RS) >> 21;
  623. __u64 sel = regs->regs[rs];
  624. perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
  625. /* Do not emulate on unsupported core models. */
  626. preempt_disable();
  627. if (!loongson3_cpucfg_emulation_enabled(&current_cpu_data)) {
  628. preempt_enable();
  629. return -1;
  630. }
  631. regs->regs[rd] = loongson3_cpucfg_read_synthesized(
  632. &current_cpu_data, sel);
  633. preempt_enable();
  634. return 0;
  635. }
  636. /* Not ours. */
  637. return -1;
  638. }
  639. #endif /* CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION */
  640. asmlinkage void do_ov(struct pt_regs *regs)
  641. {
  642. enum ctx_state prev_state;
  643. prev_state = exception_enter();
  644. die_if_kernel("Integer overflow", regs);
  645. force_sig_fault(SIGFPE, FPE_INTOVF, (void __user *)regs->cp0_epc);
  646. exception_exit(prev_state);
  647. }
  648. #ifdef CONFIG_MIPS_FP_SUPPORT
  649. /*
  650. * Send SIGFPE according to FCSR Cause bits, which must have already
  651. * been masked against Enable bits. This is impotant as Inexact can
  652. * happen together with Overflow or Underflow, and `ptrace' can set
  653. * any bits.
  654. */
  655. void force_fcr31_sig(unsigned long fcr31, void __user *fault_addr,
  656. struct task_struct *tsk)
  657. {
  658. int si_code = FPE_FLTUNK;
  659. if (fcr31 & FPU_CSR_INV_X)
  660. si_code = FPE_FLTINV;
  661. else if (fcr31 & FPU_CSR_DIV_X)
  662. si_code = FPE_FLTDIV;
  663. else if (fcr31 & FPU_CSR_OVF_X)
  664. si_code = FPE_FLTOVF;
  665. else if (fcr31 & FPU_CSR_UDF_X)
  666. si_code = FPE_FLTUND;
  667. else if (fcr31 & FPU_CSR_INE_X)
  668. si_code = FPE_FLTRES;
  669. force_sig_fault_to_task(SIGFPE, si_code, fault_addr, tsk);
  670. }
  671. int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31)
  672. {
  673. int si_code;
  674. switch (sig) {
  675. case 0:
  676. return 0;
  677. case SIGFPE:
  678. force_fcr31_sig(fcr31, fault_addr, current);
  679. return 1;
  680. case SIGBUS:
  681. force_sig_fault(SIGBUS, BUS_ADRERR, fault_addr);
  682. return 1;
  683. case SIGSEGV:
  684. mmap_read_lock(current->mm);
  685. if (vma_lookup(current->mm, (unsigned long)fault_addr))
  686. si_code = SEGV_ACCERR;
  687. else
  688. si_code = SEGV_MAPERR;
  689. mmap_read_unlock(current->mm);
  690. force_sig_fault(SIGSEGV, si_code, fault_addr);
  691. return 1;
  692. default:
  693. force_sig(sig);
  694. return 1;
  695. }
  696. }
  697. static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
  698. unsigned long old_epc, unsigned long old_ra)
  699. {
  700. union mips_instruction inst = { .word = opcode };
  701. void __user *fault_addr;
  702. unsigned long fcr31;
  703. int sig;
  704. /* If it's obviously not an FP instruction, skip it */
  705. switch (inst.i_format.opcode) {
  706. case cop1_op:
  707. case cop1x_op:
  708. case lwc1_op:
  709. case ldc1_op:
  710. case swc1_op:
  711. case sdc1_op:
  712. break;
  713. default:
  714. return -1;
  715. }
  716. /*
  717. * do_ri skipped over the instruction via compute_return_epc, undo
  718. * that for the FPU emulator.
  719. */
  720. regs->cp0_epc = old_epc;
  721. regs->regs[31] = old_ra;
  722. /* Run the emulator */
  723. sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
  724. &fault_addr);
  725. /*
  726. * We can't allow the emulated instruction to leave any
  727. * enabled Cause bits set in $fcr31.
  728. */
  729. fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
  730. current->thread.fpu.fcr31 &= ~fcr31;
  731. /* Restore the hardware register state */
  732. own_fpu(1);
  733. /* Send a signal if required. */
  734. process_fpemu_return(sig, fault_addr, fcr31);
  735. return 0;
  736. }
  737. /*
  738. * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
  739. */
  740. asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
  741. {
  742. enum ctx_state prev_state;
  743. void __user *fault_addr;
  744. int sig;
  745. prev_state = exception_enter();
  746. if (notify_die(DIE_FP, "FP exception", regs, 0, current->thread.trap_nr,
  747. SIGFPE) == NOTIFY_STOP)
  748. goto out;
  749. /* Clear FCSR.Cause before enabling interrupts */
  750. write_32bit_cp1_register(CP1_STATUS, fcr31 & ~mask_fcr31_x(fcr31));
  751. local_irq_enable();
  752. die_if_kernel("FP exception in kernel code", regs);
  753. if (fcr31 & FPU_CSR_UNI_X) {
  754. /*
  755. * Unimplemented operation exception. If we've got the full
  756. * software emulator on-board, let's use it...
  757. *
  758. * Force FPU to dump state into task/thread context. We're
  759. * moving a lot of data here for what is probably a single
  760. * instruction, but the alternative is to pre-decode the FP
  761. * register operands before invoking the emulator, which seems
  762. * a bit extreme for what should be an infrequent event.
  763. */
  764. /* Run the emulator */
  765. sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
  766. &fault_addr);
  767. /*
  768. * We can't allow the emulated instruction to leave any
  769. * enabled Cause bits set in $fcr31.
  770. */
  771. fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
  772. current->thread.fpu.fcr31 &= ~fcr31;
  773. /* Restore the hardware register state */
  774. own_fpu(1); /* Using the FPU again. */
  775. } else {
  776. sig = SIGFPE;
  777. fault_addr = (void __user *) regs->cp0_epc;
  778. }
  779. /* Send a signal if required. */
  780. process_fpemu_return(sig, fault_addr, fcr31);
  781. out:
  782. exception_exit(prev_state);
  783. }
  784. /*
  785. * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
  786. * emulated more than some threshold number of instructions, force migration to
  787. * a "CPU" that has FP support.
  788. */
  789. static void mt_ase_fp_affinity(void)
  790. {
  791. #ifdef CONFIG_MIPS_MT_FPAFF
  792. if (mt_fpemul_threshold > 0 &&
  793. ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
  794. /*
  795. * If there's no FPU present, or if the application has already
  796. * restricted the allowed set to exclude any CPUs with FPUs,
  797. * we'll skip the procedure.
  798. */
  799. if (cpumask_intersects(&current->cpus_mask, &mt_fpu_cpumask)) {
  800. cpumask_t tmask;
  801. current->thread.user_cpus_allowed
  802. = current->cpus_mask;
  803. cpumask_and(&tmask, &current->cpus_mask,
  804. &mt_fpu_cpumask);
  805. set_cpus_allowed_ptr(current, &tmask);
  806. set_thread_flag(TIF_FPUBOUND);
  807. }
  808. }
  809. #endif /* CONFIG_MIPS_MT_FPAFF */
  810. }
  811. #else /* !CONFIG_MIPS_FP_SUPPORT */
  812. static int simulate_fp(struct pt_regs *regs, unsigned int opcode,
  813. unsigned long old_epc, unsigned long old_ra)
  814. {
  815. return -1;
  816. }
  817. #endif /* !CONFIG_MIPS_FP_SUPPORT */
  818. void do_trap_or_bp(struct pt_regs *regs, unsigned int code, int si_code,
  819. const char *str)
  820. {
  821. char b[40];
  822. #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
  823. if (kgdb_ll_trap(DIE_TRAP, str, regs, code, current->thread.trap_nr,
  824. SIGTRAP) == NOTIFY_STOP)
  825. return;
  826. #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
  827. if (notify_die(DIE_TRAP, str, regs, code, current->thread.trap_nr,
  828. SIGTRAP) == NOTIFY_STOP)
  829. return;
  830. /*
  831. * A short test says that IRIX 5.3 sends SIGTRAP for all trap
  832. * insns, even for trap and break codes that indicate arithmetic
  833. * failures. Weird ...
  834. * But should we continue the brokenness??? --macro
  835. */
  836. switch (code) {
  837. case BRK_OVERFLOW:
  838. case BRK_DIVZERO:
  839. scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
  840. die_if_kernel(b, regs);
  841. force_sig_fault(SIGFPE,
  842. code == BRK_DIVZERO ? FPE_INTDIV : FPE_INTOVF,
  843. (void __user *) regs->cp0_epc);
  844. break;
  845. case BRK_BUG:
  846. die_if_kernel("Kernel bug detected", regs);
  847. force_sig(SIGTRAP);
  848. break;
  849. case BRK_MEMU:
  850. /*
  851. * This breakpoint code is used by the FPU emulator to retake
  852. * control of the CPU after executing the instruction from the
  853. * delay slot of an emulated branch.
  854. *
  855. * Terminate if exception was recognized as a delay slot return
  856. * otherwise handle as normal.
  857. */
  858. if (do_dsemulret(regs))
  859. return;
  860. die_if_kernel("Math emu break/trap", regs);
  861. force_sig(SIGTRAP);
  862. break;
  863. default:
  864. scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
  865. die_if_kernel(b, regs);
  866. if (si_code) {
  867. force_sig_fault(SIGTRAP, si_code, NULL);
  868. } else {
  869. force_sig(SIGTRAP);
  870. }
  871. }
  872. }
  873. asmlinkage void do_bp(struct pt_regs *regs)
  874. {
  875. unsigned long epc = msk_isa16_mode(exception_epc(regs));
  876. unsigned int opcode, bcode;
  877. enum ctx_state prev_state;
  878. bool user = user_mode(regs);
  879. prev_state = exception_enter();
  880. current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
  881. if (get_isa16_mode(regs->cp0_epc)) {
  882. u16 instr[2];
  883. if (__get_inst16(&instr[0], (u16 *)epc, user))
  884. goto out_sigsegv;
  885. if (!cpu_has_mmips) {
  886. /* MIPS16e mode */
  887. bcode = (instr[0] >> 5) & 0x3f;
  888. } else if (mm_insn_16bit(instr[0])) {
  889. /* 16-bit microMIPS BREAK */
  890. bcode = instr[0] & 0xf;
  891. } else {
  892. /* 32-bit microMIPS BREAK */
  893. if (__get_inst16(&instr[1], (u16 *)(epc + 2), user))
  894. goto out_sigsegv;
  895. opcode = (instr[0] << 16) | instr[1];
  896. bcode = (opcode >> 6) & ((1 << 20) - 1);
  897. }
  898. } else {
  899. if (__get_inst32(&opcode, (u32 *)epc, user))
  900. goto out_sigsegv;
  901. bcode = (opcode >> 6) & ((1 << 20) - 1);
  902. }
  903. /*
  904. * There is the ancient bug in the MIPS assemblers that the break
  905. * code starts left to bit 16 instead to bit 6 in the opcode.
  906. * Gas is bug-compatible, but not always, grrr...
  907. * We handle both cases with a simple heuristics. --macro
  908. */
  909. if (bcode >= (1 << 10))
  910. bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10);
  911. /*
  912. * notify the kprobe handlers, if instruction is likely to
  913. * pertain to them.
  914. */
  915. switch (bcode) {
  916. case BRK_UPROBE:
  917. if (notify_die(DIE_UPROBE, "uprobe", regs, bcode,
  918. current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
  919. goto out;
  920. else
  921. break;
  922. case BRK_UPROBE_XOL:
  923. if (notify_die(DIE_UPROBE_XOL, "uprobe_xol", regs, bcode,
  924. current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
  925. goto out;
  926. else
  927. break;
  928. case BRK_KPROBE_BP:
  929. if (notify_die(DIE_BREAK, "debug", regs, bcode,
  930. current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
  931. goto out;
  932. else
  933. break;
  934. case BRK_KPROBE_SSTEPBP:
  935. if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode,
  936. current->thread.trap_nr, SIGTRAP) == NOTIFY_STOP)
  937. goto out;
  938. else
  939. break;
  940. default:
  941. break;
  942. }
  943. do_trap_or_bp(regs, bcode, TRAP_BRKPT, "Break");
  944. out:
  945. exception_exit(prev_state);
  946. return;
  947. out_sigsegv:
  948. force_sig(SIGSEGV);
  949. goto out;
  950. }
  951. asmlinkage void do_tr(struct pt_regs *regs)
  952. {
  953. u32 opcode, tcode = 0;
  954. enum ctx_state prev_state;
  955. u16 instr[2];
  956. bool user = user_mode(regs);
  957. unsigned long epc = msk_isa16_mode(exception_epc(regs));
  958. prev_state = exception_enter();
  959. current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
  960. if (get_isa16_mode(regs->cp0_epc)) {
  961. if (__get_inst16(&instr[0], (u16 *)(epc + 0), user) ||
  962. __get_inst16(&instr[1], (u16 *)(epc + 2), user))
  963. goto out_sigsegv;
  964. opcode = (instr[0] << 16) | instr[1];
  965. /* Immediate versions don't provide a code. */
  966. if (!(opcode & OPCODE))
  967. tcode = (opcode >> 12) & ((1 << 4) - 1);
  968. } else {
  969. if (__get_inst32(&opcode, (u32 *)epc, user))
  970. goto out_sigsegv;
  971. /* Immediate versions don't provide a code. */
  972. if (!(opcode & OPCODE))
  973. tcode = (opcode >> 6) & ((1 << 10) - 1);
  974. }
  975. do_trap_or_bp(regs, tcode, 0, "Trap");
  976. out:
  977. exception_exit(prev_state);
  978. return;
  979. out_sigsegv:
  980. force_sig(SIGSEGV);
  981. goto out;
  982. }
  983. asmlinkage void do_ri(struct pt_regs *regs)
  984. {
  985. unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
  986. unsigned long old_epc = regs->cp0_epc;
  987. unsigned long old31 = regs->regs[31];
  988. enum ctx_state prev_state;
  989. unsigned int opcode = 0;
  990. int status = -1;
  991. /*
  992. * Avoid any kernel code. Just emulate the R2 instruction
  993. * as quickly as possible.
  994. */
  995. if (mipsr2_emulation && cpu_has_mips_r6 &&
  996. likely(user_mode(regs)) &&
  997. likely(get_user(opcode, epc) >= 0)) {
  998. unsigned long fcr31 = 0;
  999. status = mipsr2_decoder(regs, opcode, &fcr31);
  1000. switch (status) {
  1001. case 0:
  1002. case SIGEMT:
  1003. return;
  1004. case SIGILL:
  1005. goto no_r2_instr;
  1006. default:
  1007. process_fpemu_return(status,
  1008. &current->thread.cp0_baduaddr,
  1009. fcr31);
  1010. return;
  1011. }
  1012. }
  1013. no_r2_instr:
  1014. prev_state = exception_enter();
  1015. current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
  1016. if (notify_die(DIE_RI, "RI Fault", regs, 0, current->thread.trap_nr,
  1017. SIGILL) == NOTIFY_STOP)
  1018. goto out;
  1019. die_if_kernel("Reserved instruction in kernel code", regs);
  1020. if (unlikely(compute_return_epc(regs) < 0))
  1021. goto out;
  1022. if (!get_isa16_mode(regs->cp0_epc)) {
  1023. if (unlikely(get_user(opcode, epc) < 0))
  1024. status = SIGSEGV;
  1025. if (!cpu_has_llsc && status < 0)
  1026. status = simulate_llsc(regs, opcode);
  1027. if (status < 0)
  1028. status = simulate_rdhwr_normal(regs, opcode);
  1029. if (status < 0)
  1030. status = simulate_sync(regs, opcode);
  1031. if (status < 0)
  1032. status = simulate_fp(regs, opcode, old_epc, old31);
  1033. #ifdef CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION
  1034. if (status < 0)
  1035. status = simulate_loongson3_cpucfg(regs, opcode);
  1036. #endif
  1037. } else if (cpu_has_mmips) {
  1038. unsigned short mmop[2] = { 0 };
  1039. if (unlikely(get_user(mmop[0], (u16 __user *)epc + 0) < 0))
  1040. status = SIGSEGV;
  1041. if (unlikely(get_user(mmop[1], (u16 __user *)epc + 1) < 0))
  1042. status = SIGSEGV;
  1043. opcode = mmop[0];
  1044. opcode = (opcode << 16) | mmop[1];
  1045. if (status < 0)
  1046. status = simulate_rdhwr_mm(regs, opcode);
  1047. }
  1048. if (status < 0)
  1049. status = SIGILL;
  1050. if (unlikely(status > 0)) {
  1051. regs->cp0_epc = old_epc; /* Undo skip-over. */
  1052. regs->regs[31] = old31;
  1053. force_sig(status);
  1054. }
  1055. out:
  1056. exception_exit(prev_state);
  1057. }
  1058. /*
  1059. * No lock; only written during early bootup by CPU 0.
  1060. */
  1061. static RAW_NOTIFIER_HEAD(cu2_chain);
  1062. int __ref register_cu2_notifier(struct notifier_block *nb)
  1063. {
  1064. return raw_notifier_chain_register(&cu2_chain, nb);
  1065. }
  1066. int cu2_notifier_call_chain(unsigned long val, void *v)
  1067. {
  1068. return raw_notifier_call_chain(&cu2_chain, val, v);
  1069. }
  1070. static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
  1071. void *data)
  1072. {
  1073. struct pt_regs *regs = data;
  1074. die_if_kernel("COP2: Unhandled kernel unaligned access or invalid "
  1075. "instruction", regs);
  1076. force_sig(SIGILL);
  1077. return NOTIFY_OK;
  1078. }
  1079. #ifdef CONFIG_MIPS_FP_SUPPORT
  1080. static int enable_restore_fp_context(int msa)
  1081. {
  1082. int err, was_fpu_owner, prior_msa;
  1083. bool first_fp;
  1084. /* Initialize context if it hasn't been used already */
  1085. first_fp = init_fp_ctx(current);
  1086. if (first_fp) {
  1087. preempt_disable();
  1088. err = own_fpu_inatomic(1);
  1089. if (msa && !err) {
  1090. enable_msa();
  1091. /*
  1092. * with MSA enabled, userspace can see MSACSR
  1093. * and MSA regs, but the values in them are from
  1094. * other task before current task, restore them
  1095. * from saved fp/msa context
  1096. */
  1097. write_msa_csr(current->thread.fpu.msacsr);
  1098. /*
  1099. * own_fpu_inatomic(1) just restore low 64bit,
  1100. * fix the high 64bit
  1101. */
  1102. init_msa_upper();
  1103. set_thread_flag(TIF_USEDMSA);
  1104. set_thread_flag(TIF_MSA_CTX_LIVE);
  1105. }
  1106. preempt_enable();
  1107. return err;
  1108. }
  1109. /*
  1110. * This task has formerly used the FP context.
  1111. *
  1112. * If this thread has no live MSA vector context then we can simply
  1113. * restore the scalar FP context. If it has live MSA vector context
  1114. * (that is, it has or may have used MSA since last performing a
  1115. * function call) then we'll need to restore the vector context. This
  1116. * applies even if we're currently only executing a scalar FP
  1117. * instruction. This is because if we were to later execute an MSA
  1118. * instruction then we'd either have to:
  1119. *
  1120. * - Restore the vector context & clobber any registers modified by
  1121. * scalar FP instructions between now & then.
  1122. *
  1123. * or
  1124. *
  1125. * - Not restore the vector context & lose the most significant bits
  1126. * of all vector registers.
  1127. *
  1128. * Neither of those options is acceptable. We cannot restore the least
  1129. * significant bits of the registers now & only restore the most
  1130. * significant bits later because the most significant bits of any
  1131. * vector registers whose aliased FP register is modified now will have
  1132. * been zeroed. We'd have no way to know that when restoring the vector
  1133. * context & thus may load an outdated value for the most significant
  1134. * bits of a vector register.
  1135. */
  1136. if (!msa && !thread_msa_context_live())
  1137. return own_fpu(1);
  1138. /*
  1139. * This task is using or has previously used MSA. Thus we require
  1140. * that Status.FR == 1.
  1141. */
  1142. preempt_disable();
  1143. was_fpu_owner = is_fpu_owner();
  1144. err = own_fpu_inatomic(0);
  1145. if (err)
  1146. goto out;
  1147. enable_msa();
  1148. write_msa_csr(current->thread.fpu.msacsr);
  1149. set_thread_flag(TIF_USEDMSA);
  1150. /*
  1151. * If this is the first time that the task is using MSA and it has
  1152. * previously used scalar FP in this time slice then we already nave
  1153. * FP context which we shouldn't clobber. We do however need to clear
  1154. * the upper 64b of each vector register so that this task has no
  1155. * opportunity to see data left behind by another.
  1156. */
  1157. prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE);
  1158. if (!prior_msa && was_fpu_owner) {
  1159. init_msa_upper();
  1160. goto out;
  1161. }
  1162. if (!prior_msa) {
  1163. /*
  1164. * Restore the least significant 64b of each vector register
  1165. * from the existing scalar FP context.
  1166. */
  1167. _restore_fp(current);
  1168. /*
  1169. * The task has not formerly used MSA, so clear the upper 64b
  1170. * of each vector register such that it cannot see data left
  1171. * behind by another task.
  1172. */
  1173. init_msa_upper();
  1174. } else {
  1175. /* We need to restore the vector context. */
  1176. restore_msa(current);
  1177. /* Restore the scalar FP control & status register */
  1178. if (!was_fpu_owner)
  1179. write_32bit_cp1_register(CP1_STATUS,
  1180. current->thread.fpu.fcr31);
  1181. }
  1182. out:
  1183. preempt_enable();
  1184. return 0;
  1185. }
  1186. #else /* !CONFIG_MIPS_FP_SUPPORT */
  1187. static int enable_restore_fp_context(int msa)
  1188. {
  1189. return SIGILL;
  1190. }
  1191. #endif /* CONFIG_MIPS_FP_SUPPORT */
  1192. asmlinkage void do_cpu(struct pt_regs *regs)
  1193. {
  1194. enum ctx_state prev_state;
  1195. unsigned int __user *epc;
  1196. unsigned long old_epc, old31;
  1197. unsigned int opcode;
  1198. unsigned int cpid;
  1199. int status;
  1200. prev_state = exception_enter();
  1201. cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
  1202. if (cpid != 2)
  1203. die_if_kernel("do_cpu invoked from kernel context!", regs);
  1204. switch (cpid) {
  1205. case 0:
  1206. epc = (unsigned int __user *)exception_epc(regs);
  1207. old_epc = regs->cp0_epc;
  1208. old31 = regs->regs[31];
  1209. opcode = 0;
  1210. status = -1;
  1211. if (unlikely(compute_return_epc(regs) < 0))
  1212. break;
  1213. if (!get_isa16_mode(regs->cp0_epc)) {
  1214. if (unlikely(get_user(opcode, epc) < 0))
  1215. status = SIGSEGV;
  1216. if (!cpu_has_llsc && status < 0)
  1217. status = simulate_llsc(regs, opcode);
  1218. }
  1219. if (status < 0)
  1220. status = SIGILL;
  1221. if (unlikely(status > 0)) {
  1222. regs->cp0_epc = old_epc; /* Undo skip-over. */
  1223. regs->regs[31] = old31;
  1224. force_sig(status);
  1225. }
  1226. break;
  1227. #ifdef CONFIG_MIPS_FP_SUPPORT
  1228. case 3:
  1229. /*
  1230. * The COP3 opcode space and consequently the CP0.Status.CU3
  1231. * bit and the CP0.Cause.CE=3 encoding have been removed as
  1232. * of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs
  1233. * up the space has been reused for COP1X instructions, that
  1234. * are enabled by the CP0.Status.CU1 bit and consequently
  1235. * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable
  1236. * exceptions. Some FPU-less processors that implement one
  1237. * of these ISAs however use this code erroneously for COP1X
  1238. * instructions. Therefore we redirect this trap to the FP
  1239. * emulator too.
  1240. */
  1241. if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) {
  1242. force_sig(SIGILL);
  1243. break;
  1244. }
  1245. fallthrough;
  1246. case 1: {
  1247. void __user *fault_addr;
  1248. unsigned long fcr31;
  1249. int err, sig;
  1250. err = enable_restore_fp_context(0);
  1251. if (raw_cpu_has_fpu && !err)
  1252. break;
  1253. sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 0,
  1254. &fault_addr);
  1255. /*
  1256. * We can't allow the emulated instruction to leave
  1257. * any enabled Cause bits set in $fcr31.
  1258. */
  1259. fcr31 = mask_fcr31_x(current->thread.fpu.fcr31);
  1260. current->thread.fpu.fcr31 &= ~fcr31;
  1261. /* Send a signal if required. */
  1262. if (!process_fpemu_return(sig, fault_addr, fcr31) && !err)
  1263. mt_ase_fp_affinity();
  1264. break;
  1265. }
  1266. #else /* CONFIG_MIPS_FP_SUPPORT */
  1267. case 1:
  1268. case 3:
  1269. force_sig(SIGILL);
  1270. break;
  1271. #endif /* CONFIG_MIPS_FP_SUPPORT */
  1272. case 2:
  1273. raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
  1274. break;
  1275. }
  1276. exception_exit(prev_state);
  1277. }
  1278. asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr)
  1279. {
  1280. enum ctx_state prev_state;
  1281. prev_state = exception_enter();
  1282. current->thread.trap_nr = (regs->cp0_cause >> 2) & 0x1f;
  1283. if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0,
  1284. current->thread.trap_nr, SIGFPE) == NOTIFY_STOP)
  1285. goto out;
  1286. /* Clear MSACSR.Cause before enabling interrupts */
  1287. write_msa_csr(msacsr & ~MSA_CSR_CAUSEF);
  1288. local_irq_enable();
  1289. die_if_kernel("do_msa_fpe invoked from kernel context!", regs);
  1290. force_sig(SIGFPE);
  1291. out:
  1292. exception_exit(prev_state);
  1293. }
  1294. asmlinkage void do_msa(struct pt_regs *regs)
  1295. {
  1296. enum ctx_state prev_state;
  1297. int err;
  1298. prev_state = exception_enter();
  1299. if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) {
  1300. force_sig(SIGILL);
  1301. goto out;
  1302. }
  1303. die_if_kernel("do_msa invoked from kernel context!", regs);
  1304. err = enable_restore_fp_context(1);
  1305. if (err)
  1306. force_sig(SIGILL);
  1307. out:
  1308. exception_exit(prev_state);
  1309. }
  1310. asmlinkage void do_mdmx(struct pt_regs *regs)
  1311. {
  1312. enum ctx_state prev_state;
  1313. prev_state = exception_enter();
  1314. force_sig(SIGILL);
  1315. exception_exit(prev_state);
  1316. }
  1317. /*
  1318. * Called with interrupts disabled.
  1319. */
  1320. asmlinkage void do_watch(struct pt_regs *regs)
  1321. {
  1322. enum ctx_state prev_state;
  1323. prev_state = exception_enter();
  1324. /*
  1325. * Clear WP (bit 22) bit of cause register so we don't loop
  1326. * forever.
  1327. */
  1328. clear_c0_cause(CAUSEF_WP);
  1329. /*
  1330. * If the current thread has the watch registers loaded, save
  1331. * their values and send SIGTRAP. Otherwise another thread
  1332. * left the registers set, clear them and continue.
  1333. */
  1334. if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
  1335. mips_read_watch_registers();
  1336. local_irq_enable();
  1337. force_sig_fault(SIGTRAP, TRAP_HWBKPT, NULL);
  1338. } else {
  1339. mips_clear_watch_registers();
  1340. local_irq_enable();
  1341. }
  1342. exception_exit(prev_state);
  1343. }
  1344. asmlinkage void do_mcheck(struct pt_regs *regs)
  1345. {
  1346. int multi_match = regs->cp0_status & ST0_TS;
  1347. enum ctx_state prev_state;
  1348. prev_state = exception_enter();
  1349. show_regs(regs);
  1350. if (multi_match) {
  1351. dump_tlb_regs();
  1352. pr_info("\n");
  1353. dump_tlb_all();
  1354. }
  1355. show_code((void *)regs->cp0_epc, user_mode(regs));
  1356. /*
  1357. * Some chips may have other causes of machine check (e.g. SB1
  1358. * graduation timer)
  1359. */
  1360. panic("Caught Machine Check exception - %scaused by multiple "
  1361. "matching entries in the TLB.",
  1362. (multi_match) ? "" : "not ");
  1363. }
  1364. asmlinkage void do_mt(struct pt_regs *regs)
  1365. {
  1366. int subcode;
  1367. subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
  1368. >> VPECONTROL_EXCPT_SHIFT;
  1369. switch (subcode) {
  1370. case 0:
  1371. printk(KERN_DEBUG "Thread Underflow\n");
  1372. break;
  1373. case 1:
  1374. printk(KERN_DEBUG "Thread Overflow\n");
  1375. break;
  1376. case 2:
  1377. printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
  1378. break;
  1379. case 3:
  1380. printk(KERN_DEBUG "Gating Storage Exception\n");
  1381. break;
  1382. case 4:
  1383. printk(KERN_DEBUG "YIELD Scheduler Exception\n");
  1384. break;
  1385. case 5:
  1386. printk(KERN_DEBUG "Gating Storage Scheduler Exception\n");
  1387. break;
  1388. default:
  1389. printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
  1390. subcode);
  1391. break;
  1392. }
  1393. die_if_kernel("MIPS MT Thread exception in kernel", regs);
  1394. force_sig(SIGILL);
  1395. }
  1396. asmlinkage void do_dsp(struct pt_regs *regs)
  1397. {
  1398. if (cpu_has_dsp)
  1399. panic("Unexpected DSP exception");
  1400. force_sig(SIGILL);
  1401. }
  1402. asmlinkage void do_reserved(struct pt_regs *regs)
  1403. {
  1404. /*
  1405. * Game over - no way to handle this if it ever occurs. Most probably
  1406. * caused by a new unknown cpu type or after another deadly
  1407. * hard/software error.
  1408. */
  1409. show_regs(regs);
  1410. panic("Caught reserved exception %ld - should not happen.",
  1411. (regs->cp0_cause & 0x7f) >> 2);
  1412. }
  1413. static int __initdata l1parity = 1;
  1414. static int __init nol1parity(char *s)
  1415. {
  1416. l1parity = 0;
  1417. return 1;
  1418. }
  1419. __setup("nol1par", nol1parity);
  1420. static int __initdata l2parity = 1;
  1421. static int __init nol2parity(char *s)
  1422. {
  1423. l2parity = 0;
  1424. return 1;
  1425. }
  1426. __setup("nol2par", nol2parity);
  1427. /*
  1428. * Some MIPS CPUs can enable/disable for cache parity detection, but do
  1429. * it different ways.
  1430. */
  1431. static inline __init void parity_protection_init(void)
  1432. {
  1433. #define ERRCTL_PE 0x80000000
  1434. #define ERRCTL_L2P 0x00800000
  1435. if (mips_cm_revision() >= CM_REV_CM3) {
  1436. ulong gcr_ectl, cp0_ectl;
  1437. /*
  1438. * With CM3 systems we need to ensure that the L1 & L2
  1439. * parity enables are set to the same value, since this
  1440. * is presumed by the hardware engineers.
  1441. *
  1442. * If the user disabled either of L1 or L2 ECC checking,
  1443. * disable both.
  1444. */
  1445. l1parity &= l2parity;
  1446. l2parity &= l1parity;
  1447. /* Probe L1 ECC support */
  1448. cp0_ectl = read_c0_ecc();
  1449. write_c0_ecc(cp0_ectl | ERRCTL_PE);
  1450. back_to_back_c0_hazard();
  1451. cp0_ectl = read_c0_ecc();
  1452. /* Probe L2 ECC support */
  1453. gcr_ectl = read_gcr_err_control();
  1454. if (!(gcr_ectl & CM_GCR_ERR_CONTROL_L2_ECC_SUPPORT) ||
  1455. !(cp0_ectl & ERRCTL_PE)) {
  1456. /*
  1457. * One of L1 or L2 ECC checking isn't supported,
  1458. * so we cannot enable either.
  1459. */
  1460. l1parity = l2parity = 0;
  1461. }
  1462. /* Configure L1 ECC checking */
  1463. if (l1parity)
  1464. cp0_ectl |= ERRCTL_PE;
  1465. else
  1466. cp0_ectl &= ~ERRCTL_PE;
  1467. write_c0_ecc(cp0_ectl);
  1468. back_to_back_c0_hazard();
  1469. WARN_ON(!!(read_c0_ecc() & ERRCTL_PE) != l1parity);
  1470. /* Configure L2 ECC checking */
  1471. if (l2parity)
  1472. gcr_ectl |= CM_GCR_ERR_CONTROL_L2_ECC_EN;
  1473. else
  1474. gcr_ectl &= ~CM_GCR_ERR_CONTROL_L2_ECC_EN;
  1475. write_gcr_err_control(gcr_ectl);
  1476. gcr_ectl = read_gcr_err_control();
  1477. gcr_ectl &= CM_GCR_ERR_CONTROL_L2_ECC_EN;
  1478. WARN_ON(!!gcr_ectl != l2parity);
  1479. pr_info("Cache parity protection %sabled\n",
  1480. l1parity ? "en" : "dis");
  1481. return;
  1482. }
  1483. switch (current_cpu_type()) {
  1484. case CPU_24K:
  1485. case CPU_34K:
  1486. case CPU_74K:
  1487. case CPU_1004K:
  1488. case CPU_1074K:
  1489. case CPU_INTERAPTIV:
  1490. case CPU_PROAPTIV:
  1491. case CPU_P5600:
  1492. case CPU_QEMU_GENERIC:
  1493. case CPU_P6600:
  1494. {
  1495. unsigned long errctl;
  1496. unsigned int l1parity_present, l2parity_present;
  1497. errctl = read_c0_ecc();
  1498. errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
  1499. /* probe L1 parity support */
  1500. write_c0_ecc(errctl | ERRCTL_PE);
  1501. back_to_back_c0_hazard();
  1502. l1parity_present = (read_c0_ecc() & ERRCTL_PE);
  1503. /* probe L2 parity support */
  1504. write_c0_ecc(errctl|ERRCTL_L2P);
  1505. back_to_back_c0_hazard();
  1506. l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
  1507. if (l1parity_present && l2parity_present) {
  1508. if (l1parity)
  1509. errctl |= ERRCTL_PE;
  1510. if (l1parity ^ l2parity)
  1511. errctl |= ERRCTL_L2P;
  1512. } else if (l1parity_present) {
  1513. if (l1parity)
  1514. errctl |= ERRCTL_PE;
  1515. } else if (l2parity_present) {
  1516. if (l2parity)
  1517. errctl |= ERRCTL_L2P;
  1518. } else {
  1519. /* No parity available */
  1520. }
  1521. printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
  1522. write_c0_ecc(errctl);
  1523. back_to_back_c0_hazard();
  1524. errctl = read_c0_ecc();
  1525. printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
  1526. if (l1parity_present)
  1527. printk(KERN_INFO "Cache parity protection %sabled\n",
  1528. (errctl & ERRCTL_PE) ? "en" : "dis");
  1529. if (l2parity_present) {
  1530. if (l1parity_present && l1parity)
  1531. errctl ^= ERRCTL_L2P;
  1532. printk(KERN_INFO "L2 cache parity protection %sabled\n",
  1533. (errctl & ERRCTL_L2P) ? "en" : "dis");
  1534. }
  1535. }
  1536. break;
  1537. case CPU_5KC:
  1538. case CPU_5KE:
  1539. case CPU_LOONGSON32:
  1540. write_c0_ecc(0x80000000);
  1541. back_to_back_c0_hazard();
  1542. /* Set the PE bit (bit 31) in the c0_errctl register. */
  1543. printk(KERN_INFO "Cache parity protection %sabled\n",
  1544. (read_c0_ecc() & 0x80000000) ? "en" : "dis");
  1545. break;
  1546. case CPU_20KC:
  1547. case CPU_25KF:
  1548. /* Clear the DE bit (bit 16) in the c0_status register. */
  1549. printk(KERN_INFO "Enable cache parity protection for "
  1550. "MIPS 20KC/25KF CPUs.\n");
  1551. clear_c0_status(ST0_DE);
  1552. break;
  1553. default:
  1554. break;
  1555. }
  1556. }
  1557. asmlinkage void cache_parity_error(void)
  1558. {
  1559. const int field = 2 * sizeof(unsigned long);
  1560. unsigned int reg_val;
  1561. /* For the moment, report the problem and hang. */
  1562. printk("Cache error exception:\n");
  1563. printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
  1564. reg_val = read_c0_cacheerr();
  1565. printk("c0_cacheerr == %08x\n", reg_val);
  1566. printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
  1567. reg_val & (1<<30) ? "secondary" : "primary",
  1568. reg_val & (1<<31) ? "data" : "insn");
  1569. if ((cpu_has_mips_r2_r6) &&
  1570. ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) {
  1571. pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
  1572. reg_val & (1<<29) ? "ED " : "",
  1573. reg_val & (1<<28) ? "ET " : "",
  1574. reg_val & (1<<27) ? "ES " : "",
  1575. reg_val & (1<<26) ? "EE " : "",
  1576. reg_val & (1<<25) ? "EB " : "",
  1577. reg_val & (1<<24) ? "EI " : "",
  1578. reg_val & (1<<23) ? "E1 " : "",
  1579. reg_val & (1<<22) ? "E0 " : "");
  1580. } else {
  1581. pr_err("Error bits: %s%s%s%s%s%s%s\n",
  1582. reg_val & (1<<29) ? "ED " : "",
  1583. reg_val & (1<<28) ? "ET " : "",
  1584. reg_val & (1<<26) ? "EE " : "",
  1585. reg_val & (1<<25) ? "EB " : "",
  1586. reg_val & (1<<24) ? "EI " : "",
  1587. reg_val & (1<<23) ? "E1 " : "",
  1588. reg_val & (1<<22) ? "E0 " : "");
  1589. }
  1590. printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
  1591. #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
  1592. if (reg_val & (1<<22))
  1593. printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
  1594. if (reg_val & (1<<23))
  1595. printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
  1596. #endif
  1597. panic("Can't handle the cache error!");
  1598. }
  1599. asmlinkage void do_ftlb(void)
  1600. {
  1601. const int field = 2 * sizeof(unsigned long);
  1602. unsigned int reg_val;
  1603. /* For the moment, report the problem and hang. */
  1604. if ((cpu_has_mips_r2_r6) &&
  1605. (((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS) ||
  1606. ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON))) {
  1607. pr_err("FTLB error exception, cp0_ecc=0x%08x:\n",
  1608. read_c0_ecc());
  1609. pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
  1610. reg_val = read_c0_cacheerr();
  1611. pr_err("c0_cacheerr == %08x\n", reg_val);
  1612. if ((reg_val & 0xc0000000) == 0xc0000000) {
  1613. pr_err("Decoded c0_cacheerr: FTLB parity error\n");
  1614. } else {
  1615. pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
  1616. reg_val & (1<<30) ? "secondary" : "primary",
  1617. reg_val & (1<<31) ? "data" : "insn");
  1618. }
  1619. } else {
  1620. pr_err("FTLB error exception\n");
  1621. }
  1622. /* Just print the cacheerr bits for now */
  1623. cache_parity_error();
  1624. }
  1625. asmlinkage void do_gsexc(struct pt_regs *regs, u32 diag1)
  1626. {
  1627. u32 exccode = (diag1 & LOONGSON_DIAG1_EXCCODE) >>
  1628. LOONGSON_DIAG1_EXCCODE_SHIFT;
  1629. enum ctx_state prev_state;
  1630. prev_state = exception_enter();
  1631. switch (exccode) {
  1632. case 0x08:
  1633. /* Undocumented exception, will trigger on certain
  1634. * also-undocumented instructions accessible from userspace.
  1635. * Processor state is not otherwise corrupted, but currently
  1636. * we don't know how to proceed. Maybe there is some
  1637. * undocumented control flag to enable the instructions?
  1638. */
  1639. force_sig(SIGILL);
  1640. break;
  1641. default:
  1642. /* None of the other exceptions, documented or not, have
  1643. * further details given; none are encountered in the wild
  1644. * either. Panic in case some of them turn out to be fatal.
  1645. */
  1646. show_regs(regs);
  1647. panic("Unhandled Loongson exception - GSCause = %08x", diag1);
  1648. }
  1649. exception_exit(prev_state);
  1650. }
  1651. /*
  1652. * SDBBP EJTAG debug exception handler.
  1653. * We skip the instruction and return to the next instruction.
  1654. */
  1655. void ejtag_exception_handler(struct pt_regs *regs)
  1656. {
  1657. const int field = 2 * sizeof(unsigned long);
  1658. unsigned long depc, old_epc, old_ra;
  1659. unsigned int debug;
  1660. printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
  1661. depc = read_c0_depc();
  1662. debug = read_c0_debug();
  1663. printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
  1664. if (debug & 0x80000000) {
  1665. /*
  1666. * In branch delay slot.
  1667. * We cheat a little bit here and use EPC to calculate the
  1668. * debug return address (DEPC). EPC is restored after the
  1669. * calculation.
  1670. */
  1671. old_epc = regs->cp0_epc;
  1672. old_ra = regs->regs[31];
  1673. regs->cp0_epc = depc;
  1674. compute_return_epc(regs);
  1675. depc = regs->cp0_epc;
  1676. regs->cp0_epc = old_epc;
  1677. regs->regs[31] = old_ra;
  1678. } else
  1679. depc += 4;
  1680. write_c0_depc(depc);
  1681. #if 0
  1682. printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
  1683. write_c0_debug(debug | 0x100);
  1684. #endif
  1685. }
  1686. /*
  1687. * NMI exception handler.
  1688. * No lock; only written during early bootup by CPU 0.
  1689. */
  1690. static RAW_NOTIFIER_HEAD(nmi_chain);
  1691. int register_nmi_notifier(struct notifier_block *nb)
  1692. {
  1693. return raw_notifier_chain_register(&nmi_chain, nb);
  1694. }
  1695. void __noreturn nmi_exception_handler(struct pt_regs *regs)
  1696. {
  1697. char str[100];
  1698. nmi_enter();
  1699. raw_notifier_call_chain(&nmi_chain, 0, regs);
  1700. bust_spinlocks(1);
  1701. snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n",
  1702. smp_processor_id(), regs->cp0_epc);
  1703. regs->cp0_epc = read_c0_errorepc();
  1704. die(str, regs);
  1705. nmi_exit();
  1706. }
  1707. unsigned long ebase;
  1708. EXPORT_SYMBOL_GPL(ebase);
  1709. unsigned long exception_handlers[32];
  1710. unsigned long vi_handlers[64];
  1711. void reserve_exception_space(phys_addr_t addr, unsigned long size)
  1712. {
  1713. memblock_reserve(addr, size);
  1714. }
  1715. void __init *set_except_vector(int n, void *addr)
  1716. {
  1717. unsigned long handler = (unsigned long) addr;
  1718. unsigned long old_handler;
  1719. #ifdef CONFIG_CPU_MICROMIPS
  1720. /*
  1721. * Only the TLB handlers are cache aligned with an even
  1722. * address. All other handlers are on an odd address and
  1723. * require no modification. Otherwise, MIPS32 mode will
  1724. * be entered when handling any TLB exceptions. That
  1725. * would be bad...since we must stay in microMIPS mode.
  1726. */
  1727. if (!(handler & 0x1))
  1728. handler |= 1;
  1729. #endif
  1730. old_handler = xchg(&exception_handlers[n], handler);
  1731. if (n == 0 && cpu_has_divec) {
  1732. #ifdef CONFIG_CPU_MICROMIPS
  1733. unsigned long jump_mask = ~((1 << 27) - 1);
  1734. #else
  1735. unsigned long jump_mask = ~((1 << 28) - 1);
  1736. #endif
  1737. u32 *buf = (u32 *)(ebase + 0x200);
  1738. unsigned int k0 = 26;
  1739. if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
  1740. uasm_i_j(&buf, handler & ~jump_mask);
  1741. uasm_i_nop(&buf);
  1742. } else {
  1743. UASM_i_LA(&buf, k0, handler);
  1744. uasm_i_jr(&buf, k0);
  1745. uasm_i_nop(&buf);
  1746. }
  1747. local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
  1748. }
  1749. return (void *)old_handler;
  1750. }
  1751. static void do_default_vi(void)
  1752. {
  1753. show_regs(get_irq_regs());
  1754. panic("Caught unexpected vectored interrupt.");
  1755. }
  1756. static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
  1757. {
  1758. unsigned long handler;
  1759. unsigned long old_handler = vi_handlers[n];
  1760. int srssets = current_cpu_data.srsets;
  1761. u16 *h;
  1762. unsigned char *b;
  1763. BUG_ON(!cpu_has_veic && !cpu_has_vint);
  1764. if (addr == NULL) {
  1765. handler = (unsigned long) do_default_vi;
  1766. srs = 0;
  1767. } else
  1768. handler = (unsigned long) addr;
  1769. vi_handlers[n] = handler;
  1770. b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
  1771. if (srs >= srssets)
  1772. panic("Shadow register set %d not supported", srs);
  1773. if (cpu_has_veic) {
  1774. if (board_bind_eic_interrupt)
  1775. board_bind_eic_interrupt(n, srs);
  1776. } else if (cpu_has_vint) {
  1777. /* SRSMap is only defined if shadow sets are implemented */
  1778. if (srssets > 1)
  1779. change_c0_srsmap(0xf << n*4, srs << n*4);
  1780. }
  1781. if (srs == 0) {
  1782. /*
  1783. * If no shadow set is selected then use the default handler
  1784. * that does normal register saving and standard interrupt exit
  1785. */
  1786. extern const u8 except_vec_vi[], except_vec_vi_lui[];
  1787. extern const u8 except_vec_vi_ori[], except_vec_vi_end[];
  1788. extern const u8 rollback_except_vec_vi[];
  1789. const u8 *vec_start = using_rollback_handler() ?
  1790. rollback_except_vec_vi : except_vec_vi;
  1791. #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
  1792. const int lui_offset = except_vec_vi_lui - vec_start + 2;
  1793. const int ori_offset = except_vec_vi_ori - vec_start + 2;
  1794. #else
  1795. const int lui_offset = except_vec_vi_lui - vec_start;
  1796. const int ori_offset = except_vec_vi_ori - vec_start;
  1797. #endif
  1798. const int handler_len = except_vec_vi_end - vec_start;
  1799. if (handler_len > VECTORSPACING) {
  1800. /*
  1801. * Sigh... panicing won't help as the console
  1802. * is probably not configured :(
  1803. */
  1804. panic("VECTORSPACING too small");
  1805. }
  1806. set_handler(((unsigned long)b - ebase), vec_start,
  1807. #ifdef CONFIG_CPU_MICROMIPS
  1808. (handler_len - 1));
  1809. #else
  1810. handler_len);
  1811. #endif
  1812. h = (u16 *)(b + lui_offset);
  1813. *h = (handler >> 16) & 0xffff;
  1814. h = (u16 *)(b + ori_offset);
  1815. *h = (handler & 0xffff);
  1816. local_flush_icache_range((unsigned long)b,
  1817. (unsigned long)(b+handler_len));
  1818. }
  1819. else {
  1820. /*
  1821. * In other cases jump directly to the interrupt handler. It
  1822. * is the handler's responsibility to save registers if required
  1823. * (eg hi/lo) and return from the exception using "eret".
  1824. */
  1825. u32 insn;
  1826. h = (u16 *)b;
  1827. /* j handler */
  1828. #ifdef CONFIG_CPU_MICROMIPS
  1829. insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1);
  1830. #else
  1831. insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2);
  1832. #endif
  1833. h[0] = (insn >> 16) & 0xffff;
  1834. h[1] = insn & 0xffff;
  1835. h[2] = 0;
  1836. h[3] = 0;
  1837. local_flush_icache_range((unsigned long)b,
  1838. (unsigned long)(b+8));
  1839. }
  1840. return (void *)old_handler;
  1841. }
  1842. void *set_vi_handler(int n, vi_handler_t addr)
  1843. {
  1844. return set_vi_srs_handler(n, addr, 0);
  1845. }
  1846. extern void tlb_init(void);
  1847. /*
  1848. * Timer interrupt
  1849. */
  1850. int cp0_compare_irq;
  1851. EXPORT_SYMBOL_GPL(cp0_compare_irq);
  1852. int cp0_compare_irq_shift;
  1853. /*
  1854. * Performance counter IRQ or -1 if shared with timer
  1855. */
  1856. int cp0_perfcount_irq;
  1857. EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
  1858. /*
  1859. * Fast debug channel IRQ or -1 if not present
  1860. */
  1861. int cp0_fdc_irq;
  1862. EXPORT_SYMBOL_GPL(cp0_fdc_irq);
  1863. static int noulri;
  1864. static int __init ulri_disable(char *s)
  1865. {
  1866. pr_info("Disabling ulri\n");
  1867. noulri = 1;
  1868. return 1;
  1869. }
  1870. __setup("noulri", ulri_disable);
  1871. /* configure STATUS register */
  1872. static void configure_status(void)
  1873. {
  1874. /*
  1875. * Disable coprocessors and select 32-bit or 64-bit addressing
  1876. * and the 16/32 or 32/32 FPR register model. Reset the BEV
  1877. * flag that some firmware may have left set and the TS bit (for
  1878. * IP27). Set XX for ISA IV code to work.
  1879. */
  1880. unsigned int status_set = ST0_KERNEL_CUMASK;
  1881. #ifdef CONFIG_64BIT
  1882. status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
  1883. #endif
  1884. if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
  1885. status_set |= ST0_XX;
  1886. if (cpu_has_dsp)
  1887. status_set |= ST0_MX;
  1888. change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
  1889. status_set);
  1890. back_to_back_c0_hazard();
  1891. }
  1892. unsigned int hwrena;
  1893. EXPORT_SYMBOL_GPL(hwrena);
  1894. /* configure HWRENA register */
  1895. static void configure_hwrena(void)
  1896. {
  1897. hwrena = cpu_hwrena_impl_bits;
  1898. if (cpu_has_mips_r2_r6)
  1899. hwrena |= MIPS_HWRENA_CPUNUM |
  1900. MIPS_HWRENA_SYNCISTEP |
  1901. MIPS_HWRENA_CC |
  1902. MIPS_HWRENA_CCRES;
  1903. if (!noulri && cpu_has_userlocal)
  1904. hwrena |= MIPS_HWRENA_ULR;
  1905. if (hwrena)
  1906. write_c0_hwrena(hwrena);
  1907. }
  1908. static void configure_exception_vector(void)
  1909. {
  1910. if (cpu_has_mips_r2_r6) {
  1911. unsigned long sr = set_c0_status(ST0_BEV);
  1912. /* If available, use WG to set top bits of EBASE */
  1913. if (cpu_has_ebase_wg) {
  1914. #ifdef CONFIG_64BIT
  1915. write_c0_ebase_64(ebase | MIPS_EBASE_WG);
  1916. #else
  1917. write_c0_ebase(ebase | MIPS_EBASE_WG);
  1918. #endif
  1919. }
  1920. write_c0_ebase(ebase);
  1921. write_c0_status(sr);
  1922. }
  1923. if (cpu_has_veic || cpu_has_vint) {
  1924. /* Setting vector spacing enables EI/VI mode */
  1925. change_c0_intctl(0x3e0, VECTORSPACING);
  1926. }
  1927. if (cpu_has_divec) {
  1928. if (cpu_has_mipsmt) {
  1929. unsigned int vpflags = dvpe();
  1930. set_c0_cause(CAUSEF_IV);
  1931. evpe(vpflags);
  1932. } else
  1933. set_c0_cause(CAUSEF_IV);
  1934. }
  1935. }
  1936. void per_cpu_trap_init(bool is_boot_cpu)
  1937. {
  1938. unsigned int cpu = smp_processor_id();
  1939. configure_status();
  1940. configure_hwrena();
  1941. configure_exception_vector();
  1942. /*
  1943. * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
  1944. *
  1945. * o read IntCtl.IPTI to determine the timer interrupt
  1946. * o read IntCtl.IPPCI to determine the performance counter interrupt
  1947. * o read IntCtl.IPFDC to determine the fast debug channel interrupt
  1948. */
  1949. if (cpu_has_mips_r2_r6) {
  1950. cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
  1951. cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
  1952. cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
  1953. cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7;
  1954. if (!cp0_fdc_irq)
  1955. cp0_fdc_irq = -1;
  1956. } else {
  1957. cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
  1958. cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
  1959. cp0_perfcount_irq = -1;
  1960. cp0_fdc_irq = -1;
  1961. }
  1962. if (cpu_has_mmid)
  1963. cpu_data[cpu].asid_cache = 0;
  1964. else if (!cpu_data[cpu].asid_cache)
  1965. cpu_data[cpu].asid_cache = asid_first_version(cpu);
  1966. mmgrab(&init_mm);
  1967. current->active_mm = &init_mm;
  1968. BUG_ON(current->mm);
  1969. enter_lazy_tlb(&init_mm, current);
  1970. /* Boot CPU's cache setup in setup_arch(). */
  1971. if (!is_boot_cpu)
  1972. cpu_cache_init();
  1973. tlb_init();
  1974. TLBMISS_HANDLER_SETUP();
  1975. }
  1976. /* Install CPU exception handler */
  1977. void set_handler(unsigned long offset, const void *addr, unsigned long size)
  1978. {
  1979. #ifdef CONFIG_CPU_MICROMIPS
  1980. memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size);
  1981. #else
  1982. memcpy((void *)(ebase + offset), addr, size);
  1983. #endif
  1984. local_flush_icache_range(ebase + offset, ebase + offset + size);
  1985. }
  1986. static const char panic_null_cerr[] =
  1987. "Trying to set NULL cache error exception handler\n";
  1988. /*
  1989. * Install uncached CPU exception handler.
  1990. * This is suitable only for the cache error exception which is the only
  1991. * exception handler that is being run uncached.
  1992. */
  1993. void set_uncached_handler(unsigned long offset, void *addr,
  1994. unsigned long size)
  1995. {
  1996. unsigned long uncached_ebase = CKSEG1ADDR(ebase);
  1997. if (!addr)
  1998. panic(panic_null_cerr);
  1999. memcpy((void *)(uncached_ebase + offset), addr, size);
  2000. }
  2001. static int __initdata rdhwr_noopt;
  2002. static int __init set_rdhwr_noopt(char *str)
  2003. {
  2004. rdhwr_noopt = 1;
  2005. return 1;
  2006. }
  2007. __setup("rdhwr_noopt", set_rdhwr_noopt);
  2008. void __init trap_init(void)
  2009. {
  2010. extern char except_vec3_generic;
  2011. extern char except_vec4;
  2012. extern char except_vec3_r4000;
  2013. unsigned long i, vec_size;
  2014. phys_addr_t ebase_pa;
  2015. check_wait();
  2016. if (!cpu_has_mips_r2_r6) {
  2017. ebase = CAC_BASE;
  2018. vec_size = 0x400;
  2019. } else {
  2020. if (cpu_has_veic || cpu_has_vint)
  2021. vec_size = 0x200 + VECTORSPACING*64;
  2022. else
  2023. vec_size = PAGE_SIZE;
  2024. ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size));
  2025. if (!ebase_pa)
  2026. panic("%s: Failed to allocate %lu bytes align=0x%x\n",
  2027. __func__, vec_size, 1 << fls(vec_size));
  2028. /*
  2029. * Try to ensure ebase resides in KSeg0 if possible.
  2030. *
  2031. * It shouldn't generally be in XKPhys on MIPS64 to avoid
  2032. * hitting a poorly defined exception base for Cache Errors.
  2033. * The allocation is likely to be in the low 512MB of physical,
  2034. * in which case we should be able to convert to KSeg0.
  2035. *
  2036. * EVA is special though as it allows segments to be rearranged
  2037. * and to become uncached during cache error handling.
  2038. */
  2039. if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000))
  2040. ebase = CKSEG0ADDR(ebase_pa);
  2041. else
  2042. ebase = (unsigned long)phys_to_virt(ebase_pa);
  2043. }
  2044. if (cpu_has_mmips) {
  2045. unsigned int config3 = read_c0_config3();
  2046. if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
  2047. write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
  2048. else
  2049. write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
  2050. }
  2051. if (board_ebase_setup)
  2052. board_ebase_setup();
  2053. per_cpu_trap_init(true);
  2054. memblock_set_bottom_up(false);
  2055. /*
  2056. * Copy the generic exception handlers to their final destination.
  2057. * This will be overridden later as suitable for a particular
  2058. * configuration.
  2059. */
  2060. set_handler(0x180, &except_vec3_generic, 0x80);
  2061. /*
  2062. * Setup default vectors
  2063. */
  2064. for (i = 0; i <= 31; i++)
  2065. set_except_vector(i, handle_reserved);
  2066. /*
  2067. * Copy the EJTAG debug exception vector handler code to it's final
  2068. * destination.
  2069. */
  2070. if (cpu_has_ejtag && board_ejtag_handler_setup)
  2071. board_ejtag_handler_setup();
  2072. /*
  2073. * Only some CPUs have the watch exceptions.
  2074. */
  2075. if (cpu_has_watch)
  2076. set_except_vector(EXCCODE_WATCH, handle_watch);
  2077. /*
  2078. * Initialise interrupt handlers
  2079. */
  2080. if (cpu_has_veic || cpu_has_vint) {
  2081. int nvec = cpu_has_veic ? 64 : 8;
  2082. for (i = 0; i < nvec; i++)
  2083. set_vi_handler(i, NULL);
  2084. }
  2085. else if (cpu_has_divec)
  2086. set_handler(0x200, &except_vec4, 0x8);
  2087. /*
  2088. * Some CPUs can enable/disable for cache parity detection, but does
  2089. * it different ways.
  2090. */
  2091. parity_protection_init();
  2092. /*
  2093. * The Data Bus Errors / Instruction Bus Errors are signaled
  2094. * by external hardware. Therefore these two exceptions
  2095. * may have board specific handlers.
  2096. */
  2097. if (board_be_init)
  2098. board_be_init();
  2099. set_except_vector(EXCCODE_INT, using_rollback_handler() ?
  2100. rollback_handle_int : handle_int);
  2101. set_except_vector(EXCCODE_MOD, handle_tlbm);
  2102. set_except_vector(EXCCODE_TLBL, handle_tlbl);
  2103. set_except_vector(EXCCODE_TLBS, handle_tlbs);
  2104. set_except_vector(EXCCODE_ADEL, handle_adel);
  2105. set_except_vector(EXCCODE_ADES, handle_ades);
  2106. set_except_vector(EXCCODE_IBE, handle_ibe);
  2107. set_except_vector(EXCCODE_DBE, handle_dbe);
  2108. set_except_vector(EXCCODE_SYS, handle_sys);
  2109. set_except_vector(EXCCODE_BP, handle_bp);
  2110. if (rdhwr_noopt)
  2111. set_except_vector(EXCCODE_RI, handle_ri);
  2112. else {
  2113. if (cpu_has_vtag_icache)
  2114. set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
  2115. else if (current_cpu_type() == CPU_LOONGSON64)
  2116. set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
  2117. else
  2118. set_except_vector(EXCCODE_RI, handle_ri_rdhwr);
  2119. }
  2120. set_except_vector(EXCCODE_CPU, handle_cpu);
  2121. set_except_vector(EXCCODE_OV, handle_ov);
  2122. set_except_vector(EXCCODE_TR, handle_tr);
  2123. set_except_vector(EXCCODE_MSAFPE, handle_msa_fpe);
  2124. if (board_nmi_handler_setup)
  2125. board_nmi_handler_setup();
  2126. if (cpu_has_fpu && !cpu_has_nofpuex)
  2127. set_except_vector(EXCCODE_FPE, handle_fpe);
  2128. if (cpu_has_ftlbparex)
  2129. set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb);
  2130. if (cpu_has_gsexcex)
  2131. set_except_vector(LOONGSON_EXCCODE_GSEXC, handle_gsexc);
  2132. if (cpu_has_rixiex) {
  2133. set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0);
  2134. set_except_vector(EXCCODE_TLBXI, tlb_do_page_fault_0);
  2135. }
  2136. set_except_vector(EXCCODE_MSADIS, handle_msa);
  2137. set_except_vector(EXCCODE_MDMX, handle_mdmx);
  2138. if (cpu_has_mcheck)
  2139. set_except_vector(EXCCODE_MCHECK, handle_mcheck);
  2140. if (cpu_has_mipsmt)
  2141. set_except_vector(EXCCODE_THREAD, handle_mt);
  2142. set_except_vector(EXCCODE_DSPDIS, handle_dsp);
  2143. if (board_cache_error_setup)
  2144. board_cache_error_setup();
  2145. if (cpu_has_vce)
  2146. /* Special exception: R4[04]00 uses also the divec space. */
  2147. set_handler(0x180, &except_vec3_r4000, 0x100);
  2148. else if (cpu_has_4kex)
  2149. set_handler(0x180, &except_vec3_generic, 0x80);
  2150. else
  2151. set_handler(0x080, &except_vec3_generic, 0x80);
  2152. local_flush_icache_range(ebase, ebase + vec_size);
  2153. sort_extable(__start___dbe_table, __stop___dbe_table);
  2154. cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
  2155. }
  2156. static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd,
  2157. void *v)
  2158. {
  2159. switch (cmd) {
  2160. case CPU_PM_ENTER_FAILED:
  2161. case CPU_PM_EXIT:
  2162. configure_status();
  2163. configure_hwrena();
  2164. configure_exception_vector();
  2165. /* Restore register with CPU number for TLB handlers */
  2166. TLBMISS_HANDLER_RESTORE();
  2167. break;
  2168. }
  2169. return NOTIFY_OK;
  2170. }
  2171. static struct notifier_block trap_pm_notifier_block = {
  2172. .notifier_call = trap_pm_notifier,
  2173. };
  2174. static int __init trap_pm_init(void)
  2175. {
  2176. return cpu_pm_register_notifier(&trap_pm_notifier_block);
  2177. }
  2178. arch_initcall(trap_pm_init);