spram.c 4.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * MIPS SPRAM support
  4. *
  5. * Copyright (C) 2007, 2008 MIPS Technologies, Inc.
  6. */
  7. #include <linux/kernel.h>
  8. #include <linux/ptrace.h>
  9. #include <linux/stddef.h>
  10. #include <asm/fpu.h>
  11. #include <asm/mipsregs.h>
  12. #include <asm/r4kcache.h>
  13. #include <asm/hazards.h>
  14. /*
  15. * These definitions are correct for the 24K/34K/74K SPRAM sample
  16. * implementation. The 4KS interpreted the tags differently...
  17. */
  18. #define SPRAM_TAG0_ENABLE 0x00000080
  19. #define SPRAM_TAG0_PA_MASK 0xfffff000
  20. #define SPRAM_TAG1_SIZE_MASK 0xfffff000
  21. #define SPRAM_TAG_STRIDE 8
  22. #define ERRCTL_SPRAM (1 << 28)
  23. /* errctl access */
  24. #define read_c0_errctl(x) read_c0_ecc(x)
  25. #define write_c0_errctl(x) write_c0_ecc(x)
  26. /*
  27. * Different semantics to the set_c0_* function built by __BUILD_SET_C0
  28. */
  29. static unsigned int bis_c0_errctl(unsigned int set)
  30. {
  31. unsigned int res;
  32. res = read_c0_errctl();
  33. write_c0_errctl(res | set);
  34. return res;
  35. }
  36. static void ispram_store_tag(unsigned int offset, unsigned int data)
  37. {
  38. unsigned int errctl;
  39. /* enable SPRAM tag access */
  40. errctl = bis_c0_errctl(ERRCTL_SPRAM);
  41. ehb();
  42. write_c0_taglo(data);
  43. ehb();
  44. cache_op(Index_Store_Tag_I, CKSEG0|offset);
  45. ehb();
  46. write_c0_errctl(errctl);
  47. ehb();
  48. }
  49. static unsigned int ispram_load_tag(unsigned int offset)
  50. {
  51. unsigned int data;
  52. unsigned int errctl;
  53. /* enable SPRAM tag access */
  54. errctl = bis_c0_errctl(ERRCTL_SPRAM);
  55. ehb();
  56. cache_op(Index_Load_Tag_I, CKSEG0 | offset);
  57. ehb();
  58. data = read_c0_taglo();
  59. ehb();
  60. write_c0_errctl(errctl);
  61. ehb();
  62. return data;
  63. }
  64. static void dspram_store_tag(unsigned int offset, unsigned int data)
  65. {
  66. unsigned int errctl;
  67. /* enable SPRAM tag access */
  68. errctl = bis_c0_errctl(ERRCTL_SPRAM);
  69. ehb();
  70. write_c0_dtaglo(data);
  71. ehb();
  72. cache_op(Index_Store_Tag_D, CKSEG0 | offset);
  73. ehb();
  74. write_c0_errctl(errctl);
  75. ehb();
  76. }
  77. static unsigned int dspram_load_tag(unsigned int offset)
  78. {
  79. unsigned int data;
  80. unsigned int errctl;
  81. errctl = bis_c0_errctl(ERRCTL_SPRAM);
  82. ehb();
  83. cache_op(Index_Load_Tag_D, CKSEG0 | offset);
  84. ehb();
  85. data = read_c0_dtaglo();
  86. ehb();
  87. write_c0_errctl(errctl);
  88. ehb();
  89. return data;
  90. }
  91. static void probe_spram(char *type,
  92. unsigned int base,
  93. unsigned int (*read)(unsigned int),
  94. void (*write)(unsigned int, unsigned int))
  95. {
  96. unsigned int firstsize = 0, lastsize = 0;
  97. unsigned int firstpa = 0, lastpa = 0, pa = 0;
  98. unsigned int offset = 0;
  99. unsigned int size, tag0, tag1;
  100. unsigned int enabled;
  101. int i;
  102. /*
  103. * The limit is arbitrary but avoids the loop running away if
  104. * the SPRAM tags are implemented differently
  105. */
  106. for (i = 0; i < 8; i++) {
  107. tag0 = read(offset);
  108. tag1 = read(offset+SPRAM_TAG_STRIDE);
  109. pr_debug("DBG %s%d: tag0=%08x tag1=%08x\n",
  110. type, i, tag0, tag1);
  111. size = tag1 & SPRAM_TAG1_SIZE_MASK;
  112. if (size == 0)
  113. break;
  114. if (i != 0) {
  115. /* tags may repeat... */
  116. if ((pa == firstpa && size == firstsize) ||
  117. (pa == lastpa && size == lastsize))
  118. break;
  119. }
  120. /* Align base with size */
  121. base = (base + size - 1) & ~(size-1);
  122. /* reprogram the base address base address and enable */
  123. tag0 = (base & SPRAM_TAG0_PA_MASK) | SPRAM_TAG0_ENABLE;
  124. write(offset, tag0);
  125. base += size;
  126. /* reread the tag */
  127. tag0 = read(offset);
  128. pa = tag0 & SPRAM_TAG0_PA_MASK;
  129. enabled = tag0 & SPRAM_TAG0_ENABLE;
  130. if (i == 0) {
  131. firstpa = pa;
  132. firstsize = size;
  133. }
  134. lastpa = pa;
  135. lastsize = size;
  136. if (strcmp(type, "DSPRAM") == 0) {
  137. unsigned int *vp = (unsigned int *)(CKSEG1 | pa);
  138. unsigned int v;
  139. #define TDAT 0x5a5aa5a5
  140. vp[0] = TDAT;
  141. vp[1] = ~TDAT;
  142. mb();
  143. v = vp[0];
  144. if (v != TDAT)
  145. printk(KERN_ERR "vp=%p wrote=%08x got=%08x\n",
  146. vp, TDAT, v);
  147. v = vp[1];
  148. if (v != ~TDAT)
  149. printk(KERN_ERR "vp=%p wrote=%08x got=%08x\n",
  150. vp+1, ~TDAT, v);
  151. }
  152. pr_info("%s%d: PA=%08x,Size=%08x%s\n",
  153. type, i, pa, size, enabled ? ",enabled" : "");
  154. offset += 2 * SPRAM_TAG_STRIDE;
  155. }
  156. }
  157. void spram_config(void)
  158. {
  159. unsigned int config0;
  160. switch (current_cpu_type()) {
  161. case CPU_24K:
  162. case CPU_34K:
  163. case CPU_74K:
  164. case CPU_1004K:
  165. case CPU_1074K:
  166. case CPU_INTERAPTIV:
  167. case CPU_PROAPTIV:
  168. case CPU_P5600:
  169. case CPU_QEMU_GENERIC:
  170. case CPU_I6400:
  171. case CPU_P6600:
  172. config0 = read_c0_config();
  173. /* FIXME: addresses are Malta specific */
  174. if (config0 & MIPS_CONF_ISP) {
  175. probe_spram("ISPRAM", 0x1c000000,
  176. &ispram_load_tag, &ispram_store_tag);
  177. }
  178. if (config0 & MIPS_CONF_DSP)
  179. probe_spram("DSPRAM", 0x1c100000,
  180. &dspram_load_tag, &dspram_store_tag);
  181. }
  182. }