smp-mt.c 6.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240
  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. *
  4. * Copyright (C) 2004, 05, 06 MIPS Technologies, Inc.
  5. * Elizabeth Clarke ([email protected])
  6. * Ralf Baechle ([email protected])
  7. * Copyright (C) 2006 Ralf Baechle ([email protected])
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/sched.h>
  11. #include <linux/cpumask.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/compiler.h>
  14. #include <linux/sched/task_stack.h>
  15. #include <linux/smp.h>
  16. #include <linux/atomic.h>
  17. #include <asm/cacheflush.h>
  18. #include <asm/cpu.h>
  19. #include <asm/processor.h>
  20. #include <asm/hardirq.h>
  21. #include <asm/mmu_context.h>
  22. #include <asm/time.h>
  23. #include <asm/mipsregs.h>
  24. #include <asm/mipsmtregs.h>
  25. #include <asm/mips_mt.h>
  26. #include <asm/mips-cps.h>
  27. static void __init smvp_copy_vpe_config(void)
  28. {
  29. write_vpe_c0_status(
  30. (read_c0_status() & ~(ST0_IM | ST0_IE | ST0_KSU)) | ST0_CU0);
  31. /* set config to be the same as vpe0, particularly kseg0 coherency alg */
  32. write_vpe_c0_config( read_c0_config());
  33. /* make sure there are no software interrupts pending */
  34. write_vpe_c0_cause(0);
  35. /* Propagate Config7 */
  36. write_vpe_c0_config7(read_c0_config7());
  37. write_vpe_c0_count(read_c0_count());
  38. }
  39. static unsigned int __init smvp_vpe_init(unsigned int tc, unsigned int mvpconf0,
  40. unsigned int ncpu)
  41. {
  42. if (tc > ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT))
  43. return ncpu;
  44. /* Deactivate all but VPE 0 */
  45. if (tc != 0) {
  46. unsigned long tmp = read_vpe_c0_vpeconf0();
  47. tmp &= ~VPECONF0_VPA;
  48. /* master VPE */
  49. tmp |= VPECONF0_MVP;
  50. write_vpe_c0_vpeconf0(tmp);
  51. /* Record this as available CPU */
  52. set_cpu_possible(tc, true);
  53. set_cpu_present(tc, true);
  54. __cpu_number_map[tc] = ++ncpu;
  55. __cpu_logical_map[ncpu] = tc;
  56. }
  57. /* Disable multi-threading with TC's */
  58. write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE);
  59. if (tc != 0)
  60. smvp_copy_vpe_config();
  61. cpu_set_vpe_id(&cpu_data[ncpu], tc);
  62. return ncpu;
  63. }
  64. static void __init smvp_tc_init(unsigned int tc, unsigned int mvpconf0)
  65. {
  66. unsigned long tmp;
  67. if (!tc)
  68. return;
  69. /* bind a TC to each VPE, May as well put all excess TC's
  70. on the last VPE */
  71. if (tc >= (((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT)+1))
  72. write_tc_c0_tcbind(read_tc_c0_tcbind() | ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT));
  73. else {
  74. write_tc_c0_tcbind(read_tc_c0_tcbind() | tc);
  75. /* and set XTC */
  76. write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | (tc << VPECONF0_XTC_SHIFT));
  77. }
  78. tmp = read_tc_c0_tcstatus();
  79. /* mark not allocated and not dynamically allocatable */
  80. tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
  81. tmp |= TCSTATUS_IXMT; /* interrupt exempt */
  82. write_tc_c0_tcstatus(tmp);
  83. write_tc_c0_tchalt(TCHALT_H);
  84. }
  85. static void vsmp_init_secondary(void)
  86. {
  87. /* This is Malta specific: IPI,performance and timer interrupts */
  88. if (mips_gic_present())
  89. change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 |
  90. STATUSF_IP4 | STATUSF_IP5 |
  91. STATUSF_IP6 | STATUSF_IP7);
  92. else
  93. change_c0_status(ST0_IM, STATUSF_IP0 | STATUSF_IP1 |
  94. STATUSF_IP6 | STATUSF_IP7);
  95. }
  96. static void vsmp_smp_finish(void)
  97. {
  98. /* CDFIXME: remove this? */
  99. write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ));
  100. #ifdef CONFIG_MIPS_MT_FPAFF
  101. /* If we have an FPU, enroll ourselves in the FPU-full mask */
  102. if (cpu_has_fpu)
  103. cpumask_set_cpu(smp_processor_id(), &mt_fpu_cpumask);
  104. #endif /* CONFIG_MIPS_MT_FPAFF */
  105. local_irq_enable();
  106. }
  107. /*
  108. * Setup the PC, SP, and GP of a secondary processor and start it
  109. * running!
  110. * smp_bootstrap is the place to resume from
  111. * __KSTK_TOS(idle) is apparently the stack pointer
  112. * (unsigned long)idle->thread_info the gp
  113. * assumes a 1:1 mapping of TC => VPE
  114. */
  115. static int vsmp_boot_secondary(int cpu, struct task_struct *idle)
  116. {
  117. struct thread_info *gp = task_thread_info(idle);
  118. dvpe();
  119. set_c0_mvpcontrol(MVPCONTROL_VPC);
  120. settc(cpu);
  121. /* restart */
  122. write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);
  123. /* enable the tc this vpe/cpu will be running */
  124. write_tc_c0_tcstatus((read_tc_c0_tcstatus() & ~TCSTATUS_IXMT) | TCSTATUS_A);
  125. write_tc_c0_tchalt(0);
  126. /* enable the VPE */
  127. write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);
  128. /* stack pointer */
  129. write_tc_gpr_sp( __KSTK_TOS(idle));
  130. /* global pointer */
  131. write_tc_gpr_gp((unsigned long)gp);
  132. flush_icache_range((unsigned long)gp,
  133. (unsigned long)(gp + sizeof(struct thread_info)));
  134. /* finally out of configuration and into chaos */
  135. clear_c0_mvpcontrol(MVPCONTROL_VPC);
  136. evpe(EVPE_ENABLE);
  137. return 0;
  138. }
  139. /*
  140. * Common setup before any secondaries are started
  141. * Make sure all CPU's are in a sensible state before we boot any of the
  142. * secondaries
  143. */
  144. static void __init vsmp_smp_setup(void)
  145. {
  146. unsigned int mvpconf0, ntc, tc, ncpu = 0;
  147. unsigned int nvpe;
  148. #ifdef CONFIG_MIPS_MT_FPAFF
  149. /* If we have an FPU, enroll ourselves in the FPU-full mask */
  150. if (cpu_has_fpu)
  151. cpumask_set_cpu(0, &mt_fpu_cpumask);
  152. #endif /* CONFIG_MIPS_MT_FPAFF */
  153. if (!cpu_has_mipsmt)
  154. return;
  155. /* disable MT so we can configure */
  156. dvpe();
  157. dmt();
  158. /* Put MVPE's into 'configuration state' */
  159. set_c0_mvpcontrol(MVPCONTROL_VPC);
  160. mvpconf0 = read_c0_mvpconf0();
  161. ntc = (mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT;
  162. nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
  163. smp_num_siblings = nvpe;
  164. /* we'll always have more TC's than VPE's, so loop setting everything
  165. to a sensible state */
  166. for (tc = 0; tc <= ntc; tc++) {
  167. settc(tc);
  168. smvp_tc_init(tc, mvpconf0);
  169. ncpu = smvp_vpe_init(tc, mvpconf0, ncpu);
  170. }
  171. /* Release config state */
  172. clear_c0_mvpcontrol(MVPCONTROL_VPC);
  173. /* We'll wait until starting the secondaries before starting MVPE */
  174. printk(KERN_INFO "Detected %i available secondary CPU(s)\n", ncpu);
  175. }
  176. static void __init vsmp_prepare_cpus(unsigned int max_cpus)
  177. {
  178. mips_mt_set_cpuoptions();
  179. }
  180. const struct plat_smp_ops vsmp_smp_ops = {
  181. .send_ipi_single = mips_smp_send_ipi_single,
  182. .send_ipi_mask = mips_smp_send_ipi_mask,
  183. .init_secondary = vsmp_init_secondary,
  184. .smp_finish = vsmp_smp_finish,
  185. .boot_secondary = vsmp_boot_secondary,
  186. .smp_setup = vsmp_smp_setup,
  187. .prepare_cpus = vsmp_prepare_cpus,
  188. };