process.c 22 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 1994 - 1999, 2000 by Ralf Baechle and others.
  7. * Copyright (C) 2005, 2006 by Ralf Baechle ([email protected])
  8. * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  9. * Copyright (C) 2004 Thiemo Seufer
  10. * Copyright (C) 2013 Imagination Technologies Ltd.
  11. */
  12. #include <linux/cpu.h>
  13. #include <linux/errno.h>
  14. #include <linux/init.h>
  15. #include <linux/kallsyms.h>
  16. #include <linux/kernel.h>
  17. #include <linux/nmi.h>
  18. #include <linux/personality.h>
  19. #include <linux/prctl.h>
  20. #include <linux/random.h>
  21. #include <linux/sched.h>
  22. #include <linux/sched/debug.h>
  23. #include <linux/sched/task_stack.h>
  24. #include <asm/abi.h>
  25. #include <asm/asm.h>
  26. #include <asm/dsemul.h>
  27. #include <asm/dsp.h>
  28. #include <asm/exec.h>
  29. #include <asm/fpu.h>
  30. #include <asm/inst.h>
  31. #include <asm/irq.h>
  32. #include <asm/irq_regs.h>
  33. #include <asm/isadep.h>
  34. #include <asm/msa.h>
  35. #include <asm/mips-cps.h>
  36. #include <asm/mipsregs.h>
  37. #include <asm/processor.h>
  38. #include <asm/reg.h>
  39. #include <asm/stacktrace.h>
  40. #ifdef CONFIG_HOTPLUG_CPU
  41. void arch_cpu_idle_dead(void)
  42. {
  43. play_dead();
  44. }
  45. #endif
  46. asmlinkage void ret_from_fork(void);
  47. asmlinkage void ret_from_kernel_thread(void);
  48. void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp)
  49. {
  50. unsigned long status;
  51. /* New thread loses kernel privileges. */
  52. status = regs->cp0_status & ~(ST0_CU0|ST0_CU1|ST0_CU2|ST0_FR|KU_MASK);
  53. status |= KU_USER;
  54. regs->cp0_status = status;
  55. lose_fpu(0);
  56. clear_thread_flag(TIF_MSA_CTX_LIVE);
  57. clear_used_math();
  58. #ifdef CONFIG_MIPS_FP_SUPPORT
  59. atomic_set(&current->thread.bd_emu_frame, BD_EMUFRAME_NONE);
  60. #endif
  61. init_dsp();
  62. regs->cp0_epc = pc;
  63. regs->regs[29] = sp;
  64. }
  65. void exit_thread(struct task_struct *tsk)
  66. {
  67. /*
  68. * User threads may have allocated a delay slot emulation frame.
  69. * If so, clean up that allocation.
  70. */
  71. if (!(current->flags & PF_KTHREAD))
  72. dsemul_thread_cleanup(tsk);
  73. }
  74. int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
  75. {
  76. /*
  77. * Save any process state which is live in hardware registers to the
  78. * parent context prior to duplication. This prevents the new child
  79. * state becoming stale if the parent is preempted before copy_thread()
  80. * gets a chance to save the parent's live hardware registers to the
  81. * child context.
  82. */
  83. preempt_disable();
  84. if (is_msa_enabled())
  85. save_msa(current);
  86. else if (is_fpu_owner())
  87. _save_fp(current);
  88. save_dsp(current);
  89. preempt_enable();
  90. *dst = *src;
  91. return 0;
  92. }
  93. /*
  94. * Copy architecture-specific thread state
  95. */
  96. int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
  97. {
  98. unsigned long clone_flags = args->flags;
  99. unsigned long usp = args->stack;
  100. unsigned long tls = args->tls;
  101. struct thread_info *ti = task_thread_info(p);
  102. struct pt_regs *childregs, *regs = current_pt_regs();
  103. unsigned long childksp;
  104. childksp = (unsigned long)task_stack_page(p) + THREAD_SIZE - 32;
  105. /* set up new TSS. */
  106. childregs = (struct pt_regs *) childksp - 1;
  107. /* Put the stack after the struct pt_regs. */
  108. childksp = (unsigned long) childregs;
  109. p->thread.cp0_status = (read_c0_status() & ~(ST0_CU2|ST0_CU1)) | ST0_KERNEL_CUMASK;
  110. /*
  111. * New tasks lose permission to use the fpu. This accelerates context
  112. * switching for most programs since they don't use the fpu.
  113. */
  114. clear_tsk_thread_flag(p, TIF_USEDFPU);
  115. clear_tsk_thread_flag(p, TIF_USEDMSA);
  116. clear_tsk_thread_flag(p, TIF_MSA_CTX_LIVE);
  117. #ifdef CONFIG_MIPS_MT_FPAFF
  118. clear_tsk_thread_flag(p, TIF_FPUBOUND);
  119. #endif /* CONFIG_MIPS_MT_FPAFF */
  120. if (unlikely(args->fn)) {
  121. /* kernel thread */
  122. unsigned long status = p->thread.cp0_status;
  123. memset(childregs, 0, sizeof(struct pt_regs));
  124. p->thread.reg16 = (unsigned long)args->fn;
  125. p->thread.reg17 = (unsigned long)args->fn_arg;
  126. p->thread.reg29 = childksp;
  127. p->thread.reg31 = (unsigned long) ret_from_kernel_thread;
  128. #if defined(CONFIG_CPU_R3000)
  129. status = (status & ~(ST0_KUP | ST0_IEP | ST0_IEC)) |
  130. ((status & (ST0_KUC | ST0_IEC)) << 2);
  131. #else
  132. status |= ST0_EXL;
  133. #endif
  134. childregs->cp0_status = status;
  135. return 0;
  136. }
  137. /* user thread */
  138. *childregs = *regs;
  139. childregs->regs[7] = 0; /* Clear error flag */
  140. childregs->regs[2] = 0; /* Child gets zero as return value */
  141. if (usp)
  142. childregs->regs[29] = usp;
  143. p->thread.reg29 = (unsigned long) childregs;
  144. p->thread.reg31 = (unsigned long) ret_from_fork;
  145. childregs->cp0_status &= ~(ST0_CU2|ST0_CU1);
  146. #ifdef CONFIG_MIPS_FP_SUPPORT
  147. atomic_set(&p->thread.bd_emu_frame, BD_EMUFRAME_NONE);
  148. #endif
  149. if (clone_flags & CLONE_SETTLS)
  150. ti->tp_value = tls;
  151. return 0;
  152. }
  153. #ifdef CONFIG_STACKPROTECTOR
  154. #include <linux/stackprotector.h>
  155. unsigned long __stack_chk_guard __read_mostly;
  156. EXPORT_SYMBOL(__stack_chk_guard);
  157. #endif
  158. struct mips_frame_info {
  159. void *func;
  160. unsigned long func_size;
  161. int frame_size;
  162. int pc_offset;
  163. };
  164. #define J_TARGET(pc,target) \
  165. (((unsigned long)(pc) & 0xf0000000) | ((target) << 2))
  166. static inline int is_jr_ra_ins(union mips_instruction *ip)
  167. {
  168. #ifdef CONFIG_CPU_MICROMIPS
  169. /*
  170. * jr16 ra
  171. * jr ra
  172. */
  173. if (mm_insn_16bit(ip->word >> 16)) {
  174. if (ip->mm16_r5_format.opcode == mm_pool16c_op &&
  175. ip->mm16_r5_format.rt == mm_jr16_op &&
  176. ip->mm16_r5_format.imm == 31)
  177. return 1;
  178. return 0;
  179. }
  180. if (ip->r_format.opcode == mm_pool32a_op &&
  181. ip->r_format.func == mm_pool32axf_op &&
  182. ((ip->u_format.uimmediate >> 6) & GENMASK(9, 0)) == mm_jalr_op &&
  183. ip->r_format.rt == 31)
  184. return 1;
  185. return 0;
  186. #else
  187. if (ip->r_format.opcode == spec_op &&
  188. ip->r_format.func == jr_op &&
  189. ip->r_format.rs == 31)
  190. return 1;
  191. return 0;
  192. #endif
  193. }
  194. static inline int is_ra_save_ins(union mips_instruction *ip, int *poff)
  195. {
  196. #ifdef CONFIG_CPU_MICROMIPS
  197. /*
  198. * swsp ra,offset
  199. * swm16 reglist,offset(sp)
  200. * swm32 reglist,offset(sp)
  201. * sw32 ra,offset(sp)
  202. * jradiussp - NOT SUPPORTED
  203. *
  204. * microMIPS is way more fun...
  205. */
  206. if (mm_insn_16bit(ip->word >> 16)) {
  207. switch (ip->mm16_r5_format.opcode) {
  208. case mm_swsp16_op:
  209. if (ip->mm16_r5_format.rt != 31)
  210. return 0;
  211. *poff = ip->mm16_r5_format.imm;
  212. *poff = (*poff << 2) / sizeof(ulong);
  213. return 1;
  214. case mm_pool16c_op:
  215. switch (ip->mm16_m_format.func) {
  216. case mm_swm16_op:
  217. *poff = ip->mm16_m_format.imm;
  218. *poff += 1 + ip->mm16_m_format.rlist;
  219. *poff = (*poff << 2) / sizeof(ulong);
  220. return 1;
  221. default:
  222. return 0;
  223. }
  224. default:
  225. return 0;
  226. }
  227. }
  228. switch (ip->i_format.opcode) {
  229. case mm_sw32_op:
  230. if (ip->i_format.rs != 29)
  231. return 0;
  232. if (ip->i_format.rt != 31)
  233. return 0;
  234. *poff = ip->i_format.simmediate / sizeof(ulong);
  235. return 1;
  236. case mm_pool32b_op:
  237. switch (ip->mm_m_format.func) {
  238. case mm_swm32_func:
  239. if (ip->mm_m_format.rd < 0x10)
  240. return 0;
  241. if (ip->mm_m_format.base != 29)
  242. return 0;
  243. *poff = ip->mm_m_format.simmediate;
  244. *poff += (ip->mm_m_format.rd & 0xf) * sizeof(u32);
  245. *poff /= sizeof(ulong);
  246. return 1;
  247. default:
  248. return 0;
  249. }
  250. default:
  251. return 0;
  252. }
  253. #else
  254. /* sw / sd $ra, offset($sp) */
  255. if ((ip->i_format.opcode == sw_op || ip->i_format.opcode == sd_op) &&
  256. ip->i_format.rs == 29 && ip->i_format.rt == 31) {
  257. *poff = ip->i_format.simmediate / sizeof(ulong);
  258. return 1;
  259. }
  260. #ifdef CONFIG_CPU_LOONGSON64
  261. if ((ip->loongson3_lswc2_format.opcode == swc2_op) &&
  262. (ip->loongson3_lswc2_format.ls == 1) &&
  263. (ip->loongson3_lswc2_format.fr == 0) &&
  264. (ip->loongson3_lswc2_format.base == 29)) {
  265. if (ip->loongson3_lswc2_format.rt == 31) {
  266. *poff = ip->loongson3_lswc2_format.offset << 1;
  267. return 1;
  268. }
  269. if (ip->loongson3_lswc2_format.rq == 31) {
  270. *poff = (ip->loongson3_lswc2_format.offset << 1) + 1;
  271. return 1;
  272. }
  273. }
  274. #endif
  275. return 0;
  276. #endif
  277. }
  278. static inline int is_jump_ins(union mips_instruction *ip)
  279. {
  280. #ifdef CONFIG_CPU_MICROMIPS
  281. /*
  282. * jr16,jrc,jalr16,jalr16
  283. * jal
  284. * jalr/jr,jalr.hb/jr.hb,jalrs,jalrs.hb
  285. * jraddiusp - NOT SUPPORTED
  286. *
  287. * microMIPS is kind of more fun...
  288. */
  289. if (mm_insn_16bit(ip->word >> 16)) {
  290. if ((ip->mm16_r5_format.opcode == mm_pool16c_op &&
  291. (ip->mm16_r5_format.rt & mm_jr16_op) == mm_jr16_op))
  292. return 1;
  293. return 0;
  294. }
  295. if (ip->j_format.opcode == mm_j32_op)
  296. return 1;
  297. if (ip->j_format.opcode == mm_jal32_op)
  298. return 1;
  299. if (ip->r_format.opcode != mm_pool32a_op ||
  300. ip->r_format.func != mm_pool32axf_op)
  301. return 0;
  302. return ((ip->u_format.uimmediate >> 6) & mm_jalr_op) == mm_jalr_op;
  303. #else
  304. if (ip->j_format.opcode == j_op)
  305. return 1;
  306. if (ip->j_format.opcode == jal_op)
  307. return 1;
  308. if (ip->r_format.opcode != spec_op)
  309. return 0;
  310. return ip->r_format.func == jalr_op || ip->r_format.func == jr_op;
  311. #endif
  312. }
  313. static inline int is_sp_move_ins(union mips_instruction *ip, int *frame_size)
  314. {
  315. #ifdef CONFIG_CPU_MICROMIPS
  316. unsigned short tmp;
  317. /*
  318. * addiusp -imm
  319. * addius5 sp,-imm
  320. * addiu32 sp,sp,-imm
  321. * jradiussp - NOT SUPPORTED
  322. *
  323. * microMIPS is not more fun...
  324. */
  325. if (mm_insn_16bit(ip->word >> 16)) {
  326. if (ip->mm16_r3_format.opcode == mm_pool16d_op &&
  327. ip->mm16_r3_format.simmediate & mm_addiusp_func) {
  328. tmp = ip->mm_b0_format.simmediate >> 1;
  329. tmp = ((tmp & 0x1ff) ^ 0x100) - 0x100;
  330. if ((tmp + 2) < 4) /* 0x0,0x1,0x1fe,0x1ff are special */
  331. tmp ^= 0x100;
  332. *frame_size = -(signed short)(tmp << 2);
  333. return 1;
  334. }
  335. if (ip->mm16_r5_format.opcode == mm_pool16d_op &&
  336. ip->mm16_r5_format.rt == 29) {
  337. tmp = ip->mm16_r5_format.imm >> 1;
  338. *frame_size = -(signed short)(tmp & 0xf);
  339. return 1;
  340. }
  341. return 0;
  342. }
  343. if (ip->mm_i_format.opcode == mm_addiu32_op &&
  344. ip->mm_i_format.rt == 29 && ip->mm_i_format.rs == 29) {
  345. *frame_size = -ip->i_format.simmediate;
  346. return 1;
  347. }
  348. #else
  349. /* addiu/daddiu sp,sp,-imm */
  350. if (ip->i_format.rs != 29 || ip->i_format.rt != 29)
  351. return 0;
  352. if (ip->i_format.opcode == addiu_op ||
  353. ip->i_format.opcode == daddiu_op) {
  354. *frame_size = -ip->i_format.simmediate;
  355. return 1;
  356. }
  357. #endif
  358. return 0;
  359. }
  360. static int get_frame_info(struct mips_frame_info *info)
  361. {
  362. bool is_mmips = IS_ENABLED(CONFIG_CPU_MICROMIPS);
  363. union mips_instruction insn, *ip, *ip_end;
  364. unsigned int last_insn_size = 0;
  365. bool saw_jump = false;
  366. info->pc_offset = -1;
  367. info->frame_size = 0;
  368. ip = (void *)msk_isa16_mode((ulong)info->func);
  369. if (!ip)
  370. goto err;
  371. ip_end = (void *)ip + (info->func_size ? info->func_size : 512);
  372. while (ip < ip_end) {
  373. ip = (void *)ip + last_insn_size;
  374. if (is_mmips && mm_insn_16bit(ip->halfword[0])) {
  375. insn.word = ip->halfword[0] << 16;
  376. last_insn_size = 2;
  377. } else if (is_mmips) {
  378. insn.word = ip->halfword[0] << 16 | ip->halfword[1];
  379. last_insn_size = 4;
  380. } else {
  381. insn.word = ip->word;
  382. last_insn_size = 4;
  383. }
  384. if (is_jr_ra_ins(ip)) {
  385. break;
  386. } else if (!info->frame_size) {
  387. is_sp_move_ins(&insn, &info->frame_size);
  388. continue;
  389. } else if (!saw_jump && is_jump_ins(ip)) {
  390. /*
  391. * If we see a jump instruction, we are finished
  392. * with the frame save.
  393. *
  394. * Some functions can have a shortcut return at
  395. * the beginning of the function, so don't start
  396. * looking for jump instruction until we see the
  397. * frame setup.
  398. *
  399. * The RA save instruction can get put into the
  400. * delay slot of the jump instruction, so look
  401. * at the next instruction, too.
  402. */
  403. saw_jump = true;
  404. continue;
  405. }
  406. if (info->pc_offset == -1 &&
  407. is_ra_save_ins(&insn, &info->pc_offset))
  408. break;
  409. if (saw_jump)
  410. break;
  411. }
  412. if (info->frame_size && info->pc_offset >= 0) /* nested */
  413. return 0;
  414. if (info->pc_offset < 0) /* leaf */
  415. return 1;
  416. /* prologue seems bogus... */
  417. err:
  418. return -1;
  419. }
  420. static struct mips_frame_info schedule_mfi __read_mostly;
  421. #ifdef CONFIG_KALLSYMS
  422. static unsigned long get___schedule_addr(void)
  423. {
  424. return kallsyms_lookup_name("__schedule");
  425. }
  426. #else
  427. static unsigned long get___schedule_addr(void)
  428. {
  429. union mips_instruction *ip = (void *)schedule;
  430. int max_insns = 8;
  431. int i;
  432. for (i = 0; i < max_insns; i++, ip++) {
  433. if (ip->j_format.opcode == j_op)
  434. return J_TARGET(ip, ip->j_format.target);
  435. }
  436. return 0;
  437. }
  438. #endif
  439. static int __init frame_info_init(void)
  440. {
  441. unsigned long size = 0;
  442. #ifdef CONFIG_KALLSYMS
  443. unsigned long ofs;
  444. #endif
  445. unsigned long addr;
  446. addr = get___schedule_addr();
  447. if (!addr)
  448. addr = (unsigned long)schedule;
  449. #ifdef CONFIG_KALLSYMS
  450. kallsyms_lookup_size_offset(addr, &size, &ofs);
  451. #endif
  452. schedule_mfi.func = (void *)addr;
  453. schedule_mfi.func_size = size;
  454. get_frame_info(&schedule_mfi);
  455. /*
  456. * Without schedule() frame info, result given by
  457. * thread_saved_pc() and __get_wchan() are not reliable.
  458. */
  459. if (schedule_mfi.pc_offset < 0)
  460. printk("Can't analyze schedule() prologue at %p\n", schedule);
  461. return 0;
  462. }
  463. arch_initcall(frame_info_init);
  464. /*
  465. * Return saved PC of a blocked thread.
  466. */
  467. static unsigned long thread_saved_pc(struct task_struct *tsk)
  468. {
  469. struct thread_struct *t = &tsk->thread;
  470. /* New born processes are a special case */
  471. if (t->reg31 == (unsigned long) ret_from_fork)
  472. return t->reg31;
  473. if (schedule_mfi.pc_offset < 0)
  474. return 0;
  475. return ((unsigned long *)t->reg29)[schedule_mfi.pc_offset];
  476. }
  477. #ifdef CONFIG_KALLSYMS
  478. /* generic stack unwinding function */
  479. unsigned long notrace unwind_stack_by_address(unsigned long stack_page,
  480. unsigned long *sp,
  481. unsigned long pc,
  482. unsigned long *ra)
  483. {
  484. unsigned long low, high, irq_stack_high;
  485. struct mips_frame_info info;
  486. unsigned long size, ofs;
  487. struct pt_regs *regs;
  488. int leaf;
  489. if (!stack_page)
  490. return 0;
  491. /*
  492. * IRQ stacks start at IRQ_STACK_START
  493. * task stacks at THREAD_SIZE - 32
  494. */
  495. low = stack_page;
  496. if (!preemptible() && on_irq_stack(raw_smp_processor_id(), *sp)) {
  497. high = stack_page + IRQ_STACK_START;
  498. irq_stack_high = high;
  499. } else {
  500. high = stack_page + THREAD_SIZE - 32;
  501. irq_stack_high = 0;
  502. }
  503. /*
  504. * If we reached the top of the interrupt stack, start unwinding
  505. * the interrupted task stack.
  506. */
  507. if (unlikely(*sp == irq_stack_high)) {
  508. unsigned long task_sp = *(unsigned long *)*sp;
  509. /*
  510. * Check that the pointer saved in the IRQ stack head points to
  511. * something within the stack of the current task
  512. */
  513. if (!object_is_on_stack((void *)task_sp))
  514. return 0;
  515. /*
  516. * Follow pointer to tasks kernel stack frame where interrupted
  517. * state was saved.
  518. */
  519. regs = (struct pt_regs *)task_sp;
  520. pc = regs->cp0_epc;
  521. if (!user_mode(regs) && __kernel_text_address(pc)) {
  522. *sp = regs->regs[29];
  523. *ra = regs->regs[31];
  524. return pc;
  525. }
  526. return 0;
  527. }
  528. if (!kallsyms_lookup_size_offset(pc, &size, &ofs))
  529. return 0;
  530. /*
  531. * Return ra if an exception occurred at the first instruction
  532. */
  533. if (unlikely(ofs == 0)) {
  534. pc = *ra;
  535. *ra = 0;
  536. return pc;
  537. }
  538. info.func = (void *)(pc - ofs);
  539. info.func_size = ofs; /* analyze from start to ofs */
  540. leaf = get_frame_info(&info);
  541. if (leaf < 0)
  542. return 0;
  543. if (*sp < low || *sp + info.frame_size > high)
  544. return 0;
  545. if (leaf)
  546. /*
  547. * For some extreme cases, get_frame_info() can
  548. * consider wrongly a nested function as a leaf
  549. * one. In that cases avoid to return always the
  550. * same value.
  551. */
  552. pc = pc != *ra ? *ra : 0;
  553. else
  554. pc = ((unsigned long *)(*sp))[info.pc_offset];
  555. *sp += info.frame_size;
  556. *ra = 0;
  557. return __kernel_text_address(pc) ? pc : 0;
  558. }
  559. EXPORT_SYMBOL(unwind_stack_by_address);
  560. /* used by show_backtrace() */
  561. unsigned long unwind_stack(struct task_struct *task, unsigned long *sp,
  562. unsigned long pc, unsigned long *ra)
  563. {
  564. unsigned long stack_page = 0;
  565. int cpu;
  566. for_each_possible_cpu(cpu) {
  567. if (on_irq_stack(cpu, *sp)) {
  568. stack_page = (unsigned long)irq_stack[cpu];
  569. break;
  570. }
  571. }
  572. if (!stack_page)
  573. stack_page = (unsigned long)task_stack_page(task);
  574. return unwind_stack_by_address(stack_page, sp, pc, ra);
  575. }
  576. #endif
  577. /*
  578. * __get_wchan - a maintenance nightmare^W^Wpain in the ass ...
  579. */
  580. unsigned long __get_wchan(struct task_struct *task)
  581. {
  582. unsigned long pc = 0;
  583. #ifdef CONFIG_KALLSYMS
  584. unsigned long sp;
  585. unsigned long ra = 0;
  586. #endif
  587. if (!task_stack_page(task))
  588. goto out;
  589. pc = thread_saved_pc(task);
  590. #ifdef CONFIG_KALLSYMS
  591. sp = task->thread.reg29 + schedule_mfi.frame_size;
  592. while (in_sched_functions(pc))
  593. pc = unwind_stack(task, &sp, pc, &ra);
  594. #endif
  595. out:
  596. return pc;
  597. }
  598. unsigned long mips_stack_top(void)
  599. {
  600. unsigned long top = TASK_SIZE & PAGE_MASK;
  601. if (IS_ENABLED(CONFIG_MIPS_FP_SUPPORT)) {
  602. /* One page for branch delay slot "emulation" */
  603. top -= PAGE_SIZE;
  604. }
  605. /* Space for the VDSO, data page & GIC user page */
  606. top -= PAGE_ALIGN(current->thread.abi->vdso->size);
  607. top -= PAGE_SIZE;
  608. top -= mips_gic_present() ? PAGE_SIZE : 0;
  609. /* Space for cache colour alignment */
  610. if (cpu_has_dc_aliases)
  611. top -= shm_align_mask + 1;
  612. /* Space to randomize the VDSO base */
  613. if (current->flags & PF_RANDOMIZE)
  614. top -= VDSO_RANDOMIZE_SIZE;
  615. return top;
  616. }
  617. /*
  618. * Don't forget that the stack pointer must be aligned on a 8 bytes
  619. * boundary for 32-bits ABI and 16 bytes for 64-bits ABI.
  620. */
  621. unsigned long arch_align_stack(unsigned long sp)
  622. {
  623. if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
  624. sp -= prandom_u32_max(PAGE_SIZE);
  625. return sp & ALMASK;
  626. }
  627. static struct cpumask backtrace_csd_busy;
  628. static void handle_backtrace(void *info)
  629. {
  630. nmi_cpu_backtrace(get_irq_regs());
  631. cpumask_clear_cpu(smp_processor_id(), &backtrace_csd_busy);
  632. }
  633. static DEFINE_PER_CPU(call_single_data_t, backtrace_csd) =
  634. CSD_INIT(handle_backtrace, NULL);
  635. static void raise_backtrace(cpumask_t *mask)
  636. {
  637. call_single_data_t *csd;
  638. int cpu;
  639. for_each_cpu(cpu, mask) {
  640. /*
  641. * If we previously sent an IPI to the target CPU & it hasn't
  642. * cleared its bit in the busy cpumask then it didn't handle
  643. * our previous IPI & it's not safe for us to reuse the
  644. * call_single_data_t.
  645. */
  646. if (cpumask_test_and_set_cpu(cpu, &backtrace_csd_busy)) {
  647. pr_warn("Unable to send backtrace IPI to CPU%u - perhaps it hung?\n",
  648. cpu);
  649. continue;
  650. }
  651. csd = &per_cpu(backtrace_csd, cpu);
  652. smp_call_function_single_async(cpu, csd);
  653. }
  654. }
  655. void arch_trigger_cpumask_backtrace(const cpumask_t *mask, bool exclude_self)
  656. {
  657. nmi_trigger_cpumask_backtrace(mask, exclude_self, raise_backtrace);
  658. }
  659. int mips_get_process_fp_mode(struct task_struct *task)
  660. {
  661. int value = 0;
  662. if (!test_tsk_thread_flag(task, TIF_32BIT_FPREGS))
  663. value |= PR_FP_MODE_FR;
  664. if (test_tsk_thread_flag(task, TIF_HYBRID_FPREGS))
  665. value |= PR_FP_MODE_FRE;
  666. return value;
  667. }
  668. static long prepare_for_fp_mode_switch(void *unused)
  669. {
  670. /*
  671. * This is icky, but we use this to simply ensure that all CPUs have
  672. * context switched, regardless of whether they were previously running
  673. * kernel or user code. This ensures that no CPU that a mode-switching
  674. * program may execute on keeps its FPU enabled (& in the old mode)
  675. * throughout the mode switch.
  676. */
  677. return 0;
  678. }
  679. int mips_set_process_fp_mode(struct task_struct *task, unsigned int value)
  680. {
  681. const unsigned int known_bits = PR_FP_MODE_FR | PR_FP_MODE_FRE;
  682. struct task_struct *t;
  683. struct cpumask process_cpus;
  684. int cpu;
  685. /* If nothing to change, return right away, successfully. */
  686. if (value == mips_get_process_fp_mode(task))
  687. return 0;
  688. /* Only accept a mode change if 64-bit FP enabled for o32. */
  689. if (!IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT))
  690. return -EOPNOTSUPP;
  691. /* And only for o32 tasks. */
  692. if (IS_ENABLED(CONFIG_64BIT) && !test_thread_flag(TIF_32BIT_REGS))
  693. return -EOPNOTSUPP;
  694. /* Check the value is valid */
  695. if (value & ~known_bits)
  696. return -EOPNOTSUPP;
  697. /* Setting FRE without FR is not supported. */
  698. if ((value & (PR_FP_MODE_FR | PR_FP_MODE_FRE)) == PR_FP_MODE_FRE)
  699. return -EOPNOTSUPP;
  700. /* Avoid inadvertently triggering emulation */
  701. if ((value & PR_FP_MODE_FR) && raw_cpu_has_fpu &&
  702. !(raw_current_cpu_data.fpu_id & MIPS_FPIR_F64))
  703. return -EOPNOTSUPP;
  704. if ((value & PR_FP_MODE_FRE) && raw_cpu_has_fpu && !cpu_has_fre)
  705. return -EOPNOTSUPP;
  706. /* FR = 0 not supported in MIPS R6 */
  707. if (!(value & PR_FP_MODE_FR) && raw_cpu_has_fpu && cpu_has_mips_r6)
  708. return -EOPNOTSUPP;
  709. /* Indicate the new FP mode in each thread */
  710. for_each_thread(task, t) {
  711. /* Update desired FP register width */
  712. if (value & PR_FP_MODE_FR) {
  713. clear_tsk_thread_flag(t, TIF_32BIT_FPREGS);
  714. } else {
  715. set_tsk_thread_flag(t, TIF_32BIT_FPREGS);
  716. clear_tsk_thread_flag(t, TIF_MSA_CTX_LIVE);
  717. }
  718. /* Update desired FP single layout */
  719. if (value & PR_FP_MODE_FRE)
  720. set_tsk_thread_flag(t, TIF_HYBRID_FPREGS);
  721. else
  722. clear_tsk_thread_flag(t, TIF_HYBRID_FPREGS);
  723. }
  724. /*
  725. * We need to ensure that all threads in the process have switched mode
  726. * before returning, in order to allow userland to not worry about
  727. * races. We can do this by forcing all CPUs that any thread in the
  728. * process may be running on to schedule something else - in this case
  729. * prepare_for_fp_mode_switch().
  730. *
  731. * We begin by generating a mask of all CPUs that any thread in the
  732. * process may be running on.
  733. */
  734. cpumask_clear(&process_cpus);
  735. for_each_thread(task, t)
  736. cpumask_set_cpu(task_cpu(t), &process_cpus);
  737. /*
  738. * Now we schedule prepare_for_fp_mode_switch() on each of those CPUs.
  739. *
  740. * The CPUs may have rescheduled already since we switched mode or
  741. * generated the cpumask, but that doesn't matter. If the task in this
  742. * process is scheduled out then our scheduling
  743. * prepare_for_fp_mode_switch() will simply be redundant. If it's
  744. * scheduled in then it will already have picked up the new FP mode
  745. * whilst doing so.
  746. */
  747. cpus_read_lock();
  748. for_each_cpu_and(cpu, &process_cpus, cpu_online_mask)
  749. work_on_cpu(cpu, prepare_for_fp_mode_switch, NULL);
  750. cpus_read_unlock();
  751. return 0;
  752. }
  753. #if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32)
  754. void mips_dump_regs32(u32 *uregs, const struct pt_regs *regs)
  755. {
  756. unsigned int i;
  757. for (i = MIPS32_EF_R1; i <= MIPS32_EF_R31; i++) {
  758. /* k0/k1 are copied as zero. */
  759. if (i == MIPS32_EF_R26 || i == MIPS32_EF_R27)
  760. uregs[i] = 0;
  761. else
  762. uregs[i] = regs->regs[i - MIPS32_EF_R0];
  763. }
  764. uregs[MIPS32_EF_LO] = regs->lo;
  765. uregs[MIPS32_EF_HI] = regs->hi;
  766. uregs[MIPS32_EF_CP0_EPC] = regs->cp0_epc;
  767. uregs[MIPS32_EF_CP0_BADVADDR] = regs->cp0_badvaddr;
  768. uregs[MIPS32_EF_CP0_STATUS] = regs->cp0_status;
  769. uregs[MIPS32_EF_CP0_CAUSE] = regs->cp0_cause;
  770. }
  771. #endif /* CONFIG_32BIT || CONFIG_MIPS32_O32 */
  772. #ifdef CONFIG_64BIT
  773. void mips_dump_regs64(u64 *uregs, const struct pt_regs *regs)
  774. {
  775. unsigned int i;
  776. for (i = MIPS64_EF_R1; i <= MIPS64_EF_R31; i++) {
  777. /* k0/k1 are copied as zero. */
  778. if (i == MIPS64_EF_R26 || i == MIPS64_EF_R27)
  779. uregs[i] = 0;
  780. else
  781. uregs[i] = regs->regs[i - MIPS64_EF_R0];
  782. }
  783. uregs[MIPS64_EF_LO] = regs->lo;
  784. uregs[MIPS64_EF_HI] = regs->hi;
  785. uregs[MIPS64_EF_CP0_EPC] = regs->cp0_epc;
  786. uregs[MIPS64_EF_CP0_BADVADDR] = regs->cp0_badvaddr;
  787. uregs[MIPS64_EF_CP0_STATUS] = regs->cp0_status;
  788. uregs[MIPS64_EF_CP0_CAUSE] = regs->cp0_cause;
  789. }
  790. #endif /* CONFIG_64BIT */