mips-mt.c 5.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * General MIPS MT support routines, usable in AP/SP and SMVP.
  4. * Copyright (C) 2005 Mips Technologies, Inc
  5. */
  6. #include <linux/device.h>
  7. #include <linux/kernel.h>
  8. #include <linux/sched.h>
  9. #include <linux/export.h>
  10. #include <linux/interrupt.h>
  11. #include <linux/security.h>
  12. #include <asm/cpu.h>
  13. #include <asm/processor.h>
  14. #include <linux/atomic.h>
  15. #include <asm/hardirq.h>
  16. #include <asm/mmu_context.h>
  17. #include <asm/mipsmtregs.h>
  18. #include <asm/r4kcache.h>
  19. #include <asm/cacheflush.h>
  20. int vpelimit;
  21. static int __init maxvpes(char *str)
  22. {
  23. get_option(&str, &vpelimit);
  24. return 1;
  25. }
  26. __setup("maxvpes=", maxvpes);
  27. int tclimit;
  28. static int __init maxtcs(char *str)
  29. {
  30. get_option(&str, &tclimit);
  31. return 1;
  32. }
  33. __setup("maxtcs=", maxtcs);
  34. /*
  35. * Dump new MIPS MT state for the core. Does not leave TCs halted.
  36. * Takes an argument which taken to be a pre-call MVPControl value.
  37. */
  38. void mips_mt_regdump(unsigned long mvpctl)
  39. {
  40. unsigned long flags;
  41. unsigned long vpflags;
  42. unsigned long mvpconf0;
  43. int nvpe;
  44. int ntc;
  45. int i;
  46. int tc;
  47. unsigned long haltval;
  48. unsigned long tcstatval;
  49. local_irq_save(flags);
  50. vpflags = dvpe();
  51. printk("=== MIPS MT State Dump ===\n");
  52. printk("-- Global State --\n");
  53. printk(" MVPControl Passed: %08lx\n", mvpctl);
  54. printk(" MVPControl Read: %08lx\n", vpflags);
  55. printk(" MVPConf0 : %08lx\n", (mvpconf0 = read_c0_mvpconf0()));
  56. nvpe = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
  57. ntc = ((mvpconf0 & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1;
  58. printk("-- per-VPE State --\n");
  59. for (i = 0; i < nvpe; i++) {
  60. for (tc = 0; tc < ntc; tc++) {
  61. settc(tc);
  62. if ((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) {
  63. printk(" VPE %d\n", i);
  64. printk(" VPEControl : %08lx\n",
  65. read_vpe_c0_vpecontrol());
  66. printk(" VPEConf0 : %08lx\n",
  67. read_vpe_c0_vpeconf0());
  68. printk(" VPE%d.Status : %08lx\n",
  69. i, read_vpe_c0_status());
  70. printk(" VPE%d.EPC : %08lx %pS\n",
  71. i, read_vpe_c0_epc(),
  72. (void *) read_vpe_c0_epc());
  73. printk(" VPE%d.Cause : %08lx\n",
  74. i, read_vpe_c0_cause());
  75. printk(" VPE%d.Config7 : %08lx\n",
  76. i, read_vpe_c0_config7());
  77. break; /* Next VPE */
  78. }
  79. }
  80. }
  81. printk("-- per-TC State --\n");
  82. for (tc = 0; tc < ntc; tc++) {
  83. settc(tc);
  84. if (read_tc_c0_tcbind() == read_c0_tcbind()) {
  85. /* Are we dumping ourself? */
  86. haltval = 0; /* Then we're not halted, and mustn't be */
  87. tcstatval = flags; /* And pre-dump TCStatus is flags */
  88. printk(" TC %d (current TC with VPE EPC above)\n", tc);
  89. } else {
  90. haltval = read_tc_c0_tchalt();
  91. write_tc_c0_tchalt(1);
  92. tcstatval = read_tc_c0_tcstatus();
  93. printk(" TC %d\n", tc);
  94. }
  95. printk(" TCStatus : %08lx\n", tcstatval);
  96. printk(" TCBind : %08lx\n", read_tc_c0_tcbind());
  97. printk(" TCRestart : %08lx %pS\n",
  98. read_tc_c0_tcrestart(), (void *) read_tc_c0_tcrestart());
  99. printk(" TCHalt : %08lx\n", haltval);
  100. printk(" TCContext : %08lx\n", read_tc_c0_tccontext());
  101. if (!haltval)
  102. write_tc_c0_tchalt(0);
  103. }
  104. printk("===========================\n");
  105. evpe(vpflags);
  106. local_irq_restore(flags);
  107. }
  108. static int mt_opt_rpsctl = -1;
  109. static int mt_opt_nblsu = -1;
  110. static int mt_opt_forceconfig7;
  111. static int mt_opt_config7 = -1;
  112. static int __init rpsctl_set(char *str)
  113. {
  114. get_option(&str, &mt_opt_rpsctl);
  115. return 1;
  116. }
  117. __setup("rpsctl=", rpsctl_set);
  118. static int __init nblsu_set(char *str)
  119. {
  120. get_option(&str, &mt_opt_nblsu);
  121. return 1;
  122. }
  123. __setup("nblsu=", nblsu_set);
  124. static int __init config7_set(char *str)
  125. {
  126. get_option(&str, &mt_opt_config7);
  127. mt_opt_forceconfig7 = 1;
  128. return 1;
  129. }
  130. __setup("config7=", config7_set);
  131. static unsigned int itc_base;
  132. static int __init set_itc_base(char *str)
  133. {
  134. get_option(&str, &itc_base);
  135. return 1;
  136. }
  137. __setup("itcbase=", set_itc_base);
  138. void mips_mt_set_cpuoptions(void)
  139. {
  140. unsigned int oconfig7 = read_c0_config7();
  141. unsigned int nconfig7 = oconfig7;
  142. if (mt_opt_rpsctl >= 0) {
  143. printk("34K return prediction stack override set to %d.\n",
  144. mt_opt_rpsctl);
  145. if (mt_opt_rpsctl)
  146. nconfig7 |= (1 << 2);
  147. else
  148. nconfig7 &= ~(1 << 2);
  149. }
  150. if (mt_opt_nblsu >= 0) {
  151. printk("34K ALU/LSU sync override set to %d.\n", mt_opt_nblsu);
  152. if (mt_opt_nblsu)
  153. nconfig7 |= (1 << 5);
  154. else
  155. nconfig7 &= ~(1 << 5);
  156. }
  157. if (mt_opt_forceconfig7) {
  158. printk("CP0.Config7 forced to 0x%08x.\n", mt_opt_config7);
  159. nconfig7 = mt_opt_config7;
  160. }
  161. if (oconfig7 != nconfig7) {
  162. __asm__ __volatile("sync");
  163. write_c0_config7(nconfig7);
  164. ehb();
  165. printk("Config7: 0x%08x\n", read_c0_config7());
  166. }
  167. if (itc_base != 0) {
  168. /*
  169. * Configure ITC mapping. This code is very
  170. * specific to the 34K core family, which uses
  171. * a special mode bit ("ITC") in the ErrCtl
  172. * register to enable access to ITC control
  173. * registers via cache "tag" operations.
  174. */
  175. unsigned long ectlval;
  176. unsigned long itcblkgrn;
  177. /* ErrCtl register is known as "ecc" to Linux */
  178. ectlval = read_c0_ecc();
  179. write_c0_ecc(ectlval | (0x1 << 26));
  180. ehb();
  181. #define INDEX_0 (0x80000000)
  182. #define INDEX_8 (0x80000008)
  183. /* Read "cache tag" for Dcache pseudo-index 8 */
  184. cache_op(Index_Load_Tag_D, INDEX_8);
  185. ehb();
  186. itcblkgrn = read_c0_dtaglo();
  187. itcblkgrn &= 0xfffe0000;
  188. /* Set for 128 byte pitch of ITC cells */
  189. itcblkgrn |= 0x00000c00;
  190. /* Stage in Tag register */
  191. write_c0_dtaglo(itcblkgrn);
  192. ehb();
  193. /* Write out to ITU with CACHE op */
  194. cache_op(Index_Store_Tag_D, INDEX_8);
  195. /* Now set base address, and turn ITC on with 0x1 bit */
  196. write_c0_dtaglo((itc_base & 0xfffffc00) | 0x1 );
  197. ehb();
  198. /* Write out to ITU with CACHE op */
  199. cache_op(Index_Store_Tag_D, INDEX_0);
  200. write_c0_ecc(ectlval);
  201. ehb();
  202. printk("Mapped %ld ITC cells starting at 0x%08x\n",
  203. ((itcblkgrn & 0x7fe00000) >> 20), itc_base);
  204. }
  205. }
  206. struct class *mt_class;
  207. static int __init mips_mt_init(void)
  208. {
  209. struct class *mtc;
  210. mtc = class_create(THIS_MODULE, "mt");
  211. if (IS_ERR(mtc))
  212. return PTR_ERR(mtc);
  213. mt_class = mtc;
  214. return 0;
  215. }
  216. subsys_initcall(mips_mt_init);