mips-cm.c 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515
  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Copyright (C) 2013 Imagination Technologies
  4. * Author: Paul Burton <[email protected]>
  5. */
  6. #include <linux/errno.h>
  7. #include <linux/percpu.h>
  8. #include <linux/spinlock.h>
  9. #include <asm/mips-cps.h>
  10. #include <asm/mipsregs.h>
  11. void __iomem *mips_gcr_base;
  12. void __iomem *mips_cm_l2sync_base;
  13. int mips_cm_is64;
  14. static char *cm2_tr[8] = {
  15. "mem", "gcr", "gic", "mmio",
  16. "0x04", "cpc", "0x06", "0x07"
  17. };
  18. /* CM3 Tag ECC transaction type */
  19. static char *cm3_tr[16] = {
  20. [0x0] = "ReqNoData",
  21. [0x1] = "0x1",
  22. [0x2] = "ReqWData",
  23. [0x3] = "0x3",
  24. [0x4] = "IReqNoResp",
  25. [0x5] = "IReqWResp",
  26. [0x6] = "IReqNoRespDat",
  27. [0x7] = "IReqWRespDat",
  28. [0x8] = "RespNoData",
  29. [0x9] = "RespDataFol",
  30. [0xa] = "RespWData",
  31. [0xb] = "RespDataOnly",
  32. [0xc] = "IRespNoData",
  33. [0xd] = "IRespDataFol",
  34. [0xe] = "IRespWData",
  35. [0xf] = "IRespDataOnly"
  36. };
  37. static char *cm2_cmd[32] = {
  38. [0x00] = "0x00",
  39. [0x01] = "Legacy Write",
  40. [0x02] = "Legacy Read",
  41. [0x03] = "0x03",
  42. [0x04] = "0x04",
  43. [0x05] = "0x05",
  44. [0x06] = "0x06",
  45. [0x07] = "0x07",
  46. [0x08] = "Coherent Read Own",
  47. [0x09] = "Coherent Read Share",
  48. [0x0a] = "Coherent Read Discard",
  49. [0x0b] = "Coherent Ready Share Always",
  50. [0x0c] = "Coherent Upgrade",
  51. [0x0d] = "Coherent Writeback",
  52. [0x0e] = "0x0e",
  53. [0x0f] = "0x0f",
  54. [0x10] = "Coherent Copyback",
  55. [0x11] = "Coherent Copyback Invalidate",
  56. [0x12] = "Coherent Invalidate",
  57. [0x13] = "Coherent Write Invalidate",
  58. [0x14] = "Coherent Completion Sync",
  59. [0x15] = "0x15",
  60. [0x16] = "0x16",
  61. [0x17] = "0x17",
  62. [0x18] = "0x18",
  63. [0x19] = "0x19",
  64. [0x1a] = "0x1a",
  65. [0x1b] = "0x1b",
  66. [0x1c] = "0x1c",
  67. [0x1d] = "0x1d",
  68. [0x1e] = "0x1e",
  69. [0x1f] = "0x1f"
  70. };
  71. /* CM3 Tag ECC command type */
  72. static char *cm3_cmd[16] = {
  73. [0x0] = "Legacy Read",
  74. [0x1] = "Legacy Write",
  75. [0x2] = "Coherent Read Own",
  76. [0x3] = "Coherent Read Share",
  77. [0x4] = "Coherent Read Discard",
  78. [0x5] = "Coherent Evicted",
  79. [0x6] = "Coherent Upgrade",
  80. [0x7] = "Coherent Upgrade for Store Conditional",
  81. [0x8] = "Coherent Writeback",
  82. [0x9] = "Coherent Write Invalidate",
  83. [0xa] = "0xa",
  84. [0xb] = "0xb",
  85. [0xc] = "0xc",
  86. [0xd] = "0xd",
  87. [0xe] = "0xe",
  88. [0xf] = "0xf"
  89. };
  90. /* CM3 Tag ECC command group */
  91. static char *cm3_cmd_group[8] = {
  92. [0x0] = "Normal",
  93. [0x1] = "Registers",
  94. [0x2] = "TLB",
  95. [0x3] = "0x3",
  96. [0x4] = "L1I",
  97. [0x5] = "L1D",
  98. [0x6] = "L3",
  99. [0x7] = "L2"
  100. };
  101. static char *cm2_core[8] = {
  102. "Invalid/OK", "Invalid/Data",
  103. "Shared/OK", "Shared/Data",
  104. "Modified/OK", "Modified/Data",
  105. "Exclusive/OK", "Exclusive/Data"
  106. };
  107. static char *cm2_l2_type[4] = {
  108. [0x0] = "None",
  109. [0x1] = "Tag RAM single/double ECC error",
  110. [0x2] = "Data RAM single/double ECC error",
  111. [0x3] = "WS RAM uncorrectable dirty parity"
  112. };
  113. static char *cm2_l2_instr[32] = {
  114. [0x00] = "L2_NOP",
  115. [0x01] = "L2_ERR_CORR",
  116. [0x02] = "L2_TAG_INV",
  117. [0x03] = "L2_WS_CLEAN",
  118. [0x04] = "L2_RD_MDYFY_WR",
  119. [0x05] = "L2_WS_MRU",
  120. [0x06] = "L2_EVICT_LN2",
  121. [0x07] = "0x07",
  122. [0x08] = "L2_EVICT",
  123. [0x09] = "L2_REFL",
  124. [0x0a] = "L2_RD",
  125. [0x0b] = "L2_WR",
  126. [0x0c] = "L2_EVICT_MRU",
  127. [0x0d] = "L2_SYNC",
  128. [0x0e] = "L2_REFL_ERR",
  129. [0x0f] = "0x0f",
  130. [0x10] = "L2_INDX_WB_INV",
  131. [0x11] = "L2_INDX_LD_TAG",
  132. [0x12] = "L2_INDX_ST_TAG",
  133. [0x13] = "L2_INDX_ST_DATA",
  134. [0x14] = "L2_INDX_ST_ECC",
  135. [0x15] = "0x15",
  136. [0x16] = "0x16",
  137. [0x17] = "0x17",
  138. [0x18] = "L2_FTCH_AND_LCK",
  139. [0x19] = "L2_HIT_INV",
  140. [0x1a] = "L2_HIT_WB_INV",
  141. [0x1b] = "L2_HIT_WB",
  142. [0x1c] = "0x1c",
  143. [0x1d] = "0x1d",
  144. [0x1e] = "0x1e",
  145. [0x1f] = "0x1f"
  146. };
  147. static char *cm2_causes[32] = {
  148. "None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR",
  149. "COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07",
  150. "0x08", "0x09", "0x0a", "0x0b",
  151. "0x0c", "0x0d", "0x0e", "0x0f",
  152. "0x10", "INTVN_WR_ERR", "INTVN_RD_ERR", "0x13",
  153. "0x14", "0x15", "0x16", "0x17",
  154. "L2_RD_UNCORR", "L2_WR_UNCORR", "L2_CORR", "0x1b",
  155. "0x1c", "0x1d", "0x1e", "0x1f"
  156. };
  157. static char *cm3_causes[32] = {
  158. "0x0", "MP_CORRECTABLE_ECC_ERR", "MP_REQUEST_DECODE_ERR",
  159. "MP_UNCORRECTABLE_ECC_ERR", "MP_PARITY_ERR", "MP_COHERENCE_ERR",
  160. "CMBIU_REQUEST_DECODE_ERR", "CMBIU_PARITY_ERR", "CMBIU_AXI_RESP_ERR",
  161. "0x9", "RBI_BUS_ERR", "0xb", "0xc", "0xd", "0xe", "0xf", "0x10",
  162. "0x11", "0x12", "0x13", "0x14", "0x15", "0x16", "0x17", "0x18",
  163. "0x19", "0x1a", "0x1b", "0x1c", "0x1d", "0x1e", "0x1f"
  164. };
  165. static DEFINE_PER_CPU_ALIGNED(spinlock_t, cm_core_lock);
  166. static DEFINE_PER_CPU_ALIGNED(unsigned long, cm_core_lock_flags);
  167. phys_addr_t __mips_cm_phys_base(void)
  168. {
  169. u32 config3 = read_c0_config3();
  170. unsigned long cmgcr;
  171. /* Check the CMGCRBase register is implemented */
  172. if (!(config3 & MIPS_CONF3_CMGCR))
  173. return 0;
  174. /* Read the address from CMGCRBase */
  175. cmgcr = read_c0_cmgcrbase();
  176. return (cmgcr & MIPS_CMGCRF_BASE) << (36 - 32);
  177. }
  178. phys_addr_t mips_cm_phys_base(void)
  179. __attribute__((weak, alias("__mips_cm_phys_base")));
  180. phys_addr_t __mips_cm_l2sync_phys_base(void)
  181. {
  182. u32 base_reg;
  183. /*
  184. * If the L2-only sync region is already enabled then leave it at it's
  185. * current location.
  186. */
  187. base_reg = read_gcr_l2_only_sync_base();
  188. if (base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN)
  189. return base_reg & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE;
  190. /* Default to following the CM */
  191. return mips_cm_phys_base() + MIPS_CM_GCR_SIZE;
  192. }
  193. phys_addr_t mips_cm_l2sync_phys_base(void)
  194. __attribute__((weak, alias("__mips_cm_l2sync_phys_base")));
  195. static void mips_cm_probe_l2sync(void)
  196. {
  197. unsigned major_rev;
  198. phys_addr_t addr;
  199. /* L2-only sync was introduced with CM major revision 6 */
  200. major_rev = FIELD_GET(CM_GCR_REV_MAJOR, read_gcr_rev());
  201. if (major_rev < 6)
  202. return;
  203. /* Find a location for the L2 sync region */
  204. addr = mips_cm_l2sync_phys_base();
  205. BUG_ON((addr & CM_GCR_L2_ONLY_SYNC_BASE_SYNCBASE) != addr);
  206. if (!addr)
  207. return;
  208. /* Set the region base address & enable it */
  209. write_gcr_l2_only_sync_base(addr | CM_GCR_L2_ONLY_SYNC_BASE_SYNCEN);
  210. /* Map the region */
  211. mips_cm_l2sync_base = ioremap(addr, MIPS_CM_L2SYNC_SIZE);
  212. }
  213. int mips_cm_probe(void)
  214. {
  215. phys_addr_t addr;
  216. u32 base_reg;
  217. unsigned cpu;
  218. /*
  219. * No need to probe again if we have already been
  220. * here before.
  221. */
  222. if (mips_gcr_base)
  223. return 0;
  224. addr = mips_cm_phys_base();
  225. BUG_ON((addr & CM_GCR_BASE_GCRBASE) != addr);
  226. if (!addr)
  227. return -ENODEV;
  228. mips_gcr_base = ioremap(addr, MIPS_CM_GCR_SIZE);
  229. if (!mips_gcr_base)
  230. return -ENXIO;
  231. /* sanity check that we're looking at a CM */
  232. base_reg = read_gcr_base();
  233. if ((base_reg & CM_GCR_BASE_GCRBASE) != addr) {
  234. pr_err("GCRs appear to have been moved (expected them at 0x%08lx)!\n",
  235. (unsigned long)addr);
  236. iounmap(mips_gcr_base);
  237. mips_gcr_base = NULL;
  238. return -ENODEV;
  239. }
  240. /* set default target to memory */
  241. change_gcr_base(CM_GCR_BASE_CMDEFTGT, CM_GCR_BASE_CMDEFTGT_MEM);
  242. /* disable CM regions */
  243. write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR);
  244. write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK);
  245. write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR);
  246. write_gcr_reg1_mask(CM_GCR_REGn_MASK_ADDRMASK);
  247. write_gcr_reg2_base(CM_GCR_REGn_BASE_BASEADDR);
  248. write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK);
  249. write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR);
  250. write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK);
  251. /* probe for an L2-only sync region */
  252. mips_cm_probe_l2sync();
  253. /* determine register width for this CM */
  254. mips_cm_is64 = IS_ENABLED(CONFIG_64BIT) && (mips_cm_revision() >= CM_REV_CM3);
  255. for_each_possible_cpu(cpu)
  256. spin_lock_init(&per_cpu(cm_core_lock, cpu));
  257. return 0;
  258. }
  259. void mips_cm_lock_other(unsigned int cluster, unsigned int core,
  260. unsigned int vp, unsigned int block)
  261. {
  262. unsigned int curr_core, cm_rev;
  263. u32 val;
  264. cm_rev = mips_cm_revision();
  265. preempt_disable();
  266. if (cm_rev >= CM_REV_CM3) {
  267. val = FIELD_PREP(CM3_GCR_Cx_OTHER_CORE, core) |
  268. FIELD_PREP(CM3_GCR_Cx_OTHER_VP, vp);
  269. if (cm_rev >= CM_REV_CM3_5) {
  270. val |= CM_GCR_Cx_OTHER_CLUSTER_EN;
  271. val |= FIELD_PREP(CM_GCR_Cx_OTHER_CLUSTER, cluster);
  272. val |= FIELD_PREP(CM_GCR_Cx_OTHER_BLOCK, block);
  273. } else {
  274. WARN_ON(cluster != 0);
  275. WARN_ON(block != CM_GCR_Cx_OTHER_BLOCK_LOCAL);
  276. }
  277. /*
  278. * We need to disable interrupts in SMP systems in order to
  279. * ensure that we don't interrupt the caller with code which
  280. * may modify the redirect register. We do so here in a
  281. * slightly obscure way by using a spin lock, since this has
  282. * the neat property of also catching any nested uses of
  283. * mips_cm_lock_other() leading to a deadlock or a nice warning
  284. * with lockdep enabled.
  285. */
  286. spin_lock_irqsave(this_cpu_ptr(&cm_core_lock),
  287. *this_cpu_ptr(&cm_core_lock_flags));
  288. } else {
  289. WARN_ON(cluster != 0);
  290. WARN_ON(block != CM_GCR_Cx_OTHER_BLOCK_LOCAL);
  291. /*
  292. * We only have a GCR_CL_OTHER per core in systems with
  293. * CM 2.5 & older, so have to ensure other VP(E)s don't
  294. * race with us.
  295. */
  296. curr_core = cpu_core(&current_cpu_data);
  297. spin_lock_irqsave(&per_cpu(cm_core_lock, curr_core),
  298. per_cpu(cm_core_lock_flags, curr_core));
  299. val = FIELD_PREP(CM_GCR_Cx_OTHER_CORENUM, core);
  300. }
  301. write_gcr_cl_other(val);
  302. /*
  303. * Ensure the core-other region reflects the appropriate core &
  304. * VP before any accesses to it occur.
  305. */
  306. mb();
  307. }
  308. void mips_cm_unlock_other(void)
  309. {
  310. unsigned int curr_core;
  311. if (mips_cm_revision() < CM_REV_CM3) {
  312. curr_core = cpu_core(&current_cpu_data);
  313. spin_unlock_irqrestore(&per_cpu(cm_core_lock, curr_core),
  314. per_cpu(cm_core_lock_flags, curr_core));
  315. } else {
  316. spin_unlock_irqrestore(this_cpu_ptr(&cm_core_lock),
  317. *this_cpu_ptr(&cm_core_lock_flags));
  318. }
  319. preempt_enable();
  320. }
  321. void mips_cm_error_report(void)
  322. {
  323. u64 cm_error, cm_addr, cm_other;
  324. unsigned long revision;
  325. int ocause, cause;
  326. char buf[256];
  327. if (!mips_cm_present())
  328. return;
  329. revision = mips_cm_revision();
  330. cm_error = read_gcr_error_cause();
  331. cm_addr = read_gcr_error_addr();
  332. cm_other = read_gcr_error_mult();
  333. if (revision < CM_REV_CM3) { /* CM2 */
  334. cause = FIELD_GET(CM_GCR_ERROR_CAUSE_ERRTYPE, cm_error);
  335. ocause = FIELD_GET(CM_GCR_ERROR_MULT_ERR2ND, cm_other);
  336. if (!cause)
  337. return;
  338. if (cause < 16) {
  339. unsigned long cca_bits = (cm_error >> 15) & 7;
  340. unsigned long tr_bits = (cm_error >> 12) & 7;
  341. unsigned long cmd_bits = (cm_error >> 7) & 0x1f;
  342. unsigned long stag_bits = (cm_error >> 3) & 15;
  343. unsigned long sport_bits = (cm_error >> 0) & 7;
  344. snprintf(buf, sizeof(buf),
  345. "CCA=%lu TR=%s MCmd=%s STag=%lu "
  346. "SPort=%lu\n", cca_bits, cm2_tr[tr_bits],
  347. cm2_cmd[cmd_bits], stag_bits, sport_bits);
  348. } else if (cause < 24) {
  349. /* glob state & sresp together */
  350. unsigned long c3_bits = (cm_error >> 18) & 7;
  351. unsigned long c2_bits = (cm_error >> 15) & 7;
  352. unsigned long c1_bits = (cm_error >> 12) & 7;
  353. unsigned long c0_bits = (cm_error >> 9) & 7;
  354. unsigned long sc_bit = (cm_error >> 8) & 1;
  355. unsigned long cmd_bits = (cm_error >> 3) & 0x1f;
  356. unsigned long sport_bits = (cm_error >> 0) & 7;
  357. snprintf(buf, sizeof(buf),
  358. "C3=%s C2=%s C1=%s C0=%s SC=%s "
  359. "MCmd=%s SPort=%lu\n",
  360. cm2_core[c3_bits], cm2_core[c2_bits],
  361. cm2_core[c1_bits], cm2_core[c0_bits],
  362. sc_bit ? "True" : "False",
  363. cm2_cmd[cmd_bits], sport_bits);
  364. } else {
  365. unsigned long muc_bit = (cm_error >> 23) & 1;
  366. unsigned long ins_bits = (cm_error >> 18) & 0x1f;
  367. unsigned long arr_bits = (cm_error >> 16) & 3;
  368. unsigned long dw_bits = (cm_error >> 12) & 15;
  369. unsigned long way_bits = (cm_error >> 9) & 7;
  370. unsigned long mway_bit = (cm_error >> 8) & 1;
  371. unsigned long syn_bits = (cm_error >> 0) & 0xFF;
  372. snprintf(buf, sizeof(buf),
  373. "Type=%s%s Instr=%s DW=%lu Way=%lu "
  374. "MWay=%s Syndrome=0x%02lx",
  375. muc_bit ? "Multi-UC " : "",
  376. cm2_l2_type[arr_bits],
  377. cm2_l2_instr[ins_bits], dw_bits, way_bits,
  378. mway_bit ? "True" : "False", syn_bits);
  379. }
  380. pr_err("CM_ERROR=%08llx %s <%s>\n", cm_error,
  381. cm2_causes[cause], buf);
  382. pr_err("CM_ADDR =%08llx\n", cm_addr);
  383. pr_err("CM_OTHER=%08llx %s\n", cm_other, cm2_causes[ocause]);
  384. } else { /* CM3 */
  385. ulong core_id_bits, vp_id_bits, cmd_bits, cmd_group_bits;
  386. ulong cm3_cca_bits, mcp_bits, cm3_tr_bits, sched_bit;
  387. cause = FIELD_GET(CM3_GCR_ERROR_CAUSE_ERRTYPE, cm_error);
  388. ocause = FIELD_GET(CM_GCR_ERROR_MULT_ERR2ND, cm_other);
  389. if (!cause)
  390. return;
  391. /* Used by cause == {1,2,3} */
  392. core_id_bits = (cm_error >> 22) & 0xf;
  393. vp_id_bits = (cm_error >> 18) & 0xf;
  394. cmd_bits = (cm_error >> 14) & 0xf;
  395. cmd_group_bits = (cm_error >> 11) & 0xf;
  396. cm3_cca_bits = (cm_error >> 8) & 7;
  397. mcp_bits = (cm_error >> 5) & 0xf;
  398. cm3_tr_bits = (cm_error >> 1) & 0xf;
  399. sched_bit = cm_error & 0x1;
  400. if (cause == 1 || cause == 3) { /* Tag ECC */
  401. unsigned long tag_ecc = (cm_error >> 57) & 0x1;
  402. unsigned long tag_way_bits = (cm_error >> 29) & 0xffff;
  403. unsigned long dword_bits = (cm_error >> 49) & 0xff;
  404. unsigned long data_way_bits = (cm_error >> 45) & 0xf;
  405. unsigned long data_sets_bits = (cm_error >> 29) & 0xfff;
  406. unsigned long bank_bit = (cm_error >> 28) & 0x1;
  407. snprintf(buf, sizeof(buf),
  408. "%s ECC Error: Way=%lu (DWORD=%lu, Sets=%lu)"
  409. "Bank=%lu CoreID=%lu VPID=%lu Command=%s"
  410. "Command Group=%s CCA=%lu MCP=%d"
  411. "Transaction type=%s Scheduler=%lu\n",
  412. tag_ecc ? "TAG" : "DATA",
  413. tag_ecc ? (unsigned long)ffs(tag_way_bits) - 1 :
  414. data_way_bits, bank_bit, dword_bits,
  415. data_sets_bits,
  416. core_id_bits, vp_id_bits,
  417. cm3_cmd[cmd_bits],
  418. cm3_cmd_group[cmd_group_bits],
  419. cm3_cca_bits, 1 << mcp_bits,
  420. cm3_tr[cm3_tr_bits], sched_bit);
  421. } else if (cause == 2) {
  422. unsigned long data_error_type = (cm_error >> 41) & 0xfff;
  423. unsigned long data_decode_cmd = (cm_error >> 37) & 0xf;
  424. unsigned long data_decode_group = (cm_error >> 34) & 0x7;
  425. unsigned long data_decode_destination_id = (cm_error >> 28) & 0x3f;
  426. snprintf(buf, sizeof(buf),
  427. "Decode Request Error: Type=%lu, Command=%lu"
  428. "Command Group=%lu Destination ID=%lu"
  429. "CoreID=%lu VPID=%lu Command=%s"
  430. "Command Group=%s CCA=%lu MCP=%d"
  431. "Transaction type=%s Scheduler=%lu\n",
  432. data_error_type, data_decode_cmd,
  433. data_decode_group, data_decode_destination_id,
  434. core_id_bits, vp_id_bits,
  435. cm3_cmd[cmd_bits],
  436. cm3_cmd_group[cmd_group_bits],
  437. cm3_cca_bits, 1 << mcp_bits,
  438. cm3_tr[cm3_tr_bits], sched_bit);
  439. } else {
  440. buf[0] = 0;
  441. }
  442. pr_err("CM_ERROR=%llx %s <%s>\n", cm_error,
  443. cm3_causes[cause], buf);
  444. pr_err("CM_ADDR =%llx\n", cm_addr);
  445. pr_err("CM_OTHER=%llx %s\n", cm_other, cm3_causes[ocause]);
  446. }
  447. /* reprime cause register */
  448. write_gcr_error_cause(cm_error);
  449. }