branch.c 21 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 1996, 97, 2000, 2001 by Ralf Baechle
  7. * Copyright (C) 2001 MIPS Technologies, Inc.
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/sched/signal.h>
  11. #include <linux/signal.h>
  12. #include <linux/export.h>
  13. #include <asm/branch.h>
  14. #include <asm/cpu.h>
  15. #include <asm/cpu-features.h>
  16. #include <asm/fpu.h>
  17. #include <asm/fpu_emulator.h>
  18. #include <asm/inst.h>
  19. #include <asm/mips-r2-to-r6-emul.h>
  20. #include <asm/ptrace.h>
  21. #include <linux/uaccess.h>
  22. #include "probes-common.h"
  23. /*
  24. * Calculate and return exception PC in case of branch delay slot
  25. * for microMIPS and MIPS16e. It does not clear the ISA mode bit.
  26. */
  27. int __isa_exception_epc(struct pt_regs *regs)
  28. {
  29. unsigned short inst;
  30. long epc = regs->cp0_epc;
  31. /* Calculate exception PC in branch delay slot. */
  32. if (__get_user(inst, (u16 __user *) msk_isa16_mode(epc))) {
  33. /* This should never happen because delay slot was checked. */
  34. force_sig(SIGSEGV);
  35. return epc;
  36. }
  37. if (cpu_has_mips16) {
  38. union mips16e_instruction inst_mips16e;
  39. inst_mips16e.full = inst;
  40. if (inst_mips16e.ri.opcode == MIPS16e_jal_op)
  41. epc += 4;
  42. else
  43. epc += 2;
  44. } else if (mm_insn_16bit(inst))
  45. epc += 2;
  46. else
  47. epc += 4;
  48. return epc;
  49. }
  50. /* (microMIPS) Convert 16-bit register encoding to 32-bit register encoding. */
  51. static const unsigned int reg16to32map[8] = {16, 17, 2, 3, 4, 5, 6, 7};
  52. int __mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
  53. unsigned long *contpc)
  54. {
  55. union mips_instruction insn = (union mips_instruction)dec_insn.insn;
  56. int __maybe_unused bc_false = 0;
  57. if (!cpu_has_mmips)
  58. return 0;
  59. switch (insn.mm_i_format.opcode) {
  60. case mm_pool32a_op:
  61. if ((insn.mm_i_format.simmediate & MM_POOL32A_MINOR_MASK) ==
  62. mm_pool32axf_op) {
  63. switch (insn.mm_i_format.simmediate >>
  64. MM_POOL32A_MINOR_SHIFT) {
  65. case mm_jalr_op:
  66. case mm_jalrhb_op:
  67. case mm_jalrs_op:
  68. case mm_jalrshb_op:
  69. if (insn.mm_i_format.rt != 0) /* Not mm_jr */
  70. regs->regs[insn.mm_i_format.rt] =
  71. regs->cp0_epc +
  72. dec_insn.pc_inc +
  73. dec_insn.next_pc_inc;
  74. *contpc = regs->regs[insn.mm_i_format.rs];
  75. return 1;
  76. }
  77. }
  78. break;
  79. case mm_pool32i_op:
  80. switch (insn.mm_i_format.rt) {
  81. case mm_bltzals_op:
  82. case mm_bltzal_op:
  83. regs->regs[31] = regs->cp0_epc +
  84. dec_insn.pc_inc +
  85. dec_insn.next_pc_inc;
  86. fallthrough;
  87. case mm_bltz_op:
  88. if ((long)regs->regs[insn.mm_i_format.rs] < 0)
  89. *contpc = regs->cp0_epc +
  90. dec_insn.pc_inc +
  91. (insn.mm_i_format.simmediate << 1);
  92. else
  93. *contpc = regs->cp0_epc +
  94. dec_insn.pc_inc +
  95. dec_insn.next_pc_inc;
  96. return 1;
  97. case mm_bgezals_op:
  98. case mm_bgezal_op:
  99. regs->regs[31] = regs->cp0_epc +
  100. dec_insn.pc_inc +
  101. dec_insn.next_pc_inc;
  102. fallthrough;
  103. case mm_bgez_op:
  104. if ((long)regs->regs[insn.mm_i_format.rs] >= 0)
  105. *contpc = regs->cp0_epc +
  106. dec_insn.pc_inc +
  107. (insn.mm_i_format.simmediate << 1);
  108. else
  109. *contpc = regs->cp0_epc +
  110. dec_insn.pc_inc +
  111. dec_insn.next_pc_inc;
  112. return 1;
  113. case mm_blez_op:
  114. if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
  115. *contpc = regs->cp0_epc +
  116. dec_insn.pc_inc +
  117. (insn.mm_i_format.simmediate << 1);
  118. else
  119. *contpc = regs->cp0_epc +
  120. dec_insn.pc_inc +
  121. dec_insn.next_pc_inc;
  122. return 1;
  123. case mm_bgtz_op:
  124. if ((long)regs->regs[insn.mm_i_format.rs] <= 0)
  125. *contpc = regs->cp0_epc +
  126. dec_insn.pc_inc +
  127. (insn.mm_i_format.simmediate << 1);
  128. else
  129. *contpc = regs->cp0_epc +
  130. dec_insn.pc_inc +
  131. dec_insn.next_pc_inc;
  132. return 1;
  133. #ifdef CONFIG_MIPS_FP_SUPPORT
  134. case mm_bc2f_op:
  135. case mm_bc1f_op: {
  136. unsigned int fcr31;
  137. unsigned int bit;
  138. bc_false = 1;
  139. fallthrough;
  140. case mm_bc2t_op:
  141. case mm_bc1t_op:
  142. preempt_disable();
  143. if (is_fpu_owner())
  144. fcr31 = read_32bit_cp1_register(CP1_STATUS);
  145. else
  146. fcr31 = current->thread.fpu.fcr31;
  147. preempt_enable();
  148. if (bc_false)
  149. fcr31 = ~fcr31;
  150. bit = (insn.mm_i_format.rs >> 2);
  151. bit += (bit != 0);
  152. bit += 23;
  153. if (fcr31 & (1 << bit))
  154. *contpc = regs->cp0_epc +
  155. dec_insn.pc_inc +
  156. (insn.mm_i_format.simmediate << 1);
  157. else
  158. *contpc = regs->cp0_epc +
  159. dec_insn.pc_inc + dec_insn.next_pc_inc;
  160. return 1;
  161. }
  162. #endif /* CONFIG_MIPS_FP_SUPPORT */
  163. }
  164. break;
  165. case mm_pool16c_op:
  166. switch (insn.mm_i_format.rt) {
  167. case mm_jalr16_op:
  168. case mm_jalrs16_op:
  169. regs->regs[31] = regs->cp0_epc +
  170. dec_insn.pc_inc + dec_insn.next_pc_inc;
  171. fallthrough;
  172. case mm_jr16_op:
  173. *contpc = regs->regs[insn.mm_i_format.rs];
  174. return 1;
  175. }
  176. break;
  177. case mm_beqz16_op:
  178. if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] == 0)
  179. *contpc = regs->cp0_epc +
  180. dec_insn.pc_inc +
  181. (insn.mm_b1_format.simmediate << 1);
  182. else
  183. *contpc = regs->cp0_epc +
  184. dec_insn.pc_inc + dec_insn.next_pc_inc;
  185. return 1;
  186. case mm_bnez16_op:
  187. if ((long)regs->regs[reg16to32map[insn.mm_b1_format.rs]] != 0)
  188. *contpc = regs->cp0_epc +
  189. dec_insn.pc_inc +
  190. (insn.mm_b1_format.simmediate << 1);
  191. else
  192. *contpc = regs->cp0_epc +
  193. dec_insn.pc_inc + dec_insn.next_pc_inc;
  194. return 1;
  195. case mm_b16_op:
  196. *contpc = regs->cp0_epc + dec_insn.pc_inc +
  197. (insn.mm_b0_format.simmediate << 1);
  198. return 1;
  199. case mm_beq32_op:
  200. if (regs->regs[insn.mm_i_format.rs] ==
  201. regs->regs[insn.mm_i_format.rt])
  202. *contpc = regs->cp0_epc +
  203. dec_insn.pc_inc +
  204. (insn.mm_i_format.simmediate << 1);
  205. else
  206. *contpc = regs->cp0_epc +
  207. dec_insn.pc_inc +
  208. dec_insn.next_pc_inc;
  209. return 1;
  210. case mm_bne32_op:
  211. if (regs->regs[insn.mm_i_format.rs] !=
  212. regs->regs[insn.mm_i_format.rt])
  213. *contpc = regs->cp0_epc +
  214. dec_insn.pc_inc +
  215. (insn.mm_i_format.simmediate << 1);
  216. else
  217. *contpc = regs->cp0_epc +
  218. dec_insn.pc_inc + dec_insn.next_pc_inc;
  219. return 1;
  220. case mm_jalx32_op:
  221. regs->regs[31] = regs->cp0_epc +
  222. dec_insn.pc_inc + dec_insn.next_pc_inc;
  223. *contpc = regs->cp0_epc + dec_insn.pc_inc;
  224. *contpc >>= 28;
  225. *contpc <<= 28;
  226. *contpc |= (insn.j_format.target << 2);
  227. return 1;
  228. case mm_jals32_op:
  229. case mm_jal32_op:
  230. regs->regs[31] = regs->cp0_epc +
  231. dec_insn.pc_inc + dec_insn.next_pc_inc;
  232. fallthrough;
  233. case mm_j32_op:
  234. *contpc = regs->cp0_epc + dec_insn.pc_inc;
  235. *contpc >>= 27;
  236. *contpc <<= 27;
  237. *contpc |= (insn.j_format.target << 1);
  238. set_isa16_mode(*contpc);
  239. return 1;
  240. }
  241. return 0;
  242. }
  243. /*
  244. * Compute return address and emulate branch in microMIPS mode after an
  245. * exception only. It does not handle compact branches/jumps and cannot
  246. * be used in interrupt context. (Compact branches/jumps do not cause
  247. * exceptions.)
  248. */
  249. int __microMIPS_compute_return_epc(struct pt_regs *regs)
  250. {
  251. u16 __user *pc16;
  252. u16 halfword;
  253. unsigned int word;
  254. unsigned long contpc;
  255. struct mm_decoded_insn mminsn = { 0 };
  256. mminsn.micro_mips_mode = 1;
  257. /* This load never faults. */
  258. pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc);
  259. __get_user(halfword, pc16);
  260. pc16++;
  261. contpc = regs->cp0_epc + 2;
  262. word = ((unsigned int)halfword << 16);
  263. mminsn.pc_inc = 2;
  264. if (!mm_insn_16bit(halfword)) {
  265. __get_user(halfword, pc16);
  266. pc16++;
  267. contpc = regs->cp0_epc + 4;
  268. mminsn.pc_inc = 4;
  269. word |= halfword;
  270. }
  271. mminsn.insn = word;
  272. if (get_user(halfword, pc16))
  273. goto sigsegv;
  274. mminsn.next_pc_inc = 2;
  275. word = ((unsigned int)halfword << 16);
  276. if (!mm_insn_16bit(halfword)) {
  277. pc16++;
  278. if (get_user(halfword, pc16))
  279. goto sigsegv;
  280. mminsn.next_pc_inc = 4;
  281. word |= halfword;
  282. }
  283. mminsn.next_insn = word;
  284. mm_isBranchInstr(regs, mminsn, &contpc);
  285. regs->cp0_epc = contpc;
  286. return 0;
  287. sigsegv:
  288. force_sig(SIGSEGV);
  289. return -EFAULT;
  290. }
  291. /*
  292. * Compute return address and emulate branch in MIPS16e mode after an
  293. * exception only. It does not handle compact branches/jumps and cannot
  294. * be used in interrupt context. (Compact branches/jumps do not cause
  295. * exceptions.)
  296. */
  297. int __MIPS16e_compute_return_epc(struct pt_regs *regs)
  298. {
  299. u16 __user *addr;
  300. union mips16e_instruction inst;
  301. u16 inst2;
  302. u32 fullinst;
  303. long epc;
  304. epc = regs->cp0_epc;
  305. /* Read the instruction. */
  306. addr = (u16 __user *)msk_isa16_mode(epc);
  307. if (__get_user(inst.full, addr)) {
  308. force_sig(SIGSEGV);
  309. return -EFAULT;
  310. }
  311. switch (inst.ri.opcode) {
  312. case MIPS16e_extend_op:
  313. regs->cp0_epc += 4;
  314. return 0;
  315. /*
  316. * JAL and JALX in MIPS16e mode
  317. */
  318. case MIPS16e_jal_op:
  319. addr += 1;
  320. if (__get_user(inst2, addr)) {
  321. force_sig(SIGSEGV);
  322. return -EFAULT;
  323. }
  324. fullinst = ((unsigned)inst.full << 16) | inst2;
  325. regs->regs[31] = epc + 6;
  326. epc += 4;
  327. epc >>= 28;
  328. epc <<= 28;
  329. /*
  330. * JAL:5 X:1 TARGET[20-16]:5 TARGET[25:21]:5 TARGET[15:0]:16
  331. *
  332. * ......TARGET[15:0].................TARGET[20:16]...........
  333. * ......TARGET[25:21]
  334. */
  335. epc |=
  336. ((fullinst & 0xffff) << 2) | ((fullinst & 0x3e00000) >> 3) |
  337. ((fullinst & 0x1f0000) << 7);
  338. if (!inst.jal.x)
  339. set_isa16_mode(epc); /* Set ISA mode bit. */
  340. regs->cp0_epc = epc;
  341. return 0;
  342. /*
  343. * J(AL)R(C)
  344. */
  345. case MIPS16e_rr_op:
  346. if (inst.rr.func == MIPS16e_jr_func) {
  347. if (inst.rr.ra)
  348. regs->cp0_epc = regs->regs[31];
  349. else
  350. regs->cp0_epc =
  351. regs->regs[reg16to32[inst.rr.rx]];
  352. if (inst.rr.l) {
  353. if (inst.rr.nd)
  354. regs->regs[31] = epc + 2;
  355. else
  356. regs->regs[31] = epc + 4;
  357. }
  358. return 0;
  359. }
  360. break;
  361. }
  362. /*
  363. * All other cases have no branch delay slot and are 16-bits.
  364. * Branches do not cause an exception.
  365. */
  366. regs->cp0_epc += 2;
  367. return 0;
  368. }
  369. /**
  370. * __compute_return_epc_for_insn - Computes the return address and do emulate
  371. * branch simulation, if required.
  372. *
  373. * @regs: Pointer to pt_regs
  374. * @insn: branch instruction to decode
  375. * Return: -EFAULT on error and forces SIGILL, and on success
  376. * returns 0 or BRANCH_LIKELY_TAKEN as appropriate after
  377. * evaluating the branch.
  378. *
  379. * MIPS R6 Compact branches and forbidden slots:
  380. * Compact branches do not throw exceptions because they do
  381. * not have delay slots. The forbidden slot instruction ($PC+4)
  382. * is only executed if the branch was not taken. Otherwise the
  383. * forbidden slot is skipped entirely. This means that the
  384. * only possible reason to be here because of a MIPS R6 compact
  385. * branch instruction is that the forbidden slot has thrown one.
  386. * In that case the branch was not taken, so the EPC can be safely
  387. * set to EPC + 8.
  388. */
  389. int __compute_return_epc_for_insn(struct pt_regs *regs,
  390. union mips_instruction insn)
  391. {
  392. long epc = regs->cp0_epc;
  393. unsigned int dspcontrol;
  394. int ret = 0;
  395. switch (insn.i_format.opcode) {
  396. /*
  397. * jr and jalr are in r_format format.
  398. */
  399. case spec_op:
  400. switch (insn.r_format.func) {
  401. case jalr_op:
  402. regs->regs[insn.r_format.rd] = epc + 8;
  403. fallthrough;
  404. case jr_op:
  405. if (NO_R6EMU && insn.r_format.func == jr_op)
  406. goto sigill_r2r6;
  407. regs->cp0_epc = regs->regs[insn.r_format.rs];
  408. break;
  409. }
  410. break;
  411. /*
  412. * This group contains:
  413. * bltz_op, bgez_op, bltzl_op, bgezl_op,
  414. * bltzal_op, bgezal_op, bltzall_op, bgezall_op.
  415. */
  416. case bcond_op:
  417. switch (insn.i_format.rt) {
  418. case bltzl_op:
  419. if (NO_R6EMU)
  420. goto sigill_r2r6;
  421. fallthrough;
  422. case bltz_op:
  423. if ((long)regs->regs[insn.i_format.rs] < 0) {
  424. epc = epc + 4 + (insn.i_format.simmediate << 2);
  425. if (insn.i_format.rt == bltzl_op)
  426. ret = BRANCH_LIKELY_TAKEN;
  427. } else
  428. epc += 8;
  429. regs->cp0_epc = epc;
  430. break;
  431. case bgezl_op:
  432. if (NO_R6EMU)
  433. goto sigill_r2r6;
  434. fallthrough;
  435. case bgez_op:
  436. if ((long)regs->regs[insn.i_format.rs] >= 0) {
  437. epc = epc + 4 + (insn.i_format.simmediate << 2);
  438. if (insn.i_format.rt == bgezl_op)
  439. ret = BRANCH_LIKELY_TAKEN;
  440. } else
  441. epc += 8;
  442. regs->cp0_epc = epc;
  443. break;
  444. case bltzal_op:
  445. case bltzall_op:
  446. if (NO_R6EMU && (insn.i_format.rs ||
  447. insn.i_format.rt == bltzall_op))
  448. goto sigill_r2r6;
  449. regs->regs[31] = epc + 8;
  450. /*
  451. * OK we are here either because we hit a NAL
  452. * instruction or because we are emulating an
  453. * old bltzal{,l} one. Let's figure out what the
  454. * case really is.
  455. */
  456. if (!insn.i_format.rs) {
  457. /*
  458. * NAL or BLTZAL with rs == 0
  459. * Doesn't matter if we are R6 or not. The
  460. * result is the same
  461. */
  462. regs->cp0_epc += 4 +
  463. (insn.i_format.simmediate << 2);
  464. break;
  465. }
  466. /* Now do the real thing for non-R6 BLTZAL{,L} */
  467. if ((long)regs->regs[insn.i_format.rs] < 0) {
  468. epc = epc + 4 + (insn.i_format.simmediate << 2);
  469. if (insn.i_format.rt == bltzall_op)
  470. ret = BRANCH_LIKELY_TAKEN;
  471. } else
  472. epc += 8;
  473. regs->cp0_epc = epc;
  474. break;
  475. case bgezal_op:
  476. case bgezall_op:
  477. if (NO_R6EMU && (insn.i_format.rs ||
  478. insn.i_format.rt == bgezall_op))
  479. goto sigill_r2r6;
  480. regs->regs[31] = epc + 8;
  481. /*
  482. * OK we are here either because we hit a BAL
  483. * instruction or because we are emulating an
  484. * old bgezal{,l} one. Let's figure out what the
  485. * case really is.
  486. */
  487. if (!insn.i_format.rs) {
  488. /*
  489. * BAL or BGEZAL with rs == 0
  490. * Doesn't matter if we are R6 or not. The
  491. * result is the same
  492. */
  493. regs->cp0_epc += 4 +
  494. (insn.i_format.simmediate << 2);
  495. break;
  496. }
  497. /* Now do the real thing for non-R6 BGEZAL{,L} */
  498. if ((long)regs->regs[insn.i_format.rs] >= 0) {
  499. epc = epc + 4 + (insn.i_format.simmediate << 2);
  500. if (insn.i_format.rt == bgezall_op)
  501. ret = BRANCH_LIKELY_TAKEN;
  502. } else
  503. epc += 8;
  504. regs->cp0_epc = epc;
  505. break;
  506. case bposge32_op:
  507. if (!cpu_has_dsp)
  508. goto sigill_dsp;
  509. dspcontrol = rddsp(0x01);
  510. if (dspcontrol >= 32) {
  511. epc = epc + 4 + (insn.i_format.simmediate << 2);
  512. } else
  513. epc += 8;
  514. regs->cp0_epc = epc;
  515. break;
  516. }
  517. break;
  518. /*
  519. * These are unconditional and in j_format.
  520. */
  521. case jalx_op:
  522. case jal_op:
  523. regs->regs[31] = regs->cp0_epc + 8;
  524. fallthrough;
  525. case j_op:
  526. epc += 4;
  527. epc >>= 28;
  528. epc <<= 28;
  529. epc |= (insn.j_format.target << 2);
  530. regs->cp0_epc = epc;
  531. if (insn.i_format.opcode == jalx_op)
  532. set_isa16_mode(regs->cp0_epc);
  533. break;
  534. /*
  535. * These are conditional and in i_format.
  536. */
  537. case beql_op:
  538. if (NO_R6EMU)
  539. goto sigill_r2r6;
  540. fallthrough;
  541. case beq_op:
  542. if (regs->regs[insn.i_format.rs] ==
  543. regs->regs[insn.i_format.rt]) {
  544. epc = epc + 4 + (insn.i_format.simmediate << 2);
  545. if (insn.i_format.opcode == beql_op)
  546. ret = BRANCH_LIKELY_TAKEN;
  547. } else
  548. epc += 8;
  549. regs->cp0_epc = epc;
  550. break;
  551. case bnel_op:
  552. if (NO_R6EMU)
  553. goto sigill_r2r6;
  554. fallthrough;
  555. case bne_op:
  556. if (regs->regs[insn.i_format.rs] !=
  557. regs->regs[insn.i_format.rt]) {
  558. epc = epc + 4 + (insn.i_format.simmediate << 2);
  559. if (insn.i_format.opcode == bnel_op)
  560. ret = BRANCH_LIKELY_TAKEN;
  561. } else
  562. epc += 8;
  563. regs->cp0_epc = epc;
  564. break;
  565. case blezl_op: /* not really i_format */
  566. if (!insn.i_format.rt && NO_R6EMU)
  567. goto sigill_r2r6;
  568. fallthrough;
  569. case blez_op:
  570. /*
  571. * Compact branches for R6 for the
  572. * blez and blezl opcodes.
  573. * BLEZ | rs = 0 | rt != 0 == BLEZALC
  574. * BLEZ | rs = rt != 0 == BGEZALC
  575. * BLEZ | rs != 0 | rt != 0 == BGEUC
  576. * BLEZL | rs = 0 | rt != 0 == BLEZC
  577. * BLEZL | rs = rt != 0 == BGEZC
  578. * BLEZL | rs != 0 | rt != 0 == BGEC
  579. *
  580. * For real BLEZ{,L}, rt is always 0.
  581. */
  582. if (cpu_has_mips_r6 && insn.i_format.rt) {
  583. if ((insn.i_format.opcode == blez_op) &&
  584. ((!insn.i_format.rs && insn.i_format.rt) ||
  585. (insn.i_format.rs == insn.i_format.rt)))
  586. regs->regs[31] = epc + 4;
  587. regs->cp0_epc += 8;
  588. break;
  589. }
  590. /* rt field assumed to be zero */
  591. if ((long)regs->regs[insn.i_format.rs] <= 0) {
  592. epc = epc + 4 + (insn.i_format.simmediate << 2);
  593. if (insn.i_format.opcode == blezl_op)
  594. ret = BRANCH_LIKELY_TAKEN;
  595. } else
  596. epc += 8;
  597. regs->cp0_epc = epc;
  598. break;
  599. case bgtzl_op:
  600. if (!insn.i_format.rt && NO_R6EMU)
  601. goto sigill_r2r6;
  602. fallthrough;
  603. case bgtz_op:
  604. /*
  605. * Compact branches for R6 for the
  606. * bgtz and bgtzl opcodes.
  607. * BGTZ | rs = 0 | rt != 0 == BGTZALC
  608. * BGTZ | rs = rt != 0 == BLTZALC
  609. * BGTZ | rs != 0 | rt != 0 == BLTUC
  610. * BGTZL | rs = 0 | rt != 0 == BGTZC
  611. * BGTZL | rs = rt != 0 == BLTZC
  612. * BGTZL | rs != 0 | rt != 0 == BLTC
  613. *
  614. * *ZALC varint for BGTZ &&& rt != 0
  615. * For real GTZ{,L}, rt is always 0.
  616. */
  617. if (cpu_has_mips_r6 && insn.i_format.rt) {
  618. if ((insn.i_format.opcode == blez_op) &&
  619. ((!insn.i_format.rs && insn.i_format.rt) ||
  620. (insn.i_format.rs == insn.i_format.rt)))
  621. regs->regs[31] = epc + 4;
  622. regs->cp0_epc += 8;
  623. break;
  624. }
  625. /* rt field assumed to be zero */
  626. if ((long)regs->regs[insn.i_format.rs] > 0) {
  627. epc = epc + 4 + (insn.i_format.simmediate << 2);
  628. if (insn.i_format.opcode == bgtzl_op)
  629. ret = BRANCH_LIKELY_TAKEN;
  630. } else
  631. epc += 8;
  632. regs->cp0_epc = epc;
  633. break;
  634. #ifdef CONFIG_MIPS_FP_SUPPORT
  635. /*
  636. * And now the FPA/cp1 branch instructions.
  637. */
  638. case cop1_op: {
  639. unsigned int bit, fcr31, reg;
  640. if (cpu_has_mips_r6 &&
  641. ((insn.i_format.rs == bc1eqz_op) ||
  642. (insn.i_format.rs == bc1nez_op))) {
  643. if (!init_fp_ctx(current))
  644. lose_fpu(1);
  645. reg = insn.i_format.rt;
  646. bit = get_fpr32(&current->thread.fpu.fpr[reg], 0) & 0x1;
  647. if (insn.i_format.rs == bc1eqz_op)
  648. bit = !bit;
  649. own_fpu(1);
  650. if (bit)
  651. epc = epc + 4 +
  652. (insn.i_format.simmediate << 2);
  653. else
  654. epc += 8;
  655. regs->cp0_epc = epc;
  656. break;
  657. } else {
  658. preempt_disable();
  659. if (is_fpu_owner())
  660. fcr31 = read_32bit_cp1_register(CP1_STATUS);
  661. else
  662. fcr31 = current->thread.fpu.fcr31;
  663. preempt_enable();
  664. bit = (insn.i_format.rt >> 2);
  665. bit += (bit != 0);
  666. bit += 23;
  667. switch (insn.i_format.rt & 3) {
  668. case 0: /* bc1f */
  669. case 2: /* bc1fl */
  670. if (~fcr31 & (1 << bit)) {
  671. epc = epc + 4 +
  672. (insn.i_format.simmediate << 2);
  673. if (insn.i_format.rt == 2)
  674. ret = BRANCH_LIKELY_TAKEN;
  675. } else
  676. epc += 8;
  677. regs->cp0_epc = epc;
  678. break;
  679. case 1: /* bc1t */
  680. case 3: /* bc1tl */
  681. if (fcr31 & (1 << bit)) {
  682. epc = epc + 4 +
  683. (insn.i_format.simmediate << 2);
  684. if (insn.i_format.rt == 3)
  685. ret = BRANCH_LIKELY_TAKEN;
  686. } else
  687. epc += 8;
  688. regs->cp0_epc = epc;
  689. break;
  690. }
  691. break;
  692. }
  693. }
  694. #endif /* CONFIG_MIPS_FP_SUPPORT */
  695. #ifdef CONFIG_CPU_CAVIUM_OCTEON
  696. case lwc2_op: /* This is bbit0 on Octeon */
  697. if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
  698. == 0)
  699. epc = epc + 4 + (insn.i_format.simmediate << 2);
  700. else
  701. epc += 8;
  702. regs->cp0_epc = epc;
  703. break;
  704. case ldc2_op: /* This is bbit032 on Octeon */
  705. if ((regs->regs[insn.i_format.rs] &
  706. (1ull<<(insn.i_format.rt+32))) == 0)
  707. epc = epc + 4 + (insn.i_format.simmediate << 2);
  708. else
  709. epc += 8;
  710. regs->cp0_epc = epc;
  711. break;
  712. case swc2_op: /* This is bbit1 on Octeon */
  713. if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
  714. epc = epc + 4 + (insn.i_format.simmediate << 2);
  715. else
  716. epc += 8;
  717. regs->cp0_epc = epc;
  718. break;
  719. case sdc2_op: /* This is bbit132 on Octeon */
  720. if (regs->regs[insn.i_format.rs] &
  721. (1ull<<(insn.i_format.rt+32)))
  722. epc = epc + 4 + (insn.i_format.simmediate << 2);
  723. else
  724. epc += 8;
  725. regs->cp0_epc = epc;
  726. break;
  727. #else
  728. case bc6_op:
  729. /* Only valid for MIPS R6 */
  730. if (!cpu_has_mips_r6)
  731. goto sigill_r6;
  732. regs->cp0_epc += 8;
  733. break;
  734. case balc6_op:
  735. if (!cpu_has_mips_r6)
  736. goto sigill_r6;
  737. /* Compact branch: BALC */
  738. regs->regs[31] = epc + 4;
  739. epc += 4 + (insn.i_format.simmediate << 2);
  740. regs->cp0_epc = epc;
  741. break;
  742. case pop66_op:
  743. if (!cpu_has_mips_r6)
  744. goto sigill_r6;
  745. /* Compact branch: BEQZC || JIC */
  746. regs->cp0_epc += 8;
  747. break;
  748. case pop76_op:
  749. if (!cpu_has_mips_r6)
  750. goto sigill_r6;
  751. /* Compact branch: BNEZC || JIALC */
  752. if (!insn.i_format.rs) {
  753. /* JIALC: set $31/ra */
  754. regs->regs[31] = epc + 4;
  755. }
  756. regs->cp0_epc += 8;
  757. break;
  758. #endif
  759. case pop10_op:
  760. case pop30_op:
  761. /* Only valid for MIPS R6 */
  762. if (!cpu_has_mips_r6)
  763. goto sigill_r6;
  764. /*
  765. * Compact branches:
  766. * bovc, beqc, beqzalc, bnvc, bnec, bnezlac
  767. */
  768. if (insn.i_format.rt && !insn.i_format.rs)
  769. regs->regs[31] = epc + 4;
  770. regs->cp0_epc += 8;
  771. break;
  772. }
  773. return ret;
  774. sigill_dsp:
  775. pr_debug("%s: DSP branch but not DSP ASE - sending SIGILL.\n",
  776. current->comm);
  777. force_sig(SIGILL);
  778. return -EFAULT;
  779. sigill_r2r6:
  780. pr_debug("%s: R2 branch but r2-to-r6 emulator is not present - sending SIGILL.\n",
  781. current->comm);
  782. force_sig(SIGILL);
  783. return -EFAULT;
  784. sigill_r6:
  785. pr_debug("%s: R6 branch but no MIPSr6 ISA support - sending SIGILL.\n",
  786. current->comm);
  787. force_sig(SIGILL);
  788. return -EFAULT;
  789. }
  790. EXPORT_SYMBOL_GPL(__compute_return_epc_for_insn);
  791. int __compute_return_epc(struct pt_regs *regs)
  792. {
  793. unsigned int __user *addr;
  794. long epc;
  795. union mips_instruction insn;
  796. epc = regs->cp0_epc;
  797. if (epc & 3)
  798. goto unaligned;
  799. /*
  800. * Read the instruction
  801. */
  802. addr = (unsigned int __user *) epc;
  803. if (__get_user(insn.word, addr)) {
  804. force_sig(SIGSEGV);
  805. return -EFAULT;
  806. }
  807. return __compute_return_epc_for_insn(regs, insn);
  808. unaligned:
  809. printk("%s: unaligned epc - sending SIGBUS.\n", current->comm);
  810. force_sig(SIGBUS);
  811. return -EFAULT;
  812. }
  813. #if (defined CONFIG_KPROBES) || (defined CONFIG_UPROBES)
  814. int __insn_is_compact_branch(union mips_instruction insn)
  815. {
  816. if (!cpu_has_mips_r6)
  817. return 0;
  818. switch (insn.i_format.opcode) {
  819. case blezl_op:
  820. case bgtzl_op:
  821. case blez_op:
  822. case bgtz_op:
  823. /*
  824. * blez[l] and bgtz[l] opcodes with non-zero rt
  825. * are MIPS R6 compact branches
  826. */
  827. if (insn.i_format.rt)
  828. return 1;
  829. break;
  830. case bc6_op:
  831. case balc6_op:
  832. case pop10_op:
  833. case pop30_op:
  834. case pop66_op:
  835. case pop76_op:
  836. return 1;
  837. }
  838. return 0;
  839. }
  840. EXPORT_SYMBOL_GPL(__insn_is_compact_branch);
  841. #endif /* CONFIG_KPROBES || CONFIG_UPROBES */