sni.h 7.3 KB

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  1. /*
  2. * SNI specific definitions
  3. *
  4. * This file is subject to the terms and conditions of the GNU General Public
  5. * License. See the file "COPYING" in the main directory of this archive
  6. * for more details.
  7. *
  8. * Copyright (C) 1997, 1998 by Ralf Baechle
  9. * Copyright (C) 2006 Thomas Bogendoerfer ([email protected])
  10. */
  11. #ifndef __ASM_SNI_H
  12. #define __ASM_SNI_H
  13. #include <linux/irqreturn.h>
  14. extern unsigned int sni_brd_type;
  15. #define SNI_BRD_10 2
  16. #define SNI_BRD_10NEW 3
  17. #define SNI_BRD_TOWER_OASIC 4
  18. #define SNI_BRD_MINITOWER 5
  19. #define SNI_BRD_PCI_TOWER 6
  20. #define SNI_BRD_RM200 7
  21. #define SNI_BRD_PCI_MTOWER 8
  22. #define SNI_BRD_PCI_DESKTOP 9
  23. #define SNI_BRD_PCI_TOWER_CPLUS 10
  24. #define SNI_BRD_PCI_MTOWER_CPLUS 11
  25. /* RM400 cpu types */
  26. #define SNI_CPU_M8021 0x01
  27. #define SNI_CPU_M8030 0x04
  28. #define SNI_CPU_M8031 0x06
  29. #define SNI_CPU_M8034 0x0f
  30. #define SNI_CPU_M8037 0x07
  31. #define SNI_CPU_M8040 0x05
  32. #define SNI_CPU_M8043 0x09
  33. #define SNI_CPU_M8050 0x0b
  34. #define SNI_CPU_M8053 0x0d
  35. #define SNI_PORT_BASE CKSEG1ADDR(0xb4000000)
  36. #ifndef __MIPSEL__
  37. /*
  38. * ASIC PCI registers for big endian configuration.
  39. */
  40. #define PCIMT_UCONF CKSEG1ADDR(0xbfff0004)
  41. #define PCIMT_IOADTIMEOUT2 CKSEG1ADDR(0xbfff000c)
  42. #define PCIMT_IOMEMCONF CKSEG1ADDR(0xbfff0014)
  43. #define PCIMT_IOMMU CKSEG1ADDR(0xbfff001c)
  44. #define PCIMT_IOADTIMEOUT1 CKSEG1ADDR(0xbfff0024)
  45. #define PCIMT_DMAACCESS CKSEG1ADDR(0xbfff002c)
  46. #define PCIMT_DMAHIT CKSEG1ADDR(0xbfff0034)
  47. #define PCIMT_ERRSTATUS CKSEG1ADDR(0xbfff003c)
  48. #define PCIMT_ERRADDR CKSEG1ADDR(0xbfff0044)
  49. #define PCIMT_SYNDROME CKSEG1ADDR(0xbfff004c)
  50. #define PCIMT_ITPEND CKSEG1ADDR(0xbfff0054)
  51. #define IT_INT2 0x01
  52. #define IT_INTD 0x02
  53. #define IT_INTC 0x04
  54. #define IT_INTB 0x08
  55. #define IT_INTA 0x10
  56. #define IT_EISA 0x20
  57. #define IT_SCSI 0x40
  58. #define IT_ETH 0x80
  59. #define PCIMT_IRQSEL CKSEG1ADDR(0xbfff005c)
  60. #define PCIMT_TESTMEM CKSEG1ADDR(0xbfff0064)
  61. #define PCIMT_ECCREG CKSEG1ADDR(0xbfff006c)
  62. #define PCIMT_CONFIG_ADDRESS CKSEG1ADDR(0xbfff0074)
  63. #define PCIMT_ASIC_ID CKSEG1ADDR(0xbfff007c) /* read */
  64. #define PCIMT_SOFT_RESET CKSEG1ADDR(0xbfff007c) /* write */
  65. #define PCIMT_PIA_OE CKSEG1ADDR(0xbfff0084)
  66. #define PCIMT_PIA_DATAOUT CKSEG1ADDR(0xbfff008c)
  67. #define PCIMT_PIA_DATAIN CKSEG1ADDR(0xbfff0094)
  68. #define PCIMT_CACHECONF CKSEG1ADDR(0xbfff009c)
  69. #define PCIMT_INVSPACE CKSEG1ADDR(0xbfff00a4)
  70. #else
  71. /*
  72. * ASIC PCI registers for little endian configuration.
  73. */
  74. #define PCIMT_UCONF CKSEG1ADDR(0xbfff0000)
  75. #define PCIMT_IOADTIMEOUT2 CKSEG1ADDR(0xbfff0008)
  76. #define PCIMT_IOMEMCONF CKSEG1ADDR(0xbfff0010)
  77. #define PCIMT_IOMMU CKSEG1ADDR(0xbfff0018)
  78. #define PCIMT_IOADTIMEOUT1 CKSEG1ADDR(0xbfff0020)
  79. #define PCIMT_DMAACCESS CKSEG1ADDR(0xbfff0028)
  80. #define PCIMT_DMAHIT CKSEG1ADDR(0xbfff0030)
  81. #define PCIMT_ERRSTATUS CKSEG1ADDR(0xbfff0038)
  82. #define PCIMT_ERRADDR CKSEG1ADDR(0xbfff0040)
  83. #define PCIMT_SYNDROME CKSEG1ADDR(0xbfff0048)
  84. #define PCIMT_ITPEND CKSEG1ADDR(0xbfff0050)
  85. #define IT_INT2 0x01
  86. #define IT_INTD 0x02
  87. #define IT_INTC 0x04
  88. #define IT_INTB 0x08
  89. #define IT_INTA 0x10
  90. #define IT_EISA 0x20
  91. #define IT_SCSI 0x40
  92. #define IT_ETH 0x80
  93. #define PCIMT_IRQSEL CKSEG1ADDR(0xbfff0058)
  94. #define PCIMT_TESTMEM CKSEG1ADDR(0xbfff0060)
  95. #define PCIMT_ECCREG CKSEG1ADDR(0xbfff0068)
  96. #define PCIMT_CONFIG_ADDRESS CKSEG1ADDR(0xbfff0070)
  97. #define PCIMT_ASIC_ID CKSEG1ADDR(0xbfff0078) /* read */
  98. #define PCIMT_SOFT_RESET CKSEG1ADDR(0xbfff0078) /* write */
  99. #define PCIMT_PIA_OE CKSEG1ADDR(0xbfff0080)
  100. #define PCIMT_PIA_DATAOUT CKSEG1ADDR(0xbfff0088)
  101. #define PCIMT_PIA_DATAIN CKSEG1ADDR(0xbfff0090)
  102. #define PCIMT_CACHECONF CKSEG1ADDR(0xbfff0098)
  103. #define PCIMT_INVSPACE CKSEG1ADDR(0xbfff00a0)
  104. #endif
  105. #define PCIMT_PCI_CONF CKSEG1ADDR(0xbfff0100)
  106. /*
  107. * Data port for the PCI bus in IO space
  108. */
  109. #define PCIMT_CONFIG_DATA 0x0cfc
  110. /*
  111. * Board specific registers
  112. */
  113. #define PCIMT_CSMSR CKSEG1ADDR(0xbfd00000)
  114. #define PCIMT_CSSWITCH CKSEG1ADDR(0xbfd10000)
  115. #define PCIMT_CSITPEND CKSEG1ADDR(0xbfd20000)
  116. #define PCIMT_AUTO_PO_EN CKSEG1ADDR(0xbfd30000)
  117. #define PCIMT_CLR_TEMP CKSEG1ADDR(0xbfd40000)
  118. #define PCIMT_AUTO_PO_DIS CKSEG1ADDR(0xbfd50000)
  119. #define PCIMT_EXMSR CKSEG1ADDR(0xbfd60000)
  120. #define PCIMT_UNUSED1 CKSEG1ADDR(0xbfd70000)
  121. #define PCIMT_CSWCSM CKSEG1ADDR(0xbfd80000)
  122. #define PCIMT_UNUSED2 CKSEG1ADDR(0xbfd90000)
  123. #define PCIMT_CSLED CKSEG1ADDR(0xbfda0000)
  124. #define PCIMT_CSMAPISA CKSEG1ADDR(0xbfdb0000)
  125. #define PCIMT_CSRSTBP CKSEG1ADDR(0xbfdc0000)
  126. #define PCIMT_CLRPOFF CKSEG1ADDR(0xbfdd0000)
  127. #define PCIMT_CSTIMER CKSEG1ADDR(0xbfde0000)
  128. #define PCIMT_PWDN CKSEG1ADDR(0xbfdf0000)
  129. /*
  130. * A20R based boards
  131. */
  132. #define A20R_PT_CLOCK_BASE CKSEG1ADDR(0xbc040000)
  133. #define A20R_PT_TIM0_ACK CKSEG1ADDR(0xbc050000)
  134. #define A20R_PT_TIM1_ACK CKSEG1ADDR(0xbc060000)
  135. #define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE
  136. #define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5)
  137. #define SNI_PCIT_INT_REG CKSEG1ADDR(0xbfff000c)
  138. #define SNI_PCIT_INT_START 24
  139. #define SNI_PCIT_INT_END 30
  140. #define PCIT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE + 5)
  141. #define PCIT_IRQ_INTA (SNI_PCIT_INT_START + 0)
  142. #define PCIT_IRQ_INTB (SNI_PCIT_INT_START + 1)
  143. #define PCIT_IRQ_INTC (SNI_PCIT_INT_START + 2)
  144. #define PCIT_IRQ_INTD (SNI_PCIT_INT_START + 3)
  145. #define PCIT_IRQ_SCSI0 (SNI_PCIT_INT_START + 4)
  146. #define PCIT_IRQ_SCSI1 (SNI_PCIT_INT_START + 5)
  147. /*
  148. * Interrupt 0-16 are EISA interrupts. Interrupts from 16 on are assigned
  149. * to the other interrupts generated by ASIC PCI.
  150. *
  151. * INT2 is a wired-or of the push button interrupt, high temperature interrupt
  152. * ASIC PCI interrupt.
  153. */
  154. #define PCIMT_KEYBOARD_IRQ 1
  155. #define PCIMT_IRQ_INT2 24
  156. #define PCIMT_IRQ_INTD 25
  157. #define PCIMT_IRQ_INTC 26
  158. #define PCIMT_IRQ_INTB 27
  159. #define PCIMT_IRQ_INTA 28
  160. #define PCIMT_IRQ_EISA 29
  161. #define PCIMT_IRQ_SCSI 30
  162. #define PCIMT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE+6)
  163. #if 0
  164. #define PCIMT_IRQ_TEMPERATURE 24
  165. #define PCIMT_IRQ_EISA_NMI 25
  166. #define PCIMT_IRQ_POWER_OFF 26
  167. #define PCIMT_IRQ_BUTTON 27
  168. #endif
  169. /*
  170. * Base address for the mapped 16mb EISA bus segment.
  171. */
  172. #define PCIMT_EISA_BASE CKSEG1ADDR(0xb0000000)
  173. /* PCI EISA Interrupt acknowledge */
  174. #define PCIMT_INT_ACKNOWLEDGE CKSEG1ADDR(0xba000000)
  175. /*
  176. * SNI ID PROM
  177. *
  178. * SNI_IDPROM_MEMSIZE Memsize in 16MB quantities
  179. * SNI_IDPROM_BRDTYPE Board Type
  180. * SNI_IDPROM_CPUTYPE CPU Type on RM400
  181. */
  182. #ifdef CONFIG_CPU_BIG_ENDIAN
  183. #define __SNI_END 0
  184. #endif
  185. #ifdef CONFIG_CPU_LITTLE_ENDIAN
  186. #define __SNI_END 3
  187. #endif
  188. #define SNI_IDPROM_BASE CKSEG1ADDR(0x1ff00000)
  189. #define SNI_IDPROM_MEMSIZE (SNI_IDPROM_BASE + (0x28 ^ __SNI_END))
  190. #define SNI_IDPROM_BRDTYPE (SNI_IDPROM_BASE + (0x29 ^ __SNI_END))
  191. #define SNI_IDPROM_CPUTYPE (SNI_IDPROM_BASE + (0x30 ^ __SNI_END))
  192. #define SNI_IDPROM_SIZE 0x1000
  193. /* board specific init functions */
  194. extern void sni_a20r_init(void);
  195. extern void sni_pcit_init(void);
  196. extern void sni_rm200_init(void);
  197. extern void sni_pcimt_init(void);
  198. /* board specific irq init functions */
  199. extern void sni_a20r_irq_init(void);
  200. extern void sni_pcit_irq_init(void);
  201. extern void sni_pcit_cplus_irq_init(void);
  202. extern void sni_rm200_irq_init(void);
  203. extern void sni_pcimt_irq_init(void);
  204. /* eisa init for RM200/400 */
  205. #ifdef CONFIG_EISA
  206. extern int sni_eisa_root_init(void);
  207. #else
  208. static inline int sni_eisa_root_init(void)
  209. {
  210. return 0;
  211. }
  212. #endif
  213. /* common irq stuff */
  214. extern void (*sni_hwint)(void);
  215. extern irqreturn_t sni_isa_irq_handler(int dummy, void *p);
  216. #endif /* __ASM_SNI_H */