io.h 17 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 1994, 1995 Waldorf GmbH
  7. * Copyright (C) 1994 - 2000, 06 Ralf Baechle
  8. * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  9. * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
  10. * Author: Maciej W. Rozycki <[email protected]>
  11. */
  12. #ifndef _ASM_IO_H
  13. #define _ASM_IO_H
  14. #define ARCH_HAS_IOREMAP_WC
  15. #include <linux/compiler.h>
  16. #include <linux/kernel.h>
  17. #include <linux/types.h>
  18. #include <linux/irqflags.h>
  19. #include <asm/addrspace.h>
  20. #include <asm/barrier.h>
  21. #include <asm/bug.h>
  22. #include <asm/byteorder.h>
  23. #include <asm/cpu.h>
  24. #include <asm/cpu-features.h>
  25. #include <asm-generic/iomap.h>
  26. #include <asm/page.h>
  27. #include <asm/pgtable-bits.h>
  28. #include <asm/processor.h>
  29. #include <asm/string.h>
  30. #include <mangle-port.h>
  31. /*
  32. * Raw operations are never swapped in software. OTOH values that raw
  33. * operations are working on may or may not have been swapped by the bus
  34. * hardware. An example use would be for flash memory that's used for
  35. * execute in place.
  36. */
  37. # define __raw_ioswabb(a, x) (x)
  38. # define __raw_ioswabw(a, x) (x)
  39. # define __raw_ioswabl(a, x) (x)
  40. # define __raw_ioswabq(a, x) (x)
  41. # define ____raw_ioswabq(a, x) (x)
  42. # define __relaxed_ioswabb ioswabb
  43. # define __relaxed_ioswabw ioswabw
  44. # define __relaxed_ioswabl ioswabl
  45. # define __relaxed_ioswabq ioswabq
  46. /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
  47. /*
  48. * On MIPS I/O ports are memory mapped, so we access them using normal
  49. * load/store instructions. mips_io_port_base is the virtual address to
  50. * which all ports are being mapped. For sake of efficiency some code
  51. * assumes that this is an address that can be loaded with a single lui
  52. * instruction, so the lower 16 bits must be zero. Should be true on
  53. * any sane architecture; generic code does not use this assumption.
  54. */
  55. extern unsigned long mips_io_port_base;
  56. static inline void set_io_port_base(unsigned long base)
  57. {
  58. mips_io_port_base = base;
  59. }
  60. /*
  61. * Provide the necessary definitions for generic iomap. We make use of
  62. * mips_io_port_base for iomap(), but we don't reserve any low addresses for
  63. * use with I/O ports.
  64. */
  65. #define HAVE_ARCH_PIO_SIZE
  66. #define PIO_OFFSET mips_io_port_base
  67. #define PIO_MASK IO_SPACE_LIMIT
  68. #define PIO_RESERVED 0x0UL
  69. /*
  70. * Enforce in-order execution of data I/O. In the MIPS architecture
  71. * these are equivalent to corresponding platform-specific memory
  72. * barriers defined in <asm/barrier.h>. API pinched from PowerPC,
  73. * with sync additionally defined.
  74. */
  75. #define iobarrier_rw() mb()
  76. #define iobarrier_r() rmb()
  77. #define iobarrier_w() wmb()
  78. #define iobarrier_sync() iob()
  79. /*
  80. * virt_to_phys - map virtual addresses to physical
  81. * @address: address to remap
  82. *
  83. * The returned physical address is the physical (CPU) mapping for
  84. * the memory address given. It is only valid to use this function on
  85. * addresses directly mapped or allocated via kmalloc.
  86. *
  87. * This function does not give bus mappings for DMA transfers. In
  88. * almost all conceivable cases a device driver should not be using
  89. * this function
  90. */
  91. static inline unsigned long __virt_to_phys_nodebug(volatile const void *address)
  92. {
  93. return __pa(address);
  94. }
  95. #ifdef CONFIG_DEBUG_VIRTUAL
  96. extern phys_addr_t __virt_to_phys(volatile const void *x);
  97. #else
  98. #define __virt_to_phys(x) __virt_to_phys_nodebug(x)
  99. #endif
  100. #define virt_to_phys virt_to_phys
  101. static inline phys_addr_t virt_to_phys(const volatile void *x)
  102. {
  103. return __virt_to_phys(x);
  104. }
  105. /*
  106. * phys_to_virt - map physical address to virtual
  107. * @address: address to remap
  108. *
  109. * The returned virtual address is a current CPU mapping for
  110. * the memory address given. It is only valid to use this function on
  111. * addresses that have a kernel mapping
  112. *
  113. * This function does not handle bus mappings for DMA transfers. In
  114. * almost all conceivable cases a device driver should not be using
  115. * this function
  116. */
  117. static inline void * phys_to_virt(unsigned long address)
  118. {
  119. return __va(address);
  120. }
  121. /*
  122. * ISA I/O bus memory addresses are 1:1 with the physical address.
  123. */
  124. static inline unsigned long isa_virt_to_bus(volatile void *address)
  125. {
  126. return virt_to_phys(address);
  127. }
  128. static inline void *isa_bus_to_virt(unsigned long address)
  129. {
  130. return phys_to_virt(address);
  131. }
  132. /*
  133. * Change "struct page" to physical address.
  134. */
  135. #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
  136. void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size,
  137. unsigned long prot_val);
  138. void iounmap(const volatile void __iomem *addr);
  139. /*
  140. * ioremap - map bus memory into CPU space
  141. * @offset: bus address of the memory
  142. * @size: size of the resource to map
  143. *
  144. * ioremap performs a platform specific sequence of operations to
  145. * make bus memory CPU accessible via the readb/readw/readl/writeb/
  146. * writew/writel functions and the other mmio helpers. The returned
  147. * address is not guaranteed to be usable directly as a virtual
  148. * address.
  149. */
  150. #define ioremap(offset, size) \
  151. ioremap_prot((offset), (size), _CACHE_UNCACHED)
  152. #define ioremap_uc ioremap
  153. /*
  154. * ioremap_cache - map bus memory into CPU space
  155. * @offset: bus address of the memory
  156. * @size: size of the resource to map
  157. *
  158. * ioremap_cache performs a platform specific sequence of operations to
  159. * make bus memory CPU accessible via the readb/readw/readl/writeb/
  160. * writew/writel functions and the other mmio helpers. The returned
  161. * address is not guaranteed to be usable directly as a virtual
  162. * address.
  163. *
  164. * This version of ioremap ensures that the memory is marked cachable by
  165. * the CPU. Also enables full write-combining. Useful for some
  166. * memory-like regions on I/O busses.
  167. */
  168. #define ioremap_cache(offset, size) \
  169. ioremap_prot((offset), (size), _page_cachable_default)
  170. /*
  171. * ioremap_wc - map bus memory into CPU space
  172. * @offset: bus address of the memory
  173. * @size: size of the resource to map
  174. *
  175. * ioremap_wc performs a platform specific sequence of operations to
  176. * make bus memory CPU accessible via the readb/readw/readl/writeb/
  177. * writew/writel functions and the other mmio helpers. The returned
  178. * address is not guaranteed to be usable directly as a virtual
  179. * address.
  180. *
  181. * This version of ioremap ensures that the memory is marked uncachable
  182. * but accelerated by means of write-combining feature. It is specifically
  183. * useful for PCIe prefetchable windows, which may vastly improve a
  184. * communications performance. If it was determined on boot stage, what
  185. * CPU CCA doesn't support UCA, the method shall fall-back to the
  186. * _CACHE_UNCACHED option (see cpu_probe() method).
  187. */
  188. #define ioremap_wc(offset, size) \
  189. ioremap_prot((offset), (size), boot_cpu_data.writecombine)
  190. #if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON64)
  191. #define war_io_reorder_wmb() wmb()
  192. #else
  193. #define war_io_reorder_wmb() barrier()
  194. #endif
  195. #define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, barrier, relax, irq) \
  196. \
  197. static inline void pfx##write##bwlq(type val, \
  198. volatile void __iomem *mem) \
  199. { \
  200. volatile type *__mem; \
  201. type __val; \
  202. \
  203. if (barrier) \
  204. iobarrier_rw(); \
  205. else \
  206. war_io_reorder_wmb(); \
  207. \
  208. __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
  209. \
  210. __val = pfx##ioswab##bwlq(__mem, val); \
  211. \
  212. if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
  213. *__mem = __val; \
  214. else if (cpu_has_64bits) { \
  215. unsigned long __flags; \
  216. type __tmp; \
  217. \
  218. if (irq) \
  219. local_irq_save(__flags); \
  220. __asm__ __volatile__( \
  221. ".set push" "\t\t# __writeq""\n\t" \
  222. ".set arch=r4000" "\n\t" \
  223. "dsll32 %L0, %L0, 0" "\n\t" \
  224. "dsrl32 %L0, %L0, 0" "\n\t" \
  225. "dsll32 %M0, %M0, 0" "\n\t" \
  226. "or %L0, %L0, %M0" "\n\t" \
  227. "sd %L0, %2" "\n\t" \
  228. ".set pop" "\n" \
  229. : "=r" (__tmp) \
  230. : "0" (__val), "m" (*__mem)); \
  231. if (irq) \
  232. local_irq_restore(__flags); \
  233. } else \
  234. BUG(); \
  235. } \
  236. \
  237. static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
  238. { \
  239. volatile type *__mem; \
  240. type __val; \
  241. \
  242. __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
  243. \
  244. if (barrier) \
  245. iobarrier_rw(); \
  246. \
  247. if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
  248. __val = *__mem; \
  249. else if (cpu_has_64bits) { \
  250. unsigned long __flags; \
  251. \
  252. if (irq) \
  253. local_irq_save(__flags); \
  254. __asm__ __volatile__( \
  255. ".set push" "\t\t# __readq" "\n\t" \
  256. ".set arch=r4000" "\n\t" \
  257. "ld %L0, %1" "\n\t" \
  258. "dsra32 %M0, %L0, 0" "\n\t" \
  259. "sll %L0, %L0, 0" "\n\t" \
  260. ".set pop" "\n" \
  261. : "=r" (__val) \
  262. : "m" (*__mem)); \
  263. if (irq) \
  264. local_irq_restore(__flags); \
  265. } else { \
  266. __val = 0; \
  267. BUG(); \
  268. } \
  269. \
  270. /* prevent prefetching of coherent DMA data prematurely */ \
  271. if (!relax) \
  272. rmb(); \
  273. return pfx##ioswab##bwlq(__mem, __val); \
  274. }
  275. #define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, barrier, relax, p) \
  276. \
  277. static inline void pfx##out##bwlq##p(type val, unsigned long port) \
  278. { \
  279. volatile type *__addr; \
  280. type __val; \
  281. \
  282. if (barrier) \
  283. iobarrier_rw(); \
  284. else \
  285. war_io_reorder_wmb(); \
  286. \
  287. __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
  288. \
  289. __val = pfx##ioswab##bwlq(__addr, val); \
  290. \
  291. /* Really, we want this to be atomic */ \
  292. BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
  293. \
  294. *__addr = __val; \
  295. } \
  296. \
  297. static inline type pfx##in##bwlq##p(unsigned long port) \
  298. { \
  299. volatile type *__addr; \
  300. type __val; \
  301. \
  302. __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
  303. \
  304. BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
  305. \
  306. if (barrier) \
  307. iobarrier_rw(); \
  308. \
  309. __val = *__addr; \
  310. \
  311. /* prevent prefetching of coherent DMA data prematurely */ \
  312. if (!relax) \
  313. rmb(); \
  314. return pfx##ioswab##bwlq(__addr, __val); \
  315. }
  316. #define __BUILD_MEMORY_PFX(bus, bwlq, type, relax) \
  317. \
  318. __BUILD_MEMORY_SINGLE(bus, bwlq, type, 1, relax, 1)
  319. #define BUILDIO_MEM(bwlq, type) \
  320. \
  321. __BUILD_MEMORY_PFX(__raw_, bwlq, type, 0) \
  322. __BUILD_MEMORY_PFX(__relaxed_, bwlq, type, 1) \
  323. __BUILD_MEMORY_PFX(__mem_, bwlq, type, 0) \
  324. __BUILD_MEMORY_PFX(, bwlq, type, 0)
  325. BUILDIO_MEM(b, u8)
  326. BUILDIO_MEM(w, u16)
  327. BUILDIO_MEM(l, u32)
  328. #ifdef CONFIG_64BIT
  329. BUILDIO_MEM(q, u64)
  330. #else
  331. __BUILD_MEMORY_PFX(__raw_, q, u64, 0)
  332. __BUILD_MEMORY_PFX(__mem_, q, u64, 0)
  333. #endif
  334. #define __BUILD_IOPORT_PFX(bus, bwlq, type) \
  335. __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0,) \
  336. __BUILD_IOPORT_SINGLE(bus, bwlq, type, 1, 0, _p)
  337. #define BUILDIO_IOPORT(bwlq, type) \
  338. __BUILD_IOPORT_PFX(, bwlq, type) \
  339. __BUILD_IOPORT_PFX(__mem_, bwlq, type)
  340. BUILDIO_IOPORT(b, u8)
  341. BUILDIO_IOPORT(w, u16)
  342. BUILDIO_IOPORT(l, u32)
  343. #ifdef CONFIG_64BIT
  344. BUILDIO_IOPORT(q, u64)
  345. #endif
  346. #define __BUILDIO(bwlq, type) \
  347. \
  348. __BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 1, 0, 0)
  349. __BUILDIO(q, u64)
  350. #define readb_relaxed __relaxed_readb
  351. #define readw_relaxed __relaxed_readw
  352. #define readl_relaxed __relaxed_readl
  353. #ifdef CONFIG_64BIT
  354. #define readq_relaxed __relaxed_readq
  355. #endif
  356. #define writeb_relaxed __relaxed_writeb
  357. #define writew_relaxed __relaxed_writew
  358. #define writel_relaxed __relaxed_writel
  359. #ifdef CONFIG_64BIT
  360. #define writeq_relaxed __relaxed_writeq
  361. #endif
  362. #define readb_be(addr) \
  363. __raw_readb((__force unsigned *)(addr))
  364. #define readw_be(addr) \
  365. be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
  366. #define readl_be(addr) \
  367. be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
  368. #define readq_be(addr) \
  369. be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
  370. #define writeb_be(val, addr) \
  371. __raw_writeb((val), (__force unsigned *)(addr))
  372. #define writew_be(val, addr) \
  373. __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
  374. #define writel_be(val, addr) \
  375. __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
  376. #define writeq_be(val, addr) \
  377. __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
  378. /*
  379. * Some code tests for these symbols
  380. */
  381. #ifdef CONFIG_64BIT
  382. #define readq readq
  383. #define writeq writeq
  384. #endif
  385. #define __BUILD_MEMORY_STRING(bwlq, type) \
  386. \
  387. static inline void writes##bwlq(volatile void __iomem *mem, \
  388. const void *addr, unsigned int count) \
  389. { \
  390. const volatile type *__addr = addr; \
  391. \
  392. while (count--) { \
  393. __mem_write##bwlq(*__addr, mem); \
  394. __addr++; \
  395. } \
  396. } \
  397. \
  398. static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \
  399. unsigned int count) \
  400. { \
  401. volatile type *__addr = addr; \
  402. \
  403. while (count--) { \
  404. *__addr = __mem_read##bwlq(mem); \
  405. __addr++; \
  406. } \
  407. }
  408. #define __BUILD_IOPORT_STRING(bwlq, type) \
  409. \
  410. static inline void outs##bwlq(unsigned long port, const void *addr, \
  411. unsigned int count) \
  412. { \
  413. const volatile type *__addr = addr; \
  414. \
  415. while (count--) { \
  416. __mem_out##bwlq(*__addr, port); \
  417. __addr++; \
  418. } \
  419. } \
  420. \
  421. static inline void ins##bwlq(unsigned long port, void *addr, \
  422. unsigned int count) \
  423. { \
  424. volatile type *__addr = addr; \
  425. \
  426. while (count--) { \
  427. *__addr = __mem_in##bwlq(port); \
  428. __addr++; \
  429. } \
  430. }
  431. #define BUILDSTRING(bwlq, type) \
  432. \
  433. __BUILD_MEMORY_STRING(bwlq, type) \
  434. __BUILD_IOPORT_STRING(bwlq, type)
  435. BUILDSTRING(b, u8)
  436. BUILDSTRING(w, u16)
  437. BUILDSTRING(l, u32)
  438. #ifdef CONFIG_64BIT
  439. BUILDSTRING(q, u64)
  440. #endif
  441. static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
  442. {
  443. memset((void __force *) addr, val, count);
  444. }
  445. static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
  446. {
  447. memcpy(dst, (void __force *) src, count);
  448. }
  449. static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
  450. {
  451. memcpy((void __force *) dst, src, count);
  452. }
  453. /*
  454. * The caches on some architectures aren't dma-coherent and have need to
  455. * handle this in software. There are three types of operations that
  456. * can be applied to dma buffers.
  457. *
  458. * - dma_cache_wback_inv(start, size) makes caches and coherent by
  459. * writing the content of the caches back to memory, if necessary.
  460. * The function also invalidates the affected part of the caches as
  461. * necessary before DMA transfers from outside to memory.
  462. * - dma_cache_wback(start, size) makes caches and coherent by
  463. * writing the content of the caches back to memory, if necessary.
  464. * The function also invalidates the affected part of the caches as
  465. * necessary before DMA transfers from outside to memory.
  466. * - dma_cache_inv(start, size) invalidates the affected parts of the
  467. * caches. Dirty lines of the caches may be written back or simply
  468. * be discarded. This operation is necessary before dma operations
  469. * to the memory.
  470. *
  471. * This API used to be exported; it now is for arch code internal use only.
  472. */
  473. #ifdef CONFIG_DMA_NONCOHERENT
  474. extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
  475. extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
  476. extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
  477. #define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start, size)
  478. #define dma_cache_wback(start, size) _dma_cache_wback(start, size)
  479. #define dma_cache_inv(start, size) _dma_cache_inv(start, size)
  480. #else /* Sane hardware */
  481. #define dma_cache_wback_inv(start,size) \
  482. do { (void) (start); (void) (size); } while (0)
  483. #define dma_cache_wback(start,size) \
  484. do { (void) (start); (void) (size); } while (0)
  485. #define dma_cache_inv(start,size) \
  486. do { (void) (start); (void) (size); } while (0)
  487. #endif /* CONFIG_DMA_NONCOHERENT */
  488. /*
  489. * Read a 32-bit register that requires a 64-bit read cycle on the bus.
  490. * Avoid interrupt mucking, just adjust the address for 4-byte access.
  491. * Assume the addresses are 8-byte aligned.
  492. */
  493. #ifdef __MIPSEB__
  494. #define __CSR_32_ADJUST 4
  495. #else
  496. #define __CSR_32_ADJUST 0
  497. #endif
  498. #define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
  499. #define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
  500. /*
  501. * Convert a physical pointer to a virtual kernel pointer for /dev/mem
  502. * access
  503. */
  504. #define xlate_dev_mem_ptr(p) __va(p)
  505. void __ioread64_copy(void *to, const void __iomem *from, size_t count);
  506. #endif /* _ASM_IO_H */