cpu.h 16 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * cpu.h: Values of the PRId register used to match up
  4. * various MIPS cpu types.
  5. *
  6. * Copyright (C) 1996 David S. Miller ([email protected])
  7. * Copyright (C) 2004, 2013 Maciej W. Rozycki
  8. */
  9. #ifndef _ASM_CPU_H
  10. #define _ASM_CPU_H
  11. #include <linux/bits.h>
  12. /*
  13. As of the MIPS32 and MIPS64 specs from MTI, the PRId register (CP0
  14. register 15, select 0) is defined in this (backwards compatible) way:
  15. +----------------+----------------+----------------+----------------+
  16. | Company Options| Company ID | Processor ID | Revision |
  17. +----------------+----------------+----------------+----------------+
  18. 31 24 23 16 15 8 7
  19. I don't have docs for all the previous processors, but my impression is
  20. that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
  21. spec.
  22. */
  23. #define PRID_OPT_MASK 0xff000000
  24. /*
  25. * Assigned Company values for bits 23:16 of the PRId register.
  26. */
  27. #define PRID_COMP_MASK 0xff0000
  28. #define PRID_COMP_LEGACY 0x000000
  29. #define PRID_COMP_MIPS 0x010000
  30. #define PRID_COMP_BROADCOM 0x020000
  31. #define PRID_COMP_ALCHEMY 0x030000
  32. #define PRID_COMP_SIBYTE 0x040000
  33. #define PRID_COMP_SANDCRAFT 0x050000
  34. #define PRID_COMP_NXP 0x060000
  35. #define PRID_COMP_TOSHIBA 0x070000
  36. #define PRID_COMP_LSI 0x080000
  37. #define PRID_COMP_LEXRA 0x0b0000
  38. #define PRID_COMP_NETLOGIC 0x0c0000
  39. #define PRID_COMP_CAVIUM 0x0d0000
  40. #define PRID_COMP_LOONGSON 0x140000
  41. #define PRID_COMP_INGENIC_13 0x130000 /* X2000, X2100 */
  42. #define PRID_COMP_INGENIC_D0 0xd00000 /* JZ4730, JZ4740, JZ4750, JZ4755, JZ4760, X1830 */
  43. #define PRID_COMP_INGENIC_D1 0xd10000 /* JZ4770, JZ4775, X1000 */
  44. #define PRID_COMP_INGENIC_E1 0xe10000 /* JZ4780 */
  45. /*
  46. * Assigned Processor ID (implementation) values for bits 15:8 of the PRId
  47. * register. In order to detect a certain CPU type exactly eventually
  48. * additional registers may need to be examined.
  49. */
  50. #define PRID_IMP_MASK 0xff00
  51. /*
  52. * These are valid when 23:16 == PRID_COMP_LEGACY
  53. */
  54. #define PRID_IMP_R2000 0x0100
  55. #define PRID_IMP_AU1_REV1 0x0100
  56. #define PRID_IMP_AU1_REV2 0x0200
  57. #define PRID_IMP_R3000 0x0200 /* Same as R2000A */
  58. #define PRID_IMP_R6000 0x0300 /* Same as R3000A */
  59. #define PRID_IMP_R4000 0x0400
  60. #define PRID_IMP_R6000A 0x0600
  61. #define PRID_IMP_R10000 0x0900
  62. #define PRID_IMP_R4300 0x0b00
  63. #define PRID_IMP_VR41XX 0x0c00
  64. #define PRID_IMP_R12000 0x0e00
  65. #define PRID_IMP_R14000 0x0f00 /* R14K && R16K */
  66. #define PRID_IMP_R8000 0x1000
  67. #define PRID_IMP_PR4450 0x1200
  68. #define PRID_IMP_R4600 0x2000
  69. #define PRID_IMP_R4700 0x2100
  70. #define PRID_IMP_TX39 0x2200
  71. #define PRID_IMP_R4640 0x2200
  72. #define PRID_IMP_R4650 0x2200 /* Same as R4640 */
  73. #define PRID_IMP_R5000 0x2300
  74. #define PRID_IMP_TX49 0x2d00
  75. #define PRID_IMP_SONIC 0x2400
  76. #define PRID_IMP_MAGIC 0x2500
  77. #define PRID_IMP_RM7000 0x2700
  78. #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
  79. #define PRID_IMP_RM9000 0x3400
  80. #define PRID_IMP_LOONGSON_32 0x4200 /* Loongson-1 */
  81. #define PRID_IMP_R5432 0x5400
  82. #define PRID_IMP_R5500 0x5500
  83. #define PRID_IMP_LOONGSON_64R 0x6100 /* Reduced Loongson-2 */
  84. #define PRID_IMP_LOONGSON_64C 0x6300 /* Classic Loongson-2 and Loongson-3 */
  85. #define PRID_IMP_LOONGSON_64G 0xc000 /* Generic Loongson-2 and Loongson-3 */
  86. #define PRID_IMP_UNKNOWN 0xff00
  87. /*
  88. * These are the PRID's for when 23:16 == PRID_COMP_MIPS
  89. */
  90. #define PRID_IMP_QEMU_GENERIC 0x0000
  91. #define PRID_IMP_4KC 0x8000
  92. #define PRID_IMP_5KC 0x8100
  93. #define PRID_IMP_20KC 0x8200
  94. #define PRID_IMP_4KEC 0x8400
  95. #define PRID_IMP_4KSC 0x8600
  96. #define PRID_IMP_25KF 0x8800
  97. #define PRID_IMP_5KE 0x8900
  98. #define PRID_IMP_4KECR2 0x9000
  99. #define PRID_IMP_4KEMPR2 0x9100
  100. #define PRID_IMP_4KSD 0x9200
  101. #define PRID_IMP_24K 0x9300
  102. #define PRID_IMP_34K 0x9500
  103. #define PRID_IMP_24KE 0x9600
  104. #define PRID_IMP_74K 0x9700
  105. #define PRID_IMP_1004K 0x9900
  106. #define PRID_IMP_1074K 0x9a00
  107. #define PRID_IMP_M14KC 0x9c00
  108. #define PRID_IMP_M14KEC 0x9e00
  109. #define PRID_IMP_INTERAPTIV_UP 0xa000
  110. #define PRID_IMP_INTERAPTIV_MP 0xa100
  111. #define PRID_IMP_PROAPTIV_UP 0xa200
  112. #define PRID_IMP_PROAPTIV_MP 0xa300
  113. #define PRID_IMP_P6600 0xa400
  114. #define PRID_IMP_M5150 0xa700
  115. #define PRID_IMP_P5600 0xa800
  116. #define PRID_IMP_I6400 0xa900
  117. #define PRID_IMP_M6250 0xab00
  118. #define PRID_IMP_I6500 0xb000
  119. /*
  120. * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
  121. */
  122. #define PRID_IMP_SB1 0x0100
  123. #define PRID_IMP_SB1A 0x1100
  124. /*
  125. * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
  126. */
  127. #define PRID_IMP_SR71000 0x0400
  128. /*
  129. * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
  130. */
  131. #define PRID_IMP_BMIPS32_REV4 0x4000
  132. #define PRID_IMP_BMIPS32_REV8 0x8000
  133. #define PRID_IMP_BMIPS3300 0x9000
  134. #define PRID_IMP_BMIPS3300_ALT 0x9100
  135. #define PRID_IMP_BMIPS3300_BUG 0x0000
  136. #define PRID_IMP_BMIPS43XX 0xa000
  137. #define PRID_IMP_BMIPS5000 0x5a00
  138. #define PRID_IMP_BMIPS5200 0x5b00
  139. #define PRID_REV_BMIPS4380_LO 0x0040
  140. #define PRID_REV_BMIPS4380_HI 0x006f
  141. /*
  142. * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
  143. */
  144. #define PRID_IMP_CAVIUM_CN38XX 0x0000
  145. #define PRID_IMP_CAVIUM_CN31XX 0x0100
  146. #define PRID_IMP_CAVIUM_CN30XX 0x0200
  147. #define PRID_IMP_CAVIUM_CN58XX 0x0300
  148. #define PRID_IMP_CAVIUM_CN56XX 0x0400
  149. #define PRID_IMP_CAVIUM_CN50XX 0x0600
  150. #define PRID_IMP_CAVIUM_CN52XX 0x0700
  151. #define PRID_IMP_CAVIUM_CN63XX 0x9000
  152. #define PRID_IMP_CAVIUM_CN68XX 0x9100
  153. #define PRID_IMP_CAVIUM_CN66XX 0x9200
  154. #define PRID_IMP_CAVIUM_CN61XX 0x9300
  155. #define PRID_IMP_CAVIUM_CNF71XX 0x9400
  156. #define PRID_IMP_CAVIUM_CN78XX 0x9500
  157. #define PRID_IMP_CAVIUM_CN70XX 0x9600
  158. #define PRID_IMP_CAVIUM_CN73XX 0x9700
  159. #define PRID_IMP_CAVIUM_CNF75XX 0x9800
  160. /*
  161. * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_*
  162. */
  163. #define PRID_IMP_XBURST_REV1 0x0200 /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
  164. #define PRID_IMP_XBURST_REV2 0x0100 /* XBurst®1 with MXU2.0 SIMD ISA */
  165. #define PRID_IMP_XBURST2 0x2000 /* XBurst®2 with MXU2.1 SIMD ISA */
  166. /*
  167. * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
  168. */
  169. #define PRID_IMP_NETLOGIC_XLR732 0x0000
  170. #define PRID_IMP_NETLOGIC_XLR716 0x0200
  171. #define PRID_IMP_NETLOGIC_XLR532 0x0900
  172. #define PRID_IMP_NETLOGIC_XLR308 0x0600
  173. #define PRID_IMP_NETLOGIC_XLR532C 0x0800
  174. #define PRID_IMP_NETLOGIC_XLR516C 0x0a00
  175. #define PRID_IMP_NETLOGIC_XLR508C 0x0b00
  176. #define PRID_IMP_NETLOGIC_XLR308C 0x0f00
  177. #define PRID_IMP_NETLOGIC_XLS608 0x8000
  178. #define PRID_IMP_NETLOGIC_XLS408 0x8800
  179. #define PRID_IMP_NETLOGIC_XLS404 0x8c00
  180. #define PRID_IMP_NETLOGIC_XLS208 0x8e00
  181. #define PRID_IMP_NETLOGIC_XLS204 0x8f00
  182. #define PRID_IMP_NETLOGIC_XLS108 0xce00
  183. #define PRID_IMP_NETLOGIC_XLS104 0xcf00
  184. #define PRID_IMP_NETLOGIC_XLS616B 0x4000
  185. #define PRID_IMP_NETLOGIC_XLS608B 0x4a00
  186. #define PRID_IMP_NETLOGIC_XLS416B 0x4400
  187. #define PRID_IMP_NETLOGIC_XLS412B 0x4c00
  188. #define PRID_IMP_NETLOGIC_XLS408B 0x4e00
  189. #define PRID_IMP_NETLOGIC_XLS404B 0x4f00
  190. #define PRID_IMP_NETLOGIC_AU13XX 0x8000
  191. #define PRID_IMP_NETLOGIC_XLP8XX 0x1000
  192. #define PRID_IMP_NETLOGIC_XLP3XX 0x1100
  193. #define PRID_IMP_NETLOGIC_XLP2XX 0x1200
  194. #define PRID_IMP_NETLOGIC_XLP9XX 0x1500
  195. #define PRID_IMP_NETLOGIC_XLP5XX 0x1300
  196. /*
  197. * Particular Revision values for bits 7:0 of the PRId register.
  198. */
  199. #define PRID_REV_MASK 0x00ff
  200. /*
  201. * Definitions for 7:0 on legacy processors
  202. */
  203. #define PRID_REV_TX4927 0x0022
  204. #define PRID_REV_TX4937 0x0030
  205. #define PRID_REV_R4400 0x0040
  206. #define PRID_REV_R3000A 0x0030
  207. #define PRID_REV_R3000 0x0020
  208. #define PRID_REV_R2000A 0x0010
  209. #define PRID_REV_TX3912 0x0010
  210. #define PRID_REV_TX3922 0x0030
  211. #define PRID_REV_TX3927 0x0040
  212. #define PRID_REV_VR4111 0x0050
  213. #define PRID_REV_VR4181 0x0050 /* Same as VR4111 */
  214. #define PRID_REV_VR4121 0x0060
  215. #define PRID_REV_VR4122 0x0070
  216. #define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
  217. #define PRID_REV_VR4130 0x0080
  218. #define PRID_REV_34K_V1_0_2 0x0022
  219. #define PRID_REV_LOONGSON1B 0x0020
  220. #define PRID_REV_LOONGSON1C 0x0020 /* Same as Loongson-1B */
  221. #define PRID_REV_LOONGSON2E 0x0002
  222. #define PRID_REV_LOONGSON2F 0x0003
  223. #define PRID_REV_LOONGSON2K_R1_0 0x0000
  224. #define PRID_REV_LOONGSON2K_R1_1 0x0001
  225. #define PRID_REV_LOONGSON2K_R1_2 0x0002
  226. #define PRID_REV_LOONGSON2K_R1_3 0x0003
  227. #define PRID_REV_LOONGSON3A_R1 0x0005
  228. #define PRID_REV_LOONGSON3B_R1 0x0006
  229. #define PRID_REV_LOONGSON3B_R2 0x0007
  230. #define PRID_REV_LOONGSON3A_R2_0 0x0008
  231. #define PRID_REV_LOONGSON3A_R3_0 0x0009
  232. #define PRID_REV_LOONGSON3A_R2_1 0x000c
  233. #define PRID_REV_LOONGSON3A_R3_1 0x000d
  234. /*
  235. * Older processors used to encode processor version and revision in two
  236. * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
  237. * have switched to use the 8-bits as 3:3:2 bitfield with the last field as
  238. * the patch number. *ARGH*
  239. */
  240. #define PRID_REV_ENCODE_44(ver, rev) \
  241. ((ver) << 4 | (rev))
  242. #define PRID_REV_ENCODE_332(ver, rev, patch) \
  243. ((ver) << 5 | (rev) << 2 | (patch))
  244. /*
  245. * FPU implementation/revision register (CP1 control register 0).
  246. *
  247. * +---------------------------------+----------------+----------------+
  248. * | 0 | Implementation | Revision |
  249. * +---------------------------------+----------------+----------------+
  250. * 31 16 15 8 7 0
  251. */
  252. #define FPIR_IMP_MASK 0xff00
  253. #define FPIR_IMP_NONE 0x0000
  254. #if !defined(__ASSEMBLY__)
  255. enum cpu_type_enum {
  256. CPU_UNKNOWN,
  257. /*
  258. * R2000 class processors
  259. */
  260. CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052,
  261. CPU_R3081, CPU_R3081E,
  262. /*
  263. * R4000 class processors
  264. */
  265. CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
  266. CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
  267. CPU_R4700, CPU_R5000, CPU_R5500, CPU_NEVADA, CPU_R10000,
  268. CPU_R12000, CPU_R14000, CPU_R16000, CPU_RM7000,
  269. CPU_SR71000, CPU_TX49XX,
  270. /*
  271. * MIPS32 class processors
  272. */
  273. CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
  274. CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
  275. CPU_BMIPS4380, CPU_BMIPS5000, CPU_XBURST, CPU_LOONGSON32, CPU_M14KC,
  276. CPU_M14KEC, CPU_INTERAPTIV, CPU_P5600, CPU_PROAPTIV, CPU_1074K,
  277. CPU_M5150, CPU_I6400, CPU_P6600, CPU_M6250,
  278. /*
  279. * MIPS64 class processors
  280. */
  281. CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2EF,
  282. CPU_LOONGSON64, CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
  283. CPU_CAVIUM_OCTEON2, CPU_CAVIUM_OCTEON3, CPU_I6500,
  284. CPU_QEMU_GENERIC,
  285. CPU_LAST
  286. };
  287. #endif /* !__ASSEMBLY */
  288. /*
  289. * ISA Level encodings
  290. *
  291. */
  292. #define MIPS_CPU_ISA_II 0x00000001
  293. #define MIPS_CPU_ISA_III 0x00000002
  294. #define MIPS_CPU_ISA_IV 0x00000004
  295. #define MIPS_CPU_ISA_V 0x00000008
  296. #define MIPS_CPU_ISA_M32R1 0x00000010
  297. #define MIPS_CPU_ISA_M32R2 0x00000020
  298. #define MIPS_CPU_ISA_M64R1 0x00000040
  299. #define MIPS_CPU_ISA_M64R2 0x00000080
  300. #define MIPS_CPU_ISA_M32R5 0x00000100
  301. #define MIPS_CPU_ISA_M64R5 0x00000200
  302. #define MIPS_CPU_ISA_M32R6 0x00000400
  303. #define MIPS_CPU_ISA_M64R6 0x00000800
  304. #define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_II | MIPS_CPU_ISA_M32R1 | \
  305. MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M32R6)
  306. #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
  307. MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2 | \
  308. MIPS_CPU_ISA_M64R5 | MIPS_CPU_ISA_M64R6)
  309. /*
  310. * CPU Option encodings
  311. */
  312. #define MIPS_CPU_TLB BIT_ULL( 0) /* CPU has TLB */
  313. #define MIPS_CPU_4KEX BIT_ULL( 1) /* "R4K" exception model */
  314. #define MIPS_CPU_3K_CACHE BIT_ULL( 2) /* R3000-style caches */
  315. #define MIPS_CPU_4K_CACHE BIT_ULL( 3) /* R4000-style caches */
  316. #define MIPS_CPU_FPU BIT_ULL( 5) /* CPU has FPU */
  317. #define MIPS_CPU_32FPR BIT_ULL( 6) /* 32 dbl. prec. FP registers */
  318. #define MIPS_CPU_COUNTER BIT_ULL( 7) /* Cycle count/compare */
  319. #define MIPS_CPU_WATCH BIT_ULL( 8) /* watchpoint registers */
  320. #define MIPS_CPU_DIVEC BIT_ULL( 9) /* dedicated interrupt vector */
  321. #define MIPS_CPU_VCE BIT_ULL(10) /* virt. coherence conflict possible */
  322. #define MIPS_CPU_CACHE_CDEX_P BIT_ULL(11) /* Create_Dirty_Exclusive CACHE op */
  323. #define MIPS_CPU_CACHE_CDEX_S BIT_ULL(12) /* ... same for seconary cache ... */
  324. #define MIPS_CPU_MCHECK BIT_ULL(13) /* Machine check exception */
  325. #define MIPS_CPU_EJTAG BIT_ULL(14) /* EJTAG exception */
  326. #define MIPS_CPU_NOFPUEX BIT_ULL(15) /* no FPU exception */
  327. #define MIPS_CPU_LLSC BIT_ULL(16) /* CPU has ll/sc instructions */
  328. #define MIPS_CPU_INCLUSIVE_CACHES BIT_ULL(17) /* P-cache subset enforced */
  329. #define MIPS_CPU_PREFETCH BIT_ULL(18) /* CPU has usable prefetch */
  330. #define MIPS_CPU_VINT BIT_ULL(19) /* CPU supports MIPSR2 vectored interrupts */
  331. #define MIPS_CPU_VEIC BIT_ULL(20) /* CPU supports MIPSR2 external interrupt controller mode */
  332. #define MIPS_CPU_ULRI BIT_ULL(21) /* CPU has ULRI feature */
  333. #define MIPS_CPU_PCI BIT_ULL(22) /* CPU has Perf Ctr Int indicator */
  334. #define MIPS_CPU_RIXI BIT_ULL(23) /* CPU has TLB Read/eXec Inhibit */
  335. #define MIPS_CPU_MICROMIPS BIT_ULL(24) /* CPU has microMIPS capability */
  336. #define MIPS_CPU_TLBINV BIT_ULL(25) /* CPU supports TLBINV/F */
  337. #define MIPS_CPU_SEGMENTS BIT_ULL(26) /* CPU supports Segmentation Control registers */
  338. #define MIPS_CPU_EVA BIT_ULL(27) /* CPU supports Enhanced Virtual Addressing */
  339. #define MIPS_CPU_HTW BIT_ULL(28) /* CPU support Hardware Page Table Walker */
  340. #define MIPS_CPU_RIXIEX BIT_ULL(29) /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
  341. #define MIPS_CPU_MAAR BIT_ULL(30) /* MAAR(I) registers are present */
  342. #define MIPS_CPU_FRE BIT_ULL(31) /* FRE & UFE bits implemented */
  343. #define MIPS_CPU_RW_LLB BIT_ULL(32) /* LLADDR/LLB writes are allowed */
  344. #define MIPS_CPU_LPA BIT_ULL(33) /* CPU supports Large Physical Addressing */
  345. #define MIPS_CPU_CDMM BIT_ULL(34) /* CPU has Common Device Memory Map */
  346. #define MIPS_CPU_SP BIT_ULL(36) /* Small (1KB) page support */
  347. #define MIPS_CPU_FTLB BIT_ULL(37) /* CPU has Fixed-page-size TLB */
  348. #define MIPS_CPU_NAN_LEGACY BIT_ULL(38) /* Legacy NaN implemented */
  349. #define MIPS_CPU_NAN_2008 BIT_ULL(39) /* 2008 NaN implemented */
  350. #define MIPS_CPU_VP BIT_ULL(40) /* MIPSr6 Virtual Processors (multi-threading) */
  351. #define MIPS_CPU_LDPTE BIT_ULL(41) /* CPU has ldpte/lddir instructions */
  352. #define MIPS_CPU_MVH BIT_ULL(42) /* CPU supports MFHC0/MTHC0 */
  353. #define MIPS_CPU_EBASE_WG BIT_ULL(43) /* CPU has EBase.WG */
  354. #define MIPS_CPU_BADINSTR BIT_ULL(44) /* CPU has BadInstr register */
  355. #define MIPS_CPU_BADINSTRP BIT_ULL(45) /* CPU has BadInstrP register */
  356. #define MIPS_CPU_CTXTC BIT_ULL(46) /* CPU has [X]ConfigContext registers */
  357. #define MIPS_CPU_PERF BIT_ULL(47) /* CPU has MIPS performance counters */
  358. #define MIPS_CPU_GUESTCTL0EXT BIT_ULL(48) /* CPU has VZ GuestCtl0Ext register */
  359. #define MIPS_CPU_GUESTCTL1 BIT_ULL(49) /* CPU has VZ GuestCtl1 register */
  360. #define MIPS_CPU_GUESTCTL2 BIT_ULL(50) /* CPU has VZ GuestCtl2 register */
  361. #define MIPS_CPU_GUESTID BIT_ULL(51) /* CPU uses VZ ASE GuestID feature */
  362. #define MIPS_CPU_DRG BIT_ULL(52) /* CPU has VZ Direct Root to Guest (DRG) */
  363. #define MIPS_CPU_UFR BIT_ULL(53) /* CPU supports User mode FR switching */
  364. #define MIPS_CPU_SHARED_FTLB_RAM \
  365. BIT_ULL(54) /* CPU shares FTLB RAM with another */
  366. #define MIPS_CPU_SHARED_FTLB_ENTRIES \
  367. BIT_ULL(55) /* CPU shares FTLB entries with another */
  368. #define MIPS_CPU_MT_PER_TC_PERF_COUNTERS \
  369. BIT_ULL(56) /* CPU has perf counters implemented per TC (MIPSMT ASE) */
  370. #define MIPS_CPU_MMID BIT_ULL(57) /* CPU supports MemoryMapIDs */
  371. #define MIPS_CPU_MM_SYSAD BIT_ULL(58) /* CPU supports write-through SysAD Valid merge */
  372. #define MIPS_CPU_MM_FULL BIT_ULL(59) /* CPU supports write-through full merge */
  373. #define MIPS_CPU_MAC_2008_ONLY BIT_ULL(60) /* CPU Only support MAC2008 Fused multiply-add instruction */
  374. #define MIPS_CPU_FTLBPAREX BIT_ULL(61) /* CPU has FTLB parity exception */
  375. #define MIPS_CPU_GSEXCEX BIT_ULL(62) /* CPU has GSExc exception */
  376. /*
  377. * CPU ASE encodings
  378. */
  379. #define MIPS_ASE_MIPS16 0x00000001 /* code compression */
  380. #define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */
  381. #define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */
  382. #define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */
  383. #define MIPS_ASE_DSP 0x00000010 /* Signal Processing ASE */
  384. #define MIPS_ASE_MIPSMT 0x00000020 /* CPU supports MIPS MT */
  385. #define MIPS_ASE_DSP2P 0x00000040 /* Signal Processing ASE Rev 2 */
  386. #define MIPS_ASE_VZ 0x00000080 /* Virtualization ASE */
  387. #define MIPS_ASE_MSA 0x00000100 /* MIPS SIMD Architecture */
  388. #define MIPS_ASE_DSP3 0x00000200 /* Signal Processing ASE Rev 3*/
  389. #define MIPS_ASE_MIPS16E2 0x00000400 /* MIPS16e2 */
  390. #define MIPS_ASE_LOONGSON_MMI 0x00000800 /* Loongson MultiMedia extensions Instructions */
  391. #define MIPS_ASE_LOONGSON_CAM 0x00001000 /* Loongson CAM */
  392. #define MIPS_ASE_LOONGSON_EXT 0x00002000 /* Loongson EXTensions */
  393. #define MIPS_ASE_LOONGSON_EXT2 0x00004000 /* Loongson EXTensions R2 */
  394. #endif /* _ASM_CPU_H */