branch.h 2.4 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 1996, 1997, 1998, 2001 by Ralf Baechle
  7. */
  8. #ifndef _ASM_BRANCH_H
  9. #define _ASM_BRANCH_H
  10. #include <asm/cpu-features.h>
  11. #include <asm/mipsregs.h>
  12. #include <asm/ptrace.h>
  13. #include <asm/inst.h>
  14. extern int __isa_exception_epc(struct pt_regs *regs);
  15. extern int __compute_return_epc(struct pt_regs *regs);
  16. extern int __compute_return_epc_for_insn(struct pt_regs *regs,
  17. union mips_instruction insn);
  18. extern int __microMIPS_compute_return_epc(struct pt_regs *regs);
  19. extern int __MIPS16e_compute_return_epc(struct pt_regs *regs);
  20. /*
  21. * microMIPS bitfields
  22. */
  23. #define MM_POOL32A_MINOR_MASK 0x3f
  24. #define MM_POOL32A_MINOR_SHIFT 0x6
  25. #define MM_MIPS32_COND_FC 0x30
  26. int isBranchInstr(struct pt_regs *regs,
  27. struct mm_decoded_insn dec_insn, unsigned long *contpc);
  28. extern int __mm_isBranchInstr(struct pt_regs *regs,
  29. struct mm_decoded_insn dec_insn, unsigned long *contpc);
  30. static inline int mm_isBranchInstr(struct pt_regs *regs,
  31. struct mm_decoded_insn dec_insn, unsigned long *contpc)
  32. {
  33. if (!cpu_has_mmips)
  34. return 0;
  35. return __mm_isBranchInstr(regs, dec_insn, contpc);
  36. }
  37. static inline int delay_slot(struct pt_regs *regs)
  38. {
  39. return regs->cp0_cause & CAUSEF_BD;
  40. }
  41. static inline void clear_delay_slot(struct pt_regs *regs)
  42. {
  43. regs->cp0_cause &= ~CAUSEF_BD;
  44. }
  45. static inline void set_delay_slot(struct pt_regs *regs)
  46. {
  47. regs->cp0_cause |= CAUSEF_BD;
  48. }
  49. static inline unsigned long exception_epc(struct pt_regs *regs)
  50. {
  51. if (likely(!delay_slot(regs)))
  52. return regs->cp0_epc;
  53. if (get_isa16_mode(regs->cp0_epc))
  54. return __isa_exception_epc(regs);
  55. return regs->cp0_epc + 4;
  56. }
  57. #define BRANCH_LIKELY_TAKEN 0x0001
  58. static inline int compute_return_epc(struct pt_regs *regs)
  59. {
  60. if (get_isa16_mode(regs->cp0_epc)) {
  61. if (cpu_has_mmips)
  62. return __microMIPS_compute_return_epc(regs);
  63. if (cpu_has_mips16)
  64. return __MIPS16e_compute_return_epc(regs);
  65. } else if (!delay_slot(regs)) {
  66. regs->cp0_epc += 4;
  67. return 0;
  68. }
  69. return __compute_return_epc(regs);
  70. }
  71. static inline int MIPS16e_compute_return_epc(struct pt_regs *regs,
  72. union mips16e_instruction *inst)
  73. {
  74. if (likely(!delay_slot(regs))) {
  75. if (inst->ri.opcode == MIPS16e_extend_op) {
  76. regs->cp0_epc += 4;
  77. return 0;
  78. }
  79. regs->cp0_epc += 2;
  80. return 0;
  81. }
  82. return __MIPS16e_compute_return_epc(regs);
  83. }
  84. #endif /* _ASM_BRANCH_H */