atomic.h 8.1 KB

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  1. /*
  2. * Atomic operations that C can't guarantee us. Useful for
  3. * resource counting etc..
  4. *
  5. * But use these as seldom as possible since they are much more slower
  6. * than regular operations.
  7. *
  8. * This file is subject to the terms and conditions of the GNU General Public
  9. * License. See the file "COPYING" in the main directory of this archive
  10. * for more details.
  11. *
  12. * Copyright (C) 1996, 97, 99, 2000, 03, 04, 06 by Ralf Baechle
  13. */
  14. #ifndef _ASM_ATOMIC_H
  15. #define _ASM_ATOMIC_H
  16. #include <linux/irqflags.h>
  17. #include <linux/types.h>
  18. #include <asm/asm.h>
  19. #include <asm/barrier.h>
  20. #include <asm/compiler.h>
  21. #include <asm/cpu-features.h>
  22. #include <asm/cmpxchg.h>
  23. #include <asm/sync.h>
  24. #define ATOMIC_OPS(pfx, type) \
  25. static __always_inline type arch_##pfx##_read(const pfx##_t *v) \
  26. { \
  27. return READ_ONCE(v->counter); \
  28. } \
  29. \
  30. static __always_inline void arch_##pfx##_set(pfx##_t *v, type i) \
  31. { \
  32. WRITE_ONCE(v->counter, i); \
  33. } \
  34. \
  35. static __always_inline type \
  36. arch_##pfx##_cmpxchg(pfx##_t *v, type o, type n) \
  37. { \
  38. return arch_cmpxchg(&v->counter, o, n); \
  39. } \
  40. \
  41. static __always_inline type arch_##pfx##_xchg(pfx##_t *v, type n) \
  42. { \
  43. return arch_xchg(&v->counter, n); \
  44. }
  45. ATOMIC_OPS(atomic, int)
  46. #ifdef CONFIG_64BIT
  47. # define ATOMIC64_INIT(i) { (i) }
  48. ATOMIC_OPS(atomic64, s64)
  49. #endif
  50. #define ATOMIC_OP(pfx, op, type, c_op, asm_op, ll, sc) \
  51. static __inline__ void arch_##pfx##_##op(type i, pfx##_t * v) \
  52. { \
  53. type temp; \
  54. \
  55. if (!kernel_uses_llsc) { \
  56. unsigned long flags; \
  57. \
  58. raw_local_irq_save(flags); \
  59. v->counter c_op i; \
  60. raw_local_irq_restore(flags); \
  61. return; \
  62. } \
  63. \
  64. __asm__ __volatile__( \
  65. " .set push \n" \
  66. " .set " MIPS_ISA_LEVEL " \n" \
  67. " " __SYNC(full, loongson3_war) " \n" \
  68. "1: " #ll " %0, %1 # " #pfx "_" #op " \n" \
  69. " " #asm_op " %0, %2 \n" \
  70. " " #sc " %0, %1 \n" \
  71. "\t" __stringify(SC_BEQZ) " %0, 1b \n" \
  72. " .set pop \n" \
  73. : "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
  74. : "Ir" (i) : __LLSC_CLOBBER); \
  75. }
  76. #define ATOMIC_OP_RETURN(pfx, op, type, c_op, asm_op, ll, sc) \
  77. static __inline__ type \
  78. arch_##pfx##_##op##_return_relaxed(type i, pfx##_t * v) \
  79. { \
  80. type temp, result; \
  81. \
  82. if (!kernel_uses_llsc) { \
  83. unsigned long flags; \
  84. \
  85. raw_local_irq_save(flags); \
  86. result = v->counter; \
  87. result c_op i; \
  88. v->counter = result; \
  89. raw_local_irq_restore(flags); \
  90. return result; \
  91. } \
  92. \
  93. __asm__ __volatile__( \
  94. " .set push \n" \
  95. " .set " MIPS_ISA_LEVEL " \n" \
  96. " " __SYNC(full, loongson3_war) " \n" \
  97. "1: " #ll " %1, %2 # " #pfx "_" #op "_return\n" \
  98. " " #asm_op " %0, %1, %3 \n" \
  99. " " #sc " %0, %2 \n" \
  100. "\t" __stringify(SC_BEQZ) " %0, 1b \n" \
  101. " " #asm_op " %0, %1, %3 \n" \
  102. " .set pop \n" \
  103. : "=&r" (result), "=&r" (temp), \
  104. "+" GCC_OFF_SMALL_ASM() (v->counter) \
  105. : "Ir" (i) : __LLSC_CLOBBER); \
  106. \
  107. return result; \
  108. }
  109. #define ATOMIC_FETCH_OP(pfx, op, type, c_op, asm_op, ll, sc) \
  110. static __inline__ type \
  111. arch_##pfx##_fetch_##op##_relaxed(type i, pfx##_t * v) \
  112. { \
  113. int temp, result; \
  114. \
  115. if (!kernel_uses_llsc) { \
  116. unsigned long flags; \
  117. \
  118. raw_local_irq_save(flags); \
  119. result = v->counter; \
  120. v->counter c_op i; \
  121. raw_local_irq_restore(flags); \
  122. return result; \
  123. } \
  124. \
  125. __asm__ __volatile__( \
  126. " .set push \n" \
  127. " .set " MIPS_ISA_LEVEL " \n" \
  128. " " __SYNC(full, loongson3_war) " \n" \
  129. "1: " #ll " %1, %2 # " #pfx "_fetch_" #op "\n" \
  130. " " #asm_op " %0, %1, %3 \n" \
  131. " " #sc " %0, %2 \n" \
  132. "\t" __stringify(SC_BEQZ) " %0, 1b \n" \
  133. " .set pop \n" \
  134. " move %0, %1 \n" \
  135. : "=&r" (result), "=&r" (temp), \
  136. "+" GCC_OFF_SMALL_ASM() (v->counter) \
  137. : "Ir" (i) : __LLSC_CLOBBER); \
  138. \
  139. return result; \
  140. }
  141. #undef ATOMIC_OPS
  142. #define ATOMIC_OPS(pfx, op, type, c_op, asm_op, ll, sc) \
  143. ATOMIC_OP(pfx, op, type, c_op, asm_op, ll, sc) \
  144. ATOMIC_OP_RETURN(pfx, op, type, c_op, asm_op, ll, sc) \
  145. ATOMIC_FETCH_OP(pfx, op, type, c_op, asm_op, ll, sc)
  146. ATOMIC_OPS(atomic, add, int, +=, addu, ll, sc)
  147. ATOMIC_OPS(atomic, sub, int, -=, subu, ll, sc)
  148. #define arch_atomic_add_return_relaxed arch_atomic_add_return_relaxed
  149. #define arch_atomic_sub_return_relaxed arch_atomic_sub_return_relaxed
  150. #define arch_atomic_fetch_add_relaxed arch_atomic_fetch_add_relaxed
  151. #define arch_atomic_fetch_sub_relaxed arch_atomic_fetch_sub_relaxed
  152. #ifdef CONFIG_64BIT
  153. ATOMIC_OPS(atomic64, add, s64, +=, daddu, lld, scd)
  154. ATOMIC_OPS(atomic64, sub, s64, -=, dsubu, lld, scd)
  155. # define arch_atomic64_add_return_relaxed arch_atomic64_add_return_relaxed
  156. # define arch_atomic64_sub_return_relaxed arch_atomic64_sub_return_relaxed
  157. # define arch_atomic64_fetch_add_relaxed arch_atomic64_fetch_add_relaxed
  158. # define arch_atomic64_fetch_sub_relaxed arch_atomic64_fetch_sub_relaxed
  159. #endif /* CONFIG_64BIT */
  160. #undef ATOMIC_OPS
  161. #define ATOMIC_OPS(pfx, op, type, c_op, asm_op, ll, sc) \
  162. ATOMIC_OP(pfx, op, type, c_op, asm_op, ll, sc) \
  163. ATOMIC_FETCH_OP(pfx, op, type, c_op, asm_op, ll, sc)
  164. ATOMIC_OPS(atomic, and, int, &=, and, ll, sc)
  165. ATOMIC_OPS(atomic, or, int, |=, or, ll, sc)
  166. ATOMIC_OPS(atomic, xor, int, ^=, xor, ll, sc)
  167. #define arch_atomic_fetch_and_relaxed arch_atomic_fetch_and_relaxed
  168. #define arch_atomic_fetch_or_relaxed arch_atomic_fetch_or_relaxed
  169. #define arch_atomic_fetch_xor_relaxed arch_atomic_fetch_xor_relaxed
  170. #ifdef CONFIG_64BIT
  171. ATOMIC_OPS(atomic64, and, s64, &=, and, lld, scd)
  172. ATOMIC_OPS(atomic64, or, s64, |=, or, lld, scd)
  173. ATOMIC_OPS(atomic64, xor, s64, ^=, xor, lld, scd)
  174. # define arch_atomic64_fetch_and_relaxed arch_atomic64_fetch_and_relaxed
  175. # define arch_atomic64_fetch_or_relaxed arch_atomic64_fetch_or_relaxed
  176. # define arch_atomic64_fetch_xor_relaxed arch_atomic64_fetch_xor_relaxed
  177. #endif
  178. #undef ATOMIC_OPS
  179. #undef ATOMIC_FETCH_OP
  180. #undef ATOMIC_OP_RETURN
  181. #undef ATOMIC_OP
  182. /*
  183. * atomic_sub_if_positive - conditionally subtract integer from atomic variable
  184. * @i: integer value to subtract
  185. * @v: pointer of type atomic_t
  186. *
  187. * Atomically test @v and subtract @i if @v is greater or equal than @i.
  188. * The function returns the old value of @v minus @i.
  189. */
  190. #define ATOMIC_SIP_OP(pfx, type, op, ll, sc) \
  191. static __inline__ type arch_##pfx##_sub_if_positive(type i, pfx##_t * v) \
  192. { \
  193. type temp, result; \
  194. \
  195. smp_mb__before_atomic(); \
  196. \
  197. if (!kernel_uses_llsc) { \
  198. unsigned long flags; \
  199. \
  200. raw_local_irq_save(flags); \
  201. result = v->counter; \
  202. result -= i; \
  203. if (result >= 0) \
  204. v->counter = result; \
  205. raw_local_irq_restore(flags); \
  206. smp_mb__after_atomic(); \
  207. return result; \
  208. } \
  209. \
  210. __asm__ __volatile__( \
  211. " .set push \n" \
  212. " .set " MIPS_ISA_LEVEL " \n" \
  213. " " __SYNC(full, loongson3_war) " \n" \
  214. "1: " #ll " %1, %2 # atomic_sub_if_positive\n" \
  215. " .set pop \n" \
  216. " " #op " %0, %1, %3 \n" \
  217. " move %1, %0 \n" \
  218. " bltz %0, 2f \n" \
  219. " .set push \n" \
  220. " .set " MIPS_ISA_LEVEL " \n" \
  221. " " #sc " %1, %2 \n" \
  222. " " __stringify(SC_BEQZ) " %1, 1b \n" \
  223. "2: " __SYNC(full, loongson3_war) " \n" \
  224. " .set pop \n" \
  225. : "=&r" (result), "=&r" (temp), \
  226. "+" GCC_OFF_SMALL_ASM() (v->counter) \
  227. : "Ir" (i) \
  228. : __LLSC_CLOBBER); \
  229. \
  230. /* \
  231. * In the Loongson3 workaround case we already have a \
  232. * completion barrier at 2: above, which is needed due to the \
  233. * bltz that can branch to code outside of the LL/SC loop. As \
  234. * such, we don't need to emit another barrier here. \
  235. */ \
  236. if (__SYNC_loongson3_war == 0) \
  237. smp_mb__after_atomic(); \
  238. \
  239. return result; \
  240. }
  241. ATOMIC_SIP_OP(atomic, int, subu, ll, sc)
  242. #define arch_atomic_dec_if_positive(v) arch_atomic_sub_if_positive(1, v)
  243. #ifdef CONFIG_64BIT
  244. ATOMIC_SIP_OP(atomic64, s64, dsubu, lld, scd)
  245. #define arch_atomic64_dec_if_positive(v) arch_atomic64_sub_if_positive(1, v)
  246. #endif
  247. #undef ATOMIC_SIP_OP
  248. #endif /* _ASM_ATOMIC_H */