kn02-irq.c 1.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * DECstation 5000/200 (KN02) Control and Status Register
  4. * interrupts.
  5. *
  6. * Copyright (c) 2002, 2003, 2005 Maciej W. Rozycki
  7. */
  8. #include <linux/init.h>
  9. #include <linux/irq.h>
  10. #include <linux/types.h>
  11. #include <asm/dec/kn02.h>
  12. /*
  13. * Bits 7:0 of the Control Register are write-only -- the
  14. * corresponding bits of the Status Register have a different
  15. * meaning. Hence we use a cache. It speeds up things a bit
  16. * as well.
  17. *
  18. * There is no default value -- it has to be initialized.
  19. */
  20. u32 cached_kn02_csr;
  21. static int kn02_irq_base;
  22. static void unmask_kn02_irq(struct irq_data *d)
  23. {
  24. volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
  25. KN02_CSR);
  26. cached_kn02_csr |= (1 << (d->irq - kn02_irq_base + 16));
  27. *csr = cached_kn02_csr;
  28. }
  29. static void mask_kn02_irq(struct irq_data *d)
  30. {
  31. volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
  32. KN02_CSR);
  33. cached_kn02_csr &= ~(1 << (d->irq - kn02_irq_base + 16));
  34. *csr = cached_kn02_csr;
  35. }
  36. static void ack_kn02_irq(struct irq_data *d)
  37. {
  38. mask_kn02_irq(d);
  39. iob();
  40. }
  41. static struct irq_chip kn02_irq_type = {
  42. .name = "KN02-CSR",
  43. .irq_ack = ack_kn02_irq,
  44. .irq_mask = mask_kn02_irq,
  45. .irq_mask_ack = ack_kn02_irq,
  46. .irq_unmask = unmask_kn02_irq,
  47. };
  48. void __init init_kn02_irqs(int base)
  49. {
  50. volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
  51. KN02_CSR);
  52. int i;
  53. /* Mask interrupts. */
  54. cached_kn02_csr &= ~KN02_CSR_IOINTEN;
  55. *csr = cached_kn02_csr;
  56. iob();
  57. for (i = base; i < base + KN02_IRQ_LINES; i++)
  58. irq_set_chip_and_handler(i, &kn02_irq_type, handle_level_irq);
  59. kn02_irq_base = base;
  60. }