ecc-berr.c 7.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Bus error event handling code for systems equipped with ECC
  4. * handling logic, i.e. DECstation/DECsystem 5000/200 (KN02),
  5. * 5000/240 (KN03), 5000/260 (KN05) and DECsystem 5900 (KN03),
  6. * 5900/260 (KN05) systems.
  7. *
  8. * Copyright (c) 2003, 2005 Maciej W. Rozycki
  9. */
  10. #include <linux/init.h>
  11. #include <linux/interrupt.h>
  12. #include <linux/kernel.h>
  13. #include <linux/sched.h>
  14. #include <linux/types.h>
  15. #include <asm/addrspace.h>
  16. #include <asm/bootinfo.h>
  17. #include <asm/cpu.h>
  18. #include <asm/cpu-type.h>
  19. #include <asm/irq_regs.h>
  20. #include <asm/processor.h>
  21. #include <asm/ptrace.h>
  22. #include <asm/traps.h>
  23. #include <asm/dec/ecc.h>
  24. #include <asm/dec/kn02.h>
  25. #include <asm/dec/kn03.h>
  26. #include <asm/dec/kn05.h>
  27. static volatile u32 *kn0x_erraddr;
  28. static volatile u32 *kn0x_chksyn;
  29. static inline void dec_ecc_be_ack(void)
  30. {
  31. *kn0x_erraddr = 0; /* any write clears the IRQ */
  32. iob();
  33. }
  34. static int dec_ecc_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
  35. {
  36. static const char excstr[] = "exception";
  37. static const char intstr[] = "interrupt";
  38. static const char cpustr[] = "CPU";
  39. static const char dmastr[] = "DMA";
  40. static const char readstr[] = "read";
  41. static const char mreadstr[] = "memory read";
  42. static const char writestr[] = "write";
  43. static const char mwritstr[] = "partial memory write";
  44. static const char timestr[] = "timeout";
  45. static const char overstr[] = "overrun";
  46. static const char eccstr[] = "ECC error";
  47. const char *kind, *agent, *cycle, *event;
  48. const char *status = "", *xbit = "", *fmt = "";
  49. unsigned long address;
  50. u16 syn = 0, sngl;
  51. int i = 0;
  52. u32 erraddr = *kn0x_erraddr;
  53. u32 chksyn = *kn0x_chksyn;
  54. int action = MIPS_BE_FATAL;
  55. /* For non-ECC ack ASAP, so that any subsequent errors get caught. */
  56. if ((erraddr & (KN0X_EAR_VALID | KN0X_EAR_ECCERR)) == KN0X_EAR_VALID)
  57. dec_ecc_be_ack();
  58. kind = invoker ? intstr : excstr;
  59. if (!(erraddr & KN0X_EAR_VALID)) {
  60. /* No idea what happened. */
  61. printk(KERN_ALERT "Unidentified bus error %s\n", kind);
  62. return action;
  63. }
  64. agent = (erraddr & KN0X_EAR_CPU) ? cpustr : dmastr;
  65. if (erraddr & KN0X_EAR_ECCERR) {
  66. /* An ECC error on a CPU or DMA transaction. */
  67. cycle = (erraddr & KN0X_EAR_WRITE) ? mwritstr : mreadstr;
  68. event = eccstr;
  69. } else {
  70. /* A CPU timeout or a DMA overrun. */
  71. cycle = (erraddr & KN0X_EAR_WRITE) ? writestr : readstr;
  72. event = (erraddr & KN0X_EAR_CPU) ? timestr : overstr;
  73. }
  74. address = erraddr & KN0X_EAR_ADDRESS;
  75. /* For ECC errors on reads adjust for MT pipelining. */
  76. if ((erraddr & (KN0X_EAR_WRITE | KN0X_EAR_ECCERR)) == KN0X_EAR_ECCERR)
  77. address = (address & ~0xfffLL) | ((address - 5) & 0xfffLL);
  78. address <<= 2;
  79. /* Only CPU errors are fixable. */
  80. if (erraddr & KN0X_EAR_CPU && is_fixup)
  81. action = MIPS_BE_FIXUP;
  82. if (erraddr & KN0X_EAR_ECCERR) {
  83. static const u8 data_sbit[32] = {
  84. 0x4f, 0x4a, 0x52, 0x54, 0x57, 0x58, 0x5b, 0x5d,
  85. 0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c, 0x31, 0x34,
  86. 0x0e, 0x0b, 0x13, 0x15, 0x16, 0x19, 0x1a, 0x1c,
  87. 0x62, 0x64, 0x67, 0x68, 0x6b, 0x6d, 0x70, 0x75,
  88. };
  89. static const u8 data_mbit[25] = {
  90. 0x07, 0x0d, 0x1f,
  91. 0x2f, 0x32, 0x37, 0x38, 0x3b, 0x3d, 0x3e,
  92. 0x43, 0x45, 0x46, 0x49, 0x4c, 0x51, 0x5e,
  93. 0x61, 0x6e, 0x73, 0x76, 0x79, 0x7a, 0x7c, 0x7f,
  94. };
  95. static const char sbestr[] = "corrected single";
  96. static const char dbestr[] = "uncorrectable double";
  97. static const char mbestr[] = "uncorrectable multiple";
  98. if (!(address & 0x4))
  99. syn = chksyn; /* Low bank. */
  100. else
  101. syn = chksyn >> 16; /* High bank. */
  102. if (!(syn & KN0X_ESR_VLDLO)) {
  103. /* Ack now, no rewrite will happen. */
  104. dec_ecc_be_ack();
  105. fmt = KERN_ALERT "%s" "invalid\n";
  106. } else {
  107. sngl = syn & KN0X_ESR_SNGLO;
  108. syn &= KN0X_ESR_SYNLO;
  109. /*
  110. * Multibit errors may be tagged incorrectly;
  111. * check the syndrome explicitly.
  112. */
  113. for (i = 0; i < 25; i++)
  114. if (syn == data_mbit[i])
  115. break;
  116. if (i < 25) {
  117. status = mbestr;
  118. } else if (!sngl) {
  119. status = dbestr;
  120. } else {
  121. volatile u32 *ptr =
  122. (void *)CKSEG1ADDR(address);
  123. *ptr = *ptr; /* Rewrite. */
  124. iob();
  125. status = sbestr;
  126. action = MIPS_BE_DISCARD;
  127. }
  128. /* Ack now, now we've rewritten (or not). */
  129. dec_ecc_be_ack();
  130. if (syn && syn == (syn & -syn)) {
  131. if (syn == 0x01) {
  132. fmt = KERN_ALERT "%s"
  133. "%#04x -- %s bit error "
  134. "at check bit C%s\n";
  135. xbit = "X";
  136. } else {
  137. fmt = KERN_ALERT "%s"
  138. "%#04x -- %s bit error "
  139. "at check bit C%s%u\n";
  140. }
  141. i = syn >> 2;
  142. } else {
  143. for (i = 0; i < 32; i++)
  144. if (syn == data_sbit[i])
  145. break;
  146. if (i < 32)
  147. fmt = KERN_ALERT "%s"
  148. "%#04x -- %s bit error "
  149. "at data bit D%s%u\n";
  150. else
  151. fmt = KERN_ALERT "%s"
  152. "%#04x -- %s bit error\n";
  153. }
  154. }
  155. }
  156. if (action != MIPS_BE_FIXUP)
  157. printk(KERN_ALERT "Bus error %s: %s %s %s at %#010lx\n",
  158. kind, agent, cycle, event, address);
  159. if (action != MIPS_BE_FIXUP && erraddr & KN0X_EAR_ECCERR)
  160. printk(fmt, " ECC syndrome ", syn, status, xbit, i);
  161. return action;
  162. }
  163. int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup)
  164. {
  165. return dec_ecc_be_backend(regs, is_fixup, 0);
  166. }
  167. irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id)
  168. {
  169. struct pt_regs *regs = get_irq_regs();
  170. int action = dec_ecc_be_backend(regs, 0, 1);
  171. if (action == MIPS_BE_DISCARD)
  172. return IRQ_HANDLED;
  173. /*
  174. * FIXME: Find the affected processes and kill them, otherwise
  175. * we must die.
  176. *
  177. * The interrupt is asynchronously delivered thus EPC and RA
  178. * may be irrelevant, but are printed for a reference.
  179. */
  180. printk(KERN_ALERT "Fatal bus interrupt, epc == %08lx, ra == %08lx\n",
  181. regs->cp0_epc, regs->regs[31]);
  182. die("Unrecoverable bus error", regs);
  183. }
  184. /*
  185. * Initialization differs a bit between KN02 and KN03/KN05, so we
  186. * need two variants. Once set up, all systems can be handled the
  187. * same way.
  188. */
  189. static inline void dec_kn02_be_init(void)
  190. {
  191. volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR);
  192. kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR);
  193. kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN);
  194. /* Preset write-only bits of the Control Register cache. */
  195. cached_kn02_csr = *csr | KN02_CSR_LEDS;
  196. /* Set normal ECC detection and generation. */
  197. cached_kn02_csr &= ~(KN02_CSR_DIAGCHK | KN02_CSR_DIAGGEN);
  198. /* Enable ECC correction. */
  199. cached_kn02_csr |= KN02_CSR_CORRECT;
  200. *csr = cached_kn02_csr;
  201. iob();
  202. }
  203. static inline void dec_kn03_be_init(void)
  204. {
  205. volatile u32 *mcr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_MCR);
  206. volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
  207. kn0x_erraddr = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_ERRADDR);
  208. kn0x_chksyn = (void *)CKSEG1ADDR(KN03_SLOT_BASE + IOASIC_CHKSYN);
  209. /*
  210. * Set normal ECC detection and generation, enable ECC correction.
  211. * For KN05 we also need to make sure EE (?) is enabled in the MB.
  212. * Otherwise DBE/IBE exceptions would be masked but bus error
  213. * interrupts would still arrive, resulting in an inevitable crash
  214. * if get_dbe() triggers one.
  215. */
  216. *mcr = (*mcr & ~(KN03_MCR_DIAGCHK | KN03_MCR_DIAGGEN)) |
  217. KN03_MCR_CORRECT;
  218. if (current_cpu_type() == CPU_R4400SC)
  219. *mbcs |= KN4K_MB_CSR_EE;
  220. fast_iob();
  221. }
  222. void __init dec_ecc_be_init(void)
  223. {
  224. if (mips_machtype == MACH_DS5000_200)
  225. dec_kn02_be_init();
  226. else
  227. dec_kn03_be_init();
  228. /* Clear any leftover errors from the firmware. */
  229. dec_ecc_be_ack();
  230. }