reset.c 6.8 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2012 Jonas Gorski <[email protected]>
  7. */
  8. #include <linux/init.h>
  9. #include <linux/export.h>
  10. #include <linux/mutex.h>
  11. #include <linux/err.h>
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <bcm63xx_cpu.h>
  15. #include <bcm63xx_io.h>
  16. #include <bcm63xx_regs.h>
  17. #include <bcm63xx_reset.h>
  18. #define __GEN_RESET_BITS_TABLE(__cpu) \
  19. [BCM63XX_RESET_SPI] = BCM## __cpu ##_RESET_SPI, \
  20. [BCM63XX_RESET_ENET] = BCM## __cpu ##_RESET_ENET, \
  21. [BCM63XX_RESET_USBH] = BCM## __cpu ##_RESET_USBH, \
  22. [BCM63XX_RESET_USBD] = BCM## __cpu ##_RESET_USBD, \
  23. [BCM63XX_RESET_DSL] = BCM## __cpu ##_RESET_DSL, \
  24. [BCM63XX_RESET_SAR] = BCM## __cpu ##_RESET_SAR, \
  25. [BCM63XX_RESET_EPHY] = BCM## __cpu ##_RESET_EPHY, \
  26. [BCM63XX_RESET_ENETSW] = BCM## __cpu ##_RESET_ENETSW, \
  27. [BCM63XX_RESET_PCM] = BCM## __cpu ##_RESET_PCM, \
  28. [BCM63XX_RESET_MPI] = BCM## __cpu ##_RESET_MPI, \
  29. [BCM63XX_RESET_PCIE] = BCM## __cpu ##_RESET_PCIE, \
  30. [BCM63XX_RESET_PCIE_EXT] = BCM## __cpu ##_RESET_PCIE_EXT,
  31. #define BCM3368_RESET_SPI SOFTRESET_3368_SPI_MASK
  32. #define BCM3368_RESET_ENET SOFTRESET_3368_ENET_MASK
  33. #define BCM3368_RESET_USBH 0
  34. #define BCM3368_RESET_USBD SOFTRESET_3368_USBS_MASK
  35. #define BCM3368_RESET_DSL 0
  36. #define BCM3368_RESET_SAR 0
  37. #define BCM3368_RESET_EPHY SOFTRESET_3368_EPHY_MASK
  38. #define BCM3368_RESET_ENETSW 0
  39. #define BCM3368_RESET_PCM SOFTRESET_3368_PCM_MASK
  40. #define BCM3368_RESET_MPI SOFTRESET_3368_MPI_MASK
  41. #define BCM3368_RESET_PCIE 0
  42. #define BCM3368_RESET_PCIE_EXT 0
  43. #define BCM6328_RESET_SPI SOFTRESET_6328_SPI_MASK
  44. #define BCM6328_RESET_ENET 0
  45. #define BCM6328_RESET_USBH SOFTRESET_6328_USBH_MASK
  46. #define BCM6328_RESET_USBD SOFTRESET_6328_USBS_MASK
  47. #define BCM6328_RESET_DSL 0
  48. #define BCM6328_RESET_SAR SOFTRESET_6328_SAR_MASK
  49. #define BCM6328_RESET_EPHY SOFTRESET_6328_EPHY_MASK
  50. #define BCM6328_RESET_ENETSW SOFTRESET_6328_ENETSW_MASK
  51. #define BCM6328_RESET_PCM SOFTRESET_6328_PCM_MASK
  52. #define BCM6328_RESET_MPI 0
  53. #define BCM6328_RESET_PCIE \
  54. (SOFTRESET_6328_PCIE_MASK | \
  55. SOFTRESET_6328_PCIE_CORE_MASK | \
  56. SOFTRESET_6328_PCIE_HARD_MASK)
  57. #define BCM6328_RESET_PCIE_EXT SOFTRESET_6328_PCIE_EXT_MASK
  58. #define BCM6338_RESET_SPI SOFTRESET_6338_SPI_MASK
  59. #define BCM6338_RESET_ENET SOFTRESET_6338_ENET_MASK
  60. #define BCM6338_RESET_USBH SOFTRESET_6338_USBH_MASK
  61. #define BCM6338_RESET_USBD SOFTRESET_6338_USBS_MASK
  62. #define BCM6338_RESET_DSL SOFTRESET_6338_ADSL_MASK
  63. #define BCM6338_RESET_SAR SOFTRESET_6338_SAR_MASK
  64. #define BCM6338_RESET_EPHY 0
  65. #define BCM6338_RESET_ENETSW 0
  66. #define BCM6338_RESET_PCM 0
  67. #define BCM6338_RESET_MPI 0
  68. #define BCM6338_RESET_PCIE 0
  69. #define BCM6338_RESET_PCIE_EXT 0
  70. #define BCM6348_RESET_SPI SOFTRESET_6348_SPI_MASK
  71. #define BCM6348_RESET_ENET SOFTRESET_6348_ENET_MASK
  72. #define BCM6348_RESET_USBH SOFTRESET_6348_USBH_MASK
  73. #define BCM6348_RESET_USBD SOFTRESET_6348_USBS_MASK
  74. #define BCM6348_RESET_DSL SOFTRESET_6348_ADSL_MASK
  75. #define BCM6348_RESET_SAR SOFTRESET_6348_SAR_MASK
  76. #define BCM6348_RESET_EPHY 0
  77. #define BCM6348_RESET_ENETSW 0
  78. #define BCM6348_RESET_PCM 0
  79. #define BCM6348_RESET_MPI 0
  80. #define BCM6348_RESET_PCIE 0
  81. #define BCM6348_RESET_PCIE_EXT 0
  82. #define BCM6358_RESET_SPI SOFTRESET_6358_SPI_MASK
  83. #define BCM6358_RESET_ENET SOFTRESET_6358_ENET_MASK
  84. #define BCM6358_RESET_USBH SOFTRESET_6358_USBH_MASK
  85. #define BCM6358_RESET_USBD 0
  86. #define BCM6358_RESET_DSL SOFTRESET_6358_ADSL_MASK
  87. #define BCM6358_RESET_SAR SOFTRESET_6358_SAR_MASK
  88. #define BCM6358_RESET_EPHY SOFTRESET_6358_EPHY_MASK
  89. #define BCM6358_RESET_ENETSW 0
  90. #define BCM6358_RESET_PCM SOFTRESET_6358_PCM_MASK
  91. #define BCM6358_RESET_MPI SOFTRESET_6358_MPI_MASK
  92. #define BCM6358_RESET_PCIE 0
  93. #define BCM6358_RESET_PCIE_EXT 0
  94. #define BCM6362_RESET_SPI SOFTRESET_6362_SPI_MASK
  95. #define BCM6362_RESET_ENET 0
  96. #define BCM6362_RESET_USBH SOFTRESET_6362_USBH_MASK
  97. #define BCM6362_RESET_USBD SOFTRESET_6362_USBS_MASK
  98. #define BCM6362_RESET_DSL 0
  99. #define BCM6362_RESET_SAR SOFTRESET_6362_SAR_MASK
  100. #define BCM6362_RESET_EPHY SOFTRESET_6362_EPHY_MASK
  101. #define BCM6362_RESET_ENETSW SOFTRESET_6362_ENETSW_MASK
  102. #define BCM6362_RESET_PCM SOFTRESET_6362_PCM_MASK
  103. #define BCM6362_RESET_MPI 0
  104. #define BCM6362_RESET_PCIE (SOFTRESET_6362_PCIE_MASK | \
  105. SOFTRESET_6362_PCIE_CORE_MASK)
  106. #define BCM6362_RESET_PCIE_EXT SOFTRESET_6362_PCIE_EXT_MASK
  107. #define BCM6368_RESET_SPI SOFTRESET_6368_SPI_MASK
  108. #define BCM6368_RESET_ENET 0
  109. #define BCM6368_RESET_USBH SOFTRESET_6368_USBH_MASK
  110. #define BCM6368_RESET_USBD SOFTRESET_6368_USBS_MASK
  111. #define BCM6368_RESET_DSL 0
  112. #define BCM6368_RESET_SAR SOFTRESET_6368_SAR_MASK
  113. #define BCM6368_RESET_EPHY SOFTRESET_6368_EPHY_MASK
  114. #define BCM6368_RESET_ENETSW SOFTRESET_6368_ENETSW_MASK
  115. #define BCM6368_RESET_PCM SOFTRESET_6368_PCM_MASK
  116. #define BCM6368_RESET_MPI SOFTRESET_6368_MPI_MASK
  117. #define BCM6368_RESET_PCIE 0
  118. #define BCM6368_RESET_PCIE_EXT 0
  119. /*
  120. * core reset bits
  121. */
  122. static const u32 bcm3368_reset_bits[] = {
  123. __GEN_RESET_BITS_TABLE(3368)
  124. };
  125. static const u32 bcm6328_reset_bits[] = {
  126. __GEN_RESET_BITS_TABLE(6328)
  127. };
  128. static const u32 bcm6338_reset_bits[] = {
  129. __GEN_RESET_BITS_TABLE(6338)
  130. };
  131. static const u32 bcm6348_reset_bits[] = {
  132. __GEN_RESET_BITS_TABLE(6348)
  133. };
  134. static const u32 bcm6358_reset_bits[] = {
  135. __GEN_RESET_BITS_TABLE(6358)
  136. };
  137. static const u32 bcm6362_reset_bits[] = {
  138. __GEN_RESET_BITS_TABLE(6362)
  139. };
  140. static const u32 bcm6368_reset_bits[] = {
  141. __GEN_RESET_BITS_TABLE(6368)
  142. };
  143. const u32 *bcm63xx_reset_bits;
  144. static int reset_reg;
  145. static int __init bcm63xx_reset_bits_init(void)
  146. {
  147. if (BCMCPU_IS_3368()) {
  148. reset_reg = PERF_SOFTRESET_6358_REG;
  149. bcm63xx_reset_bits = bcm3368_reset_bits;
  150. } else if (BCMCPU_IS_6328()) {
  151. reset_reg = PERF_SOFTRESET_6328_REG;
  152. bcm63xx_reset_bits = bcm6328_reset_bits;
  153. } else if (BCMCPU_IS_6338()) {
  154. reset_reg = PERF_SOFTRESET_REG;
  155. bcm63xx_reset_bits = bcm6338_reset_bits;
  156. } else if (BCMCPU_IS_6348()) {
  157. reset_reg = PERF_SOFTRESET_REG;
  158. bcm63xx_reset_bits = bcm6348_reset_bits;
  159. } else if (BCMCPU_IS_6358()) {
  160. reset_reg = PERF_SOFTRESET_6358_REG;
  161. bcm63xx_reset_bits = bcm6358_reset_bits;
  162. } else if (BCMCPU_IS_6362()) {
  163. reset_reg = PERF_SOFTRESET_6362_REG;
  164. bcm63xx_reset_bits = bcm6362_reset_bits;
  165. } else if (BCMCPU_IS_6368()) {
  166. reset_reg = PERF_SOFTRESET_6368_REG;
  167. bcm63xx_reset_bits = bcm6368_reset_bits;
  168. }
  169. return 0;
  170. }
  171. static DEFINE_SPINLOCK(reset_mutex);
  172. static void __bcm63xx_core_set_reset(u32 mask, int enable)
  173. {
  174. unsigned long flags;
  175. u32 val;
  176. if (!mask)
  177. return;
  178. spin_lock_irqsave(&reset_mutex, flags);
  179. val = bcm_perf_readl(reset_reg);
  180. if (enable)
  181. val &= ~mask;
  182. else
  183. val |= mask;
  184. bcm_perf_writel(val, reset_reg);
  185. spin_unlock_irqrestore(&reset_mutex, flags);
  186. }
  187. void bcm63xx_core_set_reset(enum bcm63xx_core_reset core, int reset)
  188. {
  189. __bcm63xx_core_set_reset(bcm63xx_reset_bits[core], reset);
  190. }
  191. EXPORT_SYMBOL(bcm63xx_core_set_reset);
  192. postcore_initcall(bcm63xx_reset_bits_init);