common.c 4.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Atheros AR71XX/AR724X/AR913X common routines
  4. *
  5. * Copyright (C) 2010-2011 Jaiganesh Narayanan <[email protected]>
  6. * Copyright (C) 2008-2011 Gabor Juhos <[email protected]>
  7. * Copyright (C) 2008 Imre Kaloz <[email protected]>
  8. *
  9. * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
  10. */
  11. #include <linux/kernel.h>
  12. #include <linux/export.h>
  13. #include <linux/types.h>
  14. #include <linux/spinlock.h>
  15. #include <asm/mach-ath79/ath79.h>
  16. #include <asm/mach-ath79/ar71xx_regs.h>
  17. #include "common.h"
  18. static DEFINE_SPINLOCK(ath79_device_reset_lock);
  19. u32 ath79_cpu_freq;
  20. EXPORT_SYMBOL_GPL(ath79_cpu_freq);
  21. u32 ath79_ahb_freq;
  22. EXPORT_SYMBOL_GPL(ath79_ahb_freq);
  23. u32 ath79_ddr_freq;
  24. EXPORT_SYMBOL_GPL(ath79_ddr_freq);
  25. enum ath79_soc_type ath79_soc;
  26. unsigned int ath79_soc_rev;
  27. void __iomem *ath79_pll_base;
  28. void __iomem *ath79_reset_base;
  29. EXPORT_SYMBOL_GPL(ath79_reset_base);
  30. static void __iomem *ath79_ddr_base;
  31. static void __iomem *ath79_ddr_wb_flush_base;
  32. static void __iomem *ath79_ddr_pci_win_base;
  33. void ath79_ddr_ctrl_init(void)
  34. {
  35. ath79_ddr_base = ioremap(AR71XX_DDR_CTRL_BASE,
  36. AR71XX_DDR_CTRL_SIZE);
  37. if (soc_is_ar913x() || soc_is_ar724x() || soc_is_ar933x()) {
  38. ath79_ddr_wb_flush_base = ath79_ddr_base + 0x7c;
  39. ath79_ddr_pci_win_base = 0;
  40. } else {
  41. ath79_ddr_wb_flush_base = ath79_ddr_base + 0x9c;
  42. ath79_ddr_pci_win_base = ath79_ddr_base + 0x7c;
  43. }
  44. }
  45. EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init);
  46. void ath79_ddr_wb_flush(u32 reg)
  47. {
  48. void __iomem *flush_reg = ath79_ddr_wb_flush_base + (reg * 4);
  49. /* Flush the DDR write buffer. */
  50. __raw_writel(0x1, flush_reg);
  51. while (__raw_readl(flush_reg) & 0x1)
  52. ;
  53. /* It must be run twice. */
  54. __raw_writel(0x1, flush_reg);
  55. while (__raw_readl(flush_reg) & 0x1)
  56. ;
  57. }
  58. EXPORT_SYMBOL_GPL(ath79_ddr_wb_flush);
  59. void ath79_ddr_set_pci_windows(void)
  60. {
  61. BUG_ON(!ath79_ddr_pci_win_base);
  62. __raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0x0);
  63. __raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 0x4);
  64. __raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 0x8);
  65. __raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 0xc);
  66. __raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 0x10);
  67. __raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 0x14);
  68. __raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 0x18);
  69. __raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 0x1c);
  70. }
  71. EXPORT_SYMBOL_GPL(ath79_ddr_set_pci_windows);
  72. void ath79_device_reset_set(u32 mask)
  73. {
  74. unsigned long flags;
  75. u32 reg;
  76. u32 t;
  77. if (soc_is_ar71xx())
  78. reg = AR71XX_RESET_REG_RESET_MODULE;
  79. else if (soc_is_ar724x())
  80. reg = AR724X_RESET_REG_RESET_MODULE;
  81. else if (soc_is_ar913x())
  82. reg = AR913X_RESET_REG_RESET_MODULE;
  83. else if (soc_is_ar933x())
  84. reg = AR933X_RESET_REG_RESET_MODULE;
  85. else if (soc_is_ar934x())
  86. reg = AR934X_RESET_REG_RESET_MODULE;
  87. else if (soc_is_qca953x())
  88. reg = QCA953X_RESET_REG_RESET_MODULE;
  89. else if (soc_is_qca955x())
  90. reg = QCA955X_RESET_REG_RESET_MODULE;
  91. else if (soc_is_qca956x() || soc_is_tp9343())
  92. reg = QCA956X_RESET_REG_RESET_MODULE;
  93. else
  94. BUG();
  95. spin_lock_irqsave(&ath79_device_reset_lock, flags);
  96. t = ath79_reset_rr(reg);
  97. ath79_reset_wr(reg, t | mask);
  98. spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
  99. }
  100. EXPORT_SYMBOL_GPL(ath79_device_reset_set);
  101. void ath79_device_reset_clear(u32 mask)
  102. {
  103. unsigned long flags;
  104. u32 reg;
  105. u32 t;
  106. if (soc_is_ar71xx())
  107. reg = AR71XX_RESET_REG_RESET_MODULE;
  108. else if (soc_is_ar724x())
  109. reg = AR724X_RESET_REG_RESET_MODULE;
  110. else if (soc_is_ar913x())
  111. reg = AR913X_RESET_REG_RESET_MODULE;
  112. else if (soc_is_ar933x())
  113. reg = AR933X_RESET_REG_RESET_MODULE;
  114. else if (soc_is_ar934x())
  115. reg = AR934X_RESET_REG_RESET_MODULE;
  116. else if (soc_is_qca953x())
  117. reg = QCA953X_RESET_REG_RESET_MODULE;
  118. else if (soc_is_qca955x())
  119. reg = QCA955X_RESET_REG_RESET_MODULE;
  120. else if (soc_is_qca956x() || soc_is_tp9343())
  121. reg = QCA956X_RESET_REG_RESET_MODULE;
  122. else
  123. BUG();
  124. spin_lock_irqsave(&ath79_device_reset_lock, flags);
  125. t = ath79_reset_rr(reg);
  126. ath79_reset_wr(reg, t & ~mask);
  127. spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
  128. }
  129. EXPORT_SYMBOL_GPL(ath79_device_reset_clear);